Texas Instruments | SN65HVDA54x-Q1, SN65HVDA54x-5-Q1 5-V Can Transceiver With I/O Level Adapting and Low-Power Mode Supply Optimization (Rev. D) | Datasheet | Texas Instruments SN65HVDA54x-Q1, SN65HVDA54x-5-Q1 5-V Can Transceiver With I/O Level Adapting and Low-Power Mode Supply Optimization (Rev. D) Datasheet

Texas Instruments SN65HVDA54x-Q1, SN65HVDA54x-5-Q1 5-V Can Transceiver With I/O Level Adapting and Low-Power Mode Supply Optimization (Rev. D) Datasheet
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SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
SN65HVDA54x-Q1, SN65HVDA54x-5-Q1 5-V Can Transceiver
With I/O Level Adapting and Low-Power Mode Supply Optimization
1 Features
•
•
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
– Device MM ESD Classification Level M4
Meets or Exceeds the Requirements of
ISO 11898-2 and ISO 11898-5
GIFT/ICT Compliant
ESD Protection up to ±12 kV (Human-Body
Model) on Bus Pins
I/O Voltage Level Adapting
– SN65HVDA54x: Adaptable I/O Voltage Range
(VIO) From 3 V to 5.33 V
– SN65HVDA54x-5: 5 V VCC Device Version
Operating Modes:
– Normal Mode: All Devices
– Low Power Standby Mode (VCC Not Required,
Only VIO Supply Needed Saving System
Power)
– SN65HVDA540: No Wake Up
– SN65HVDA541: RXD Wake Up Request
– Silent (Receive Only) Mode: HVDA542
High Electromagnetic Compliance (EMC)
Protection
– Undervoltage Protection on VIO and VCC
– Bus-Fault Protection of –27 V to 40 V
HVDA54x Functional Block Diagram
– TXD Dominant State Time Out
– RXD Wake Up Request Lock Out on CAN Bus
Stuck Dominant Fault (HVDA541)
– Thermal Shutdown Protection
– Power-Up/Down Glitch-Free Bus I/O
– High Bus Input Impedance When Unpowered
(No Bus Load)
2 Applications
•
•
•
•
•
SAE J2284 High-Speed CAN for Automotive
Applications
SAE J1939 Standard Data Bus Interface
GMW3122 Dual-Wire CAN Physical Layer
ISO 11783 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
3 Description
The SN65HVDA54x-Q1 and SN65HVDA54x-5-Q1
devices, known as the HVDA54x and HVDA54x-5
respectively, are designed and qualified for use in
automotive applications and meets or exceeds the
specifications of the ISO 11898 High Speed CAN
(Controller Area Network) Physical Layer standard
(transceiver).
Device Information(1)
PART NUMBER
PACKAGE
SN65HVDA54x-Q1,
SN65HVDA54x-5-Q1
SOIC (8)
VIO/NC
HVDA54x-5 Functional Block Diagram
(See Note A)
VIO
DOMINANT
TIME-OUT
VIO
STB
DRIVER
6
(See
Note B)
8
CANH
TXD
1
DOMINANT
TIME-OUT
DRIVER
6
CANH
CANL
MODE SELECT
LOGIC
OUTPUT
S
8
MUX
RXD
VCC
OVER
TEMPERATURE
7
CANL
UNDER
VOLTAGE
4
3
(See
Note B)
OVER
TEMPERATURE
1
VCC
5
VCC
7
TXD
VIO/NC
3
(See
Note B)
VIO
HVDA542
VCC
5
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HVDA540 / HVDA541
(See Note A)
BODY SIZE (NOM)
UNDER
VOLTAGE
WAKE UP LOGIC /
MONITOR
Low Power Standby Bus
Receiver and Monitor
HVDA541
MODE SELECT
4
RXD
LOGIC
OUTPUT
2
GND
Copyright © 2016, Texas Instruments Incorporated
HVDA54x devices pin 5 is VIO. HVDA54x-5
devices pin 5 is NC and VIO is internally
connected to VCC.
2
GND
Copyright © 2016, Texas Instruments Incorporated
HVDA54x-5 devices: VIO is internally
connected to VCC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Power Dissipation Ratings ........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagrams ..................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Applications ................................................ 21
9.3 System Examples ................................................... 23
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Examples................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2012) to Revision D
Page
•
Changed device numbers From: SN65HVD54x-Q1 To: HVD54x-Q1 .................................................................................... 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed Ordering Information table, see POA at the end of the data sheet........................................................................ 4
Changes from Revision B (September 2010) to Revision C
Page
•
Deleted DSJ package info ...................................................................................................................................................... 1
•
Deleted DSJ package info ...................................................................................................................................................... 3
•
Added note in line 4.5 Test Conditions, "TA = –40°C, 25°C, 125°C"...................................................................................... 5
•
Deleted DSJ package info ...................................................................................................................................................... 8
•
Deleted DSJ (VSON) package info ...................................................................................................................................... 17
2
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA542-Q1 SN65HVDA540-5-Q1
SN65HVDA541-5-Q1 SN65HVDA542-5-Q1
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
www.ti.com
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
5 Pin Configuration and Functions
HVDA54x D Package
8-Pin SOIC
Top View
HVDA54x-5 D Package
8-Pin SOIC
Top View
TXD
1
8
STB/S
TXD
1
8
STB/S
GND
2
7
CANH
GND
2
7
CANH
VCC
3
6
CANL
6
CANL
4
5
VIO
VCC
3
RXD
RXD
4
5
NC
Not to scale
Not to scale
Pin Functions
PIN
NAME
HVDA54x
HVDA54x-5
CANH
7
7
CANL
6
GND
2
NC
TYPE
DESCRIPTION
I/O
High level CAN bus line
6
I/O
Low level CAN bus line
2
GND
—
5
Supply
RXD
4
4
O
CAN receive data output (low in dominant bus state, high in recessive bus state)
STB/S
8
8
I
Mode select:
STB, Standby mode (HVDA540/541) select pin (active high)
S, Silent mode (HVDA542) select pin (active high)
TXD
1
1
I
CAN transmit data input (low for dominant bus state, high for recessive bus state)
VCC
3
3
Supply
Transceiver 5V supply voltage
VIO
5
—
Supply
HVDA54x: Transceiver logic level (IO) supply voltage
HVDA54x-5: No connect
Copyright © 2009–2016, Texas Instruments Incorporated
Ground connection
HVDA54x: Transceiver logic level (IO) supply voltage
HVDA54x-5: No connect
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SN65HVDA541-5-Q1 SN65HVDA542-5-Q1
3
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
VCC
Supply voltage
–0.3
6
V
VIO
I/O supply voltage
–0.3
6
V
Voltage at bus terminals (CANH, CANL)
–27
40
V
20
mA
IO
Receiver output current (RXD)
VI
Voltage input (TXD, STB, S)
HVDA54x
–0.3
6 V and VI ≤
VIO + 0.3
V
HVDA54x-5
–0.3
6
V
–40
150
°C
260
°C
TJ
Operating virtual-junction temperature
TLEAD
Lead temperature (soldering, 10 seconds)
Tstg
Storage temperature
(1)
(2)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
Electrostatic
discharge
V(ESD)
±4000
Pins 6 and 7 (2)
±12000
Charged-device model (CDM), per AEC Q100-011
±1000
Machine model
±7000
IEC 61000-4-2 contact discharge (3)
(1)
(2)
(3)
All pins except 6 and 7
Pins 6 and 7 to pin 2
UNIT
V
±7000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
HBM test method based on AEC-Q100-002, CANH and CANL bus pins stressed with respect to each other and GND.
IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system level configurations will lead to different results.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
4.68
5.33
V
3
5.33
V
–12
12
V
0.7 × VIO
VIO
V
0 0.3 × VIO
V
VCC
Supply voltage
VIO
I/O supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage
TXD, STB, S (for HVD54x-5: VIO = VCC)
VIL
Low-level input voltage
TXD, STB, S (for HVD54x-5: VIO = VCC)
VID
Differential input voltage,
bus
Between CANH and CANL
–6
IOH
High-level output current
RXD
–2
IOL
Low-level output current
RXD
TA
Operating ambient free-air
temperature
See Thermal Information and Power Dissipation Ratings
4
Submit Documentation Feedback
–40
6
V
mA
2
mA
125
°C
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA542-Q1 SN65HVDA540-5-Q1
SN65HVDA541-5-Q1 SN65HVDA542-5-Q1
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
www.ti.com
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
6.4 Thermal Information
THERMAL METRIC
HVDA54x,
HVDA54x-5-Q1
(1)
UNIT
D (SOIC)
8 PINS
Low-K thermal resistance
140
High-K thermal resistance
112
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
56
°C/W
RθJB
Junction-to-board thermal resistance
50
°C/W
ψJT
Junction-to-top characterization parameter
13
°C/W
ψJB
Junction-to-board characterization parameter
55
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices VIO = VCC
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
SUPPLY CHARACTERISTICS (HVDA54x)
Standby
mode
STB at VIO, VCC = 5.33 V, VIO = 3 V,
(HVDA540/54 TXD at VIO (2)
1 Only)
5-V supply
current
ICC
5
Normal mode
TXD at 0 V, 60-Ω load, STB / S at 0 V
(Dominant)
50
70
Normal mode TXD at VIO, No load, STB / S at 0 V or S at
(Recessive)
VIO
5.5
10
Silent Mode
(HVDA542
only)
5.5
10
7
15
TXD at VIO, No load, STB / S at 0 V or S at
VIO
Standby
STB at VIO , VCC = 5.33 V or 0 V, RXD
mode
floating, TXD at VIO
(HVDA540/54
TA = –40°C, 25°C, 125°C (3)
1 Only)
Normal mode
I/O supply current (recessive or
dominant)
VCC = 5.33 V, RXD floating, TXD at 0 V or
and Silent
VIO. Normal Mode: STB or S at 0 V. Silent
Mode
Mode (HVDA542): S at VIO.
(HVDA542
Only)
IIO
UVVCC
Undervoltage detection on VCC
for forced standby mode
Undervoltage detection on VIO for
forced standby mode
VHYS(UVVIO)
Hysteresis voltage for
undervoltage detection on UVVIO
for forced standby mode
(1)
(2)
(3)
mA
µA
3.2
Hysteresis voltage for
VHYS(UVVCC) undervoltage detection on UVVCC
for standby mode
UVVIO
µA
75
300
3.6
4
200
1.9
2.45
V
mV
2.95
130
V
mV
All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 3.3 V.
The VCC supply is not needed during standby mode so in the application ICC in standby mode may be zero. If the VCC supply remains,
then ICC is per specification with VCC.
See SN65HVDA54x-Q1 Errata .
Copyright © 2009–2016, Texas Instruments Incorporated
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5
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
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Electrical Characteristics (continued)
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices VIO = VCC
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
SUPPLY CHARACTERISTICS (HVDA54x-5)
Standby
mode
STB at VCC, VCC = 5.33 V, TXD at VCC
(HVDA5405/541-5 Only)
5-V supply
current
ICC
(2)
Normal mode
TXD at 0 V, 60-Ω load, STB / S at 0 V
(Dominant)
50
70
Normal mode TXD at VIO, No load, STB / S at 0 V or S at
(Recessive)
VIO
5.5
10
Silent Mode
(HVDA542
only)
5.5
10
3.6
4
TXD at VIO, No load, STB / S at 0 V or S at
VIO
Undervoltage detection on VCC
for forced standby mode
UVVCC
20
3.2
Hysteresis voltage for
VHYS(UVVCC) undervoltage detection on UVVCC
for standby mode
240
µA
mA
V
mV
DEVICE SWITCHING CHARACTERISTICS: PROPAGATION TIME (LOOP TIME TXD TO RXD)
Total loop delay, driver input
tPROP(LOOP1) (TXD) to receiver output (RXD),
recessive to dominant
tPROP(LOOP2)
Total loop delay, driver input
(TXD) to receiver output (RXD),
dominant to recessive
70
230
Figure 9, STB at 0 V
ns
70
230
2.9
4.5
0.8
1.75
DRIVER ELECTRICAL CHARACTERISTICS
VO(D)
Bus output
voltage
(dominant)
CANH
VO(R)
Bus output voltage (recessive)
VI = VIO, VIO = 3 V, STB at 0 V or S at X (4),
RL = 60 Ω, See Figure 2 and Figure 15
VO(STBY)
Bus output voltage, standby
mode (HVDA540, HVDA541
only)
STB / S at VIO, RL = 60 Ω,
See Figure 2 and Figure 15
VOD(D)
Differential output voltage
(dominant)
CANL
Differential output voltage
(recessive)
VOD(R)
VI = 0 V, STB / S at 0 V, RL = 60 Ω,
See Figure 2 and Figure 15
2
2.5
V
3
V
–0.1
0.1
V
VI = 0 V, RL = 60 Ω, STB / S at 0 V,
See Figure 2, Figure 15, and Figure 3
1.5
3
VI = 0 V, RL = 45 Ω, STB / S at 0 V,
See Figure 2, Figure 15, and Figure 3
1.4
3
–0.012
0.012
–0.5
0.05
V
VI = 3 V, STB / S at 0 V, RL = 60 Ω, See
Figure 2 and Figure 15
VI = 3 V, STB / S at 0 V, No load
V
VSYM
Output symmetry (dominant or
recessive) (VO(CANH) + VO(CANL))
STB / S at 0 V, RL = 60 Ω,
See Figure 12
0.9 VCC
VCC
1.1 VCC
V
VOC(SS)
Steady-state common-mode
output voltage
STB / S at 0 V, RL = 60 Ω,
See Figure 8
2
2.5
3
V
ΔVOC(SS)
Change in steady-state common- STB / S at 0 V, RL = 60 Ω,
mode output voltage
See Figure 8
IOS(SS)_DOM
Short-circuit steady-state output
current, Dominant
(4)
6
40
VCANH = 0 V, CANL open, TXD = low,
See Figure 11
mV
–100
VCANL = 32 V, CANH open, TXD = low, See
Figure 11
mA
100
For the HVDA542 device the bus output voltage (recessive) will be the same if the device is in normal mode with S pin at 0 V or if the
device is in silent mode with the S pin at HIGH.
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SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
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SLLS804D – MARCH 2009 – REVISED AUGUST 2016
Electrical Characteristics (continued)
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices VIO = VCC
PARAMETER
IOS(SS)_REC
CO
Short-circuit steady-state output
current, Recessive
Output capacitance
TEST CONDITIONS
MIN
TYP (1)
MAX
–20 V ≤ VCANH ≤ 32 V, CANL open,
TXD = high, See Figure 11
–10
10
–20 V ≤ VCANL ≤ 32 V, CANH open,
TXD = high, See Figure 11
–10
10
UNIT
mA
See receiver input capacitance
DRIVER SWITCHING CHARACTERISTICS
tPLH
Propagation delay time, low-tohigh level output
STB / S at 0 V, See Figure 4
65
ns
tPHL
Propagation delay time, high-tolow level output
STB / S at 0 V, See Figure 4
50
ns
tR
Differential output signal rise time STB / S at 0 V, See Figure 4
25
ns
tF
Differential output signal fall time
STB / S at 0 V, See Figure 4
55
ns
tEN
Enable time from standby or
silent mode to normal mode
dominant
See Figure 7
t(DOM) (5)
Dominant time out
See Figure 10
300
20
µs
400
700
µs
800
900
mV
RECEIVER ELECTRICAL CHARACTERISTICS
VIT+
Positive-going input threshold
voltage, normal mode
STB / S at 0 V, See Table 1
VIT–
Negative-going input threshold
voltage, normal mode
STB / S at 0 V, See Table 1
Vhys
Hysteresis voltage (VIT+ – VIT–)
VIT(STBY)
Input threshold voltage,
standby mode (HVDA541 only)
STB at VIO
II(OFF_LKG)
Power-off (unpowered) bus input
leakage current
CANH = CANL = 5 V, VCC at 0 V,
VIO at 0 V, TXD at 0 V
CI
Input capacitance to ground
(CANH or CANL)
HVDA54x: TXD at VIO, VIO at 3.3 V.
HVDA54x-5: TXD at VCC
VI = 0.4 sin (4E6πt) + 2.5 V
13
pF
CID
Differential input capacitance
HVDA54x: TXD at VIO, VIO at 3.3 V.
HVDA54x-5: TXD at VCC
VI = 0.4 sin(4E6πt)
5
pF
RID
Differential input resistance
RIN
Input resistance (CANH or
CANL)
RI(M)
Input resistance matching
[1 – ®IN(CANH)/RIN(CANL))] × 100%
HVDA54x: TXD at VIO, VIO = 3.3 V,
STB at 0 V
HVDA54x-5: TXD at VCC, STB at 0 V
V(CANH) = V(CANL)
500
650
mV
100
125
mV
400
29
1150
mV
3
µA
80
kΩ
14.5
25
40
kΩ
–3
0
3
%
RECEIVER SWITCHING CHARACTERISTICS
tPLH
Propagation delay time, low-tohigh-level output
STB / S at 0 V , See Figure 6
95
ns
tPHL
Propagation delay time, high-tolow-level output
STB / S at 0 V , See Figure 6
60
ns
tR
Output signal rise time
STB / S at 0 V , See Figure 6
13
ns
tF
Output signal fall time
STB / S at 0 V , See Figure 6
10
ns
(5)
The TXD dominant time out (t(DOM)) disables the driver of the transceiver once the TXD has been dominant longer than t(DOM), which
releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the
minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case,
where five successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t(DOM) = 11 bits / 300 µs = 37 kbps
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Electrical Characteristics (continued)
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices VIO = VCC
PARAMETER
TEST CONDITIONS
tBUS
Dominant time required on bus
for wake-up from standby
(HVDA541 only)
tCLEAR
Recessive time on the bus to
clear the standby mode receiver
output (RXD) if standby mode is
entered while bus is dominant
(HVDA541 only)
MIN
TYP (1)
MAX
UNIT
1.5
5
µs
1.5
5
µs
STB at VIO, See Figure 17 and Figure 18
TXD PIN CHARACTERISTICS
VIH
High-level input voltage
HVD54x-5: VIO = VCC
VIL
Low-level input voltage
HVD54x-5: VIO = VCC
0.7 × VIO
IIH
High-level input current
HVDA54x: TXD at VIO HVDA54x-5: TXD at
VCC
IIL
Low-level input current
TXD at 0 V
V
0.3 × VIO
V
–2
2
µA
–100
–7
µA
RXD PIN CHARACTERISTICS
VOH
High-level output voltage
IO = –2 mA, See Figure 6 HVD54x-5:
VIO = VCC
VOL
Low-level output voltage
IO = 2 mA, See Figure 6 HVD54x-5:
VIO = VCC
0.8 × VIO
V
0.2 × VIO
V
STB PIN CHARACTERISTICS (HVDA540 AND HVDA541 ONLY)
VIH
High-level input voltage
HVD54x-5: VIO = VCC
VIL
Low-level input voltage
HVD54x-5: VIO = VCC
0.7 × VIO
IIH
High-level input current
HVDA54x: STB at VIO HVDA54x-5: STB at
VCC
IIL
Low-level input current
STB at 0 V
V
0.3 × VIO
V
2
µA
–2
–20
µA
0.7 × VIO
V
S PIN CHARACTERISTICS (HVDA542 ONLY)
VIH
High-level input voltage
HVD54x-5: VIO = VCC
VIL
Low-level input voltage
HVD54x-5: VIO = VCC
IIH
High-level input current
HVDA54x: S at VIO HVDA54x-5: S at VCC
IIL
Low-level input current
S at 0 V
0.3 × VIO
V
30
µA
2
µA
–2
Thermal shutdown temperature
185
°C
6.6 Power Dissipation Ratings
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices VIO = VCC
MIN
PD
8
Average power
dissipation
VCC = 5 V, VIO = VCC, TJ = 27°C, RL = 60 Ω,
STB at 0 V, Input to TXD at 500 kHz,
50% duty cycle square wave,
CL at RXD = 15 pF
TYP
UNIT
140
mW
VCC = 5.33 V, VIO = VCC, TJ = 130°C,
RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz,
50% duty cycle square wave, CL at RXD = 15 pF
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MAX
215
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6.7 Typical Characteristics
3.00E+00
2.50E+00
VOD
2.00E+00
1.50E+00
1.00E+00
5.00E-01
0.00E+00
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
VCC
C001
STB = 0 V RL= 60 Ω CL= Open Rcm= open
Temp = 25°C
Figure 1. HVDA540 VCC vs VOD from 4.5 V to 5.5 V
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7 Parameter Measurement Information
Figure 2. Driver Voltage, Current, and Test Definition
Figure 3. Driver VOD Test Circuit
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
C.
For HVDA54x-5 device versions, VIO = VCC.
Figure 4. Driver Test Circuit and Voltage Waveforms
Figure 5. Receiver Voltage and Current Definitions
10
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Parameter Measurement Information (continued)
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
C.
C. For HVDA54x-5 device versions VIO = VCC.
Figure 6. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
VCANH
OUTPUT
VCANL
|VID|
R
–11.1 V
–12 V
900 mV
L
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
6V
H
6V
12 V
6V
H
Open
Open
X
H
VOL
VOH
A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 25 kHz, 50% duty cycle.
C.
C. For HVDA54x-5 device versions VIO = VCC.
Figure 7. tEN Test Circuit and Waveforms
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A.
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All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. Common-Mode Output Voltage Test and Waveforms
A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
C.
For HVDA54x-5 device versions, VIO = VCC.
Figure 9. tPROP(LOOP) Test Circuit and Waveform
A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
C.
For HVDA54x-5 device versions, VIO = VCC.
Figure 10. TXD Dominant Time Out Test Circuit and Waveforms
12
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A.
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
For HVDA54x-5 device versions VIO = VCC.
Figure 11. Driver Short-Circuit Current Test and Waveforms
A.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr/tf ≤ 6 ns,
Pulse Repetition Rate (PRR) = 250 kHz, 50% duty cycle.
Figure 12. Driver Output Symmetry Test Circuit
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8 Detailed Description
8.1 Overview
The device meets or exceeds the specifications of the ISO 11898 High Speed CAN (Controller Area Network)
Physical Layer standard (transceiver). This device provides CAN transceiver functions: differential transmit
capability to the bus and differential receive capability at data rates up to 1 megabit per second (Mbps). The
device includes many protection features providing device and CAN network robustness.
8.2 Functional Block Diagrams
HVDA540 / HVDA541
(See Note A)
VIO/NC
VCC
3
5
VCC
(See
Note B)
VIO
OVER
TEMPERATURE
7
TXD
1
DOMINANT
TIME-OUT
VIO
STB
DRIVER
6
(See
Note B)
8
CANH
CANL
MODE SELECT
RXD
4
LOGIC
OUTPUT
MUX
UNDER
VOLTAGE
WAKE UP LOGIC /
MONITOR
Low Power Standby Bus
Receiver and Monitor
HVDA541
2
GND
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HVDA54x devices pin 5 is VIO. HVDA54x-5 devices pin 5 is NC and VIO is internally connected to VCC.
Figure 13. HVDA54x Functional Block Diagram
14
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Functional Block Diagrams (continued)
HVDA542
(See Note A)
VIO/NC
VCC
3
5
VCC
(See
Note B)
VIO
OVER
TEMPERATURE
7
TXD
S
1
DOMINANT
TIME-OUT
8
DRIVER
6
CANH
CANL
MODE SELECT
UNDER
VOLTAGE
4
RXD
LOGIC
OUTPUT
2
GND
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HVDA54x-5 devices: VIO is internally connected to VCC
Figure 14. HVDA54x-5 Functional Block Diagram
8.3 Feature Description
8.3.1 Digital Inputs and Outputs
The HVDA54x devices have an I/O supply voltage input pin (VIO) to ratiometrically level shift the digital logic input
and output levels with respect to VIO for compatibility with protocol controllers having I/O supply voltages between
3 V and 5.33 V.
The HVDA54x-5 devices have a single VCC supply (5 V). The digital logic input and output levels for these
devices are with respect to VCC for compatibility with protocol controllers having I/O supply voltages between
4.68 V and 5.33 V.
8.3.2 TXD Dominant State Time Out
During normal mode, the only mode where the CAN driver is active, the TXD dominant time out circuit prevents
the transceiver from blocking network communication in event of a hardware or software failure where TXD is
held dominant longer than the time-out period t(DOM). The dominant time out circuit is triggered by a falling edge
on TXD. If no rising edge is seen before the time out constant of the circuit expires (t(DOM)) the CAN bus driver is
disabled freeing the bus for communication between other network nodes. The CAN driver is reactivated when a
recessive signal is seen on TXD pin, thus clearing the dominant state time out. The CAN bus pins is biased to
recessive level during a TXD dominant state time out.
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Feature Description (continued)
NOTE
The maximum dominant TXD time allowed by the TXD Dominant state time out limits the
minimum possible data rate of the device. The CAN protocol allows a maximum of eleven
successive dominant bits (on TXD) for the worst case, where five successive dominant
bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits
the minimum bit rate.
The minimum bit rate may be calculated in Equation 1:
Minimum Bit Rate = 11/t(DOM)
(1)
8.3.3 Thermal Shutdown
If the junction temperature of the device exceeds the thermal shut down threshold the device will turn off the
CAN driver circuits. This condition is cleared once the temperature drops below the thermal shut down
temperature of the device. The CAN bus pins will be biased to recessive level during a thermal shutdown.
8.3.4 Undervoltage Lockout and Unpowered Device
Both of the supply pins have undervoltage detection which place the device in forced standby mode to protect
the bus during an undervoltage event on either the VCC or VIO supply pins. If VIO is undervoltage the RXD pin is
tri-stated and the device does not pass any wake-up signals from the bus to the RXD pin. Since the device is
placed into forced standby mode the CAN bus pins have a common mode bias to ground protecting the CAN
network, see Figure 15 and Figure 16.
The device is designed to be an ideal passive load to the CAN bus if it is unpowered. The bus pins (CANH,
CANL) have extremely low leakage currents when the device is unpowered so they will not load down the bus
but rather be no load. This is critical, especially if some nodes of the network will be unpowered while the rest of
the network remains in operation.
NOTE
Once an undervoltage condition is cleared and the VCC and VIO have returned to valid
levels the device will typically need 300 µs to transition to normal operation.
Table 2. Undervoltage Protection
DEVICE
VCC
VIO
HVDA540
HVDA541
Bad
Good
HVDA542
(3)
16
BUS
RXD
Forced Standby Mode
Common mode
bias to GND (1)
HIGH (Recessive)
Forced Standby Mode
Common mode
bias to GND (1)
Mirrors bus state via wake-up
filter (2)
Forced Standby Mode
Common mode
bias to GND (1)
HIGH (Recessive)
HVDA54x
Good
Bad
Forced Standby Mode (3)
Common mode
bias to GND (1)
tri-state
HVDA54x-5
Bad
N/A
Forced Standby Mode
Common mode
bias to GND (1)
HIGH (Recessive) or tri-state
Unpowered
No Load
High Z
All Devices
(1)
(2)
DEVICE STATE
Unpowered
See Figure 15 and Figure 16 for common mode bias information.
See Figure 17 and Figure 18 for operation of the low power wake up receiver and bus monitor for RXD Wake Up Request behavior and
Table 5 for the wake up receiver threshold levels.
When VIO is undervoltage, the device is forced into standby mode with respect to the CAN bus since there is not a valid digital reference
to determine the digital I/O states or power the wake-up receiver.
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8.3.5 Floating Pins
The device has integrated pullup and pulldowns on critical pins to place the device into known states if the pins
float. The TXD pin is pulled up to VIO to force a recessive input level if the pin floats. The STB is pulled up to the
IO supply pin, VIO(HVDA540 and HVDA541), or VCC (HVDA540-5 and HVDA541-5) to force the device in
standby mode (low power) if the pin floats. The S pin is pulled down to GND to force the device into normal
mode if the pin floats (HVDA542 and HVDA542-5).
8.3.6 CAN Bus Short-Circuit Current Limiting
The device has several protection features that limit the short circuit current when a CAN bus line is shorted.
These include CAN driver current limiting (dominant and recessive) and TXD dominant state time out to prevent
continuously driving dominant. During CAN communication the bus switches between dominant and recessive
states, thus the short circuit current may be viewed either as the current during each bus state or as a DC
average current. For system current and power considerations in termination resistance and common mode
choke ratings the average short circuit current should be used. The device has TXD dominant state time out
which prevents permanently having the higher short circuit current of dominant state. The CAN protocol also has
forced state changes and recessive bits such as bit stuffing, control fields, and interframe space. These ensure
there is a minimum recessive amount of time on the bus even if the data field contains a high percentage of
dominant bits.
NOTE
The short circuit current of the bus depends on the ratio of recessive to dominant bits and
their respective short circuit currents.
The average short circuit current may be calculated by Equation 2:
IOS(AVG) = %Transmit * [(%REC_Bits * IOS(SS)_REC) + (%DOM_Bits * IOS(SS)_DOM)] + [%Receive * IOS(SS)_REC]
where
•
•
•
•
•
•
•
IOS(AVG) is the average short circuit current,
%Transmit is the percentage the node is transmitting CAN messages,
%Receive is the percentage the node is receiving CAN messages,
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages,
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages,
IOS(SS)_REC is the recessive steady state short circuit current
and IOS(SS)_DOM is the dominant steady-state short circuit current.
(2)
8.4 Device Functional Modes
The device has two main operating modes: normal mode (all devices) and standby mode (HVDA540 / 541) or
silent mode (HVDA542). Operating mode selection is made through the STB (HVDA540 / 541) or the S
(HVDA542) input pin.
Table 3. Operating Modes
(1)
(2)
DEVICE
STB / S
MODE
DRIVER
RECEIVER
RXD Pin
All Devices
LOW
Normal Mode
Enabled (On)
Enabled (On)
Mirrors bus state (1)
HVDA540
HIGH
Standby Mode (No Wake Up)
Disabled (Off)
Disabled (Off)
Recessive (HIGH)
Mirrors bus state via wakeup filter (2)
Mirrors bus state (1)
HVDA541
HIGH
Standby Mode (RXD Wake Up
Request)
Disabled (Off)
Low power wake-up
receiver and bus monitor
enabled
HVDA542
HIGH
Silent Mode
Disabled (Off)
Enabled (On)
Mirrors bus state: LOW if CAN bus is dominant, HIGH if CAN bus is recessive.
See Figure 17 and Figure 18 for operation of the low power wake up receiver and bus monitor for RXD Wake Up Request behavior and
Table 5 for the wake up receiver threshold levels.
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8.4.1 Bus States by Mode
The CAN bus has three valid states during powered operation depending on the mode of the device. In normal
mode the bus may be dominant (logic LOW) where the bus lines are driven differentially apart or recessive (logic
HIGH) where the bus lines are biased to VCC/2 via the high-ohmic internal input resistors RIN of the receiver. The
third state is low power standby mode where the bus lines will be biased to GND via the high-ohmic internal input
resistors RIN of the receiver.
Typical Bus Voltage
CANH
Low Power
Standby Mode
Normal & Silent Mode
VCC/2
A
RXD
CANH
B
CANL
Vdiff
Vdiff
CANL
A: Normal Mode
B: Low Power Standby Mode
Recessive
Dominant
Recessive
Time, t
Figure 15. Bus States (Physical Bit Representation)
Figure 16. Simplified Common Mode Bias and
Receiver Implementation
8.4.2 Normal Mode
This is the normal operating mode of the device. It is selected by setting STB or S low. The CAN driver and
receiver are fully operational and CAN communication is bidirectional. The driver is translating a digital input on
TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH
and CANL to a digital output on RXD. In recessive state the CAN bus pins (CANH and CANL) are biased to
0.5 × VCC. In dominant state the bus pins are driven differentially apart. Logic high is equivalent to recessive on
the bus and logic low is equivalent to a dominant (differential) signal on the bus.
8.4.3 Standby Mode (HVDA540)
This is the low power mode of the device. It is selected by setting STB high. The CAN driver and receiver are
turned off and bidirectional CAN communication is not possible. There is no wake up capability in the HVDA540,
the RXD pin will remain recessive (high) while the device is in standby mode. This state is supplied via the VIO
supply, thus the VCC (5V) supply may be turned off for additional power savings at the system level. The local
protocol controller (MCU) should reactivate the device to normal mode to enable communication via the CAN
bus. The 5 V (VCC) supply needs to be reactivated by the local protocol controller to resume normal mode if it
has been turned off for low-power standby operation. The CAN bus pins are weakly pulled to GND, see
Figure 15 and Figure 16.
8.4.4 Standby Mode With RXD Wake Up-Request (HVDA541)
This is the low power mode of the device. It is selected by setting STB high. The CAN driver and main receiver
are turned off and bidirectional CAN communication is not possible. The low power receiver and bus monitor,
both supplied via the VIO supply, are enabled to allow for RXD wake up requests via the CAN bus. The VCC (5V)
supply may be turned off for additional power savings at the system level. A wake up request will be output to
RXD (driven low) for any dominant bus transmissions longer than the filter time tBUS. The local protocol controller
(MCU) should monitor RXD for transitions and then reactivate the device to normal mode based on the wake up
request. The 5 V (VCC) supply needs to be reactivated by the local protocol controller to resume normal mode if it
has been turned off for low-power standby operation. The CAN bus pins are weakly pulled to GND, see
Figure 15 and Figure 16.
8.4.4.1 RXD Wake Up Request Lock Out for Bus Stuck Dominant Fault (HVDA541)
If the bus has a fault condition where it is stuck dominant while the HVDA541 is placed into standby mode via the
STB pin, the device locks out the RXD wake up request until the fault has been removed to prevent false wake
up signals in the system.
18
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Standby Mode, STB = High
STB
Bus VDiff
tBUS
<tBUS
<tBUS
tBUS
<tBUS
RXD
Figure 17. HVDA541 RXD Wake Up Request With No Bus Fault Condition
STB
Standby Mode, STB = High
Bus VDiff
tBUS
tBUS
tBUS
tClear
<tClear
tBUS
<tBUS
RXD
Figure 18. HVDA541 RXD Wake Up Request Lock Out When Bus Dominant Fault Condition
8.4.5 Silent (Receive Only) Mode (HVDA542)
This is the silent (receive only) mode of the device. It is selected by setting S high. The CAN driver is turned off
while the receiver remains active and RXD will output the received bus state. There is no low power mode in the
HVDA542 except for VCC and VIO supply undervoltage conditions (see Undervoltage Lockout and Unpowered
Device).
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SN65HVDA541-5-Q1 SN65HVDA542-5-Q1
19
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
www.ti.com
8.4.6 Driver and Receiver Function Tables
Table 4. Driver Function Table
INPUTS
DEVICE
STB / S
All Devices
HVDA540/541
(2)
HVDA542 (3)
(1)
(2)
(3)
(1)
OUTPUTS
TXD
(1)
CANH
(1)
CANL (1)
DRIVEN BUS
STATE
L
L
H
L
Dominant
L
H
Z
Z
Recessive
L
Open
Z
Z
Recessive
H
X
Y
Y
Recessive
H
X
Z
Z
Recessive
H = high level, L = low level, X = irrelevant, Y = common mode bias to GND, Z = common mode bias
to VCC/2. See Figure 15 and Figure 16 for common mode bias information.
HVDA540/541 have internal pull up to VIO on STB pin. If STB pin is open the pin will be pulled high
and the device will be in standby mode.
HVDA542 has internal pulldown to GND on S pin. If S pin is open the pin will be pulled low and the
device will be in normal mode.
Table 5. Receiver Function Table
DEVICE MODE
CAN DIFFERENTIAL INPUTS
VID = V(CANH) – V(CANL)
BUS STATE
RXD PIN (1)
STANDBY
(HVDA540) (2)
X
X
H
STANDBY WITH
RXD WAKE UP
REQUEST
(HVDA541) (3)
VID ≥ 1.15 V
DOMINANT
L
0.4 V < VID < 1.15 V
?
?
VID ≤ 0.4 V
RECESSIVE
H
VID ≥ 0.9 V
DOMINANT
L
0.5 V < VID < 0.9 V
?
?
VID ≤ 0.5 V
RECESSIVE
H
Open
N/A
H
NORMAL OR
SILENT
ANY
(1)
(2)
(3)
20
H = high level, L = low level, X = irrelevant, ? = indeterminate.
While STB is high (standby mode) the RXD output of the HVDA540 is always high (recessive)
because it has no wake-up receiver.
While STB is high (standby mode) the RXD output of the HVDA541 functions according to the levels
above and the wake-up conditions shown in Figure 17 and Figure 18.
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SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
www.ti.com
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the
data link layer portion of the CAN protocol. Below are typical application configurations for both 5-V and 3.3-V
microprocessor applications. The bus termination is shown for illustrative purposes.
9.2 Typical Applications
9.2.1 3.3-V I/O Voltage Level and Normal Mode
VBATTERY
VOUT
3.3-V
Voltage
Regulator
VIN
VIO
(e.g. TPSxxxx)
VIO
VCORE
5
Port x
STB
VCORE
(e.g. TMS 470)
EN
Port y
5-V
Voltage
Regulator
RXD
TXD
CANH
HVDA540
or
HVDA541
MCU
VIN
7
8
RXD
TXD
CAN Transceiver
4
1
3
VCC
6
2
CANL
GND
(e.g. TPSxxxx)
VOUT
Copyright © 2016, Texas Instruments Incorporated
5-V VCC, Not Needed in Low-Power Mode
Figure 19. Typical Application Using 3.3-V I/O Voltage Level and Low-Power Mode
9.2.1.1 Design Requirements
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus.
A large number of nodes requires transceivers with high input impedance such as the HVDA54x family of
transceivers.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2. They have made system-level tradeoffs for data rate, cable length, and parasitic loading of the bus.
Examples of some of these specifications are ARINC825, CANopen, DeviceNet, and NMEA2000.
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21
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
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Typical Applications (continued)
Node n
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
SN65HVD251 CAN
Transceiver
SN65HVD1050 CAN
Transceiver
SN65HVD233 CAN
Transceiver
(with termination)
MCU or DSP
CAN
Controller
SN65HVD257 CAN
Transceiver
RTERM
RTERM
Figure 20. Typical CAN Bus
9.2.1.2 Detailed Design Procedure
The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
to terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be on
the cable or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so
that two terminations always exist on the network. Termination may be a single 120-Ω resistor at the end of the
bus, either on the cable or in a terminating node. If filtering and stabilization of the common mode voltage of the
bus is desired, then split termination may be used (see Figure 21). Split termination improves the
electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common-mode voltages
at the start and end of message transmissions.
Standard Termination
CANH
Split Termination
CANH
RTERM/2
CAN
Transceiver
RTERM
CAN
Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 21. CAN Bus Termination Concepts
The family of transceivers have variants for both 5-V only applications and applications where level shifting is
needed for a 3.3-V micrcontroller.
22
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SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
www.ti.com
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
Typical Applications (continued)
9.2.1.2.1 Loop Propagation Delay
Transceiver loop delay is a measure of the overall device propagation delay and consists of the delay from driver
input (TXD pin) to differential outputs (CANH and CANL), plus the delay from the receiver inputs (CANH and
CANL) to the output pin RXD.
In Figure 22 is displayed the loop delay at 1 Mbps with Vio equal to 3.3 V
Data rate = 1 Mbps, Temp = 25°C, VCC = 5 V, Load = 60 Ω, STB = 0, VIO = 3.3 V.
Figure 22. t_LOOP Delay
9.2.1.3 Application Curves
Data rate = 1 Mbps, Temp = 25°C, VCC = 5 V, Load = 60 Ω,
STB = 0, VIO = 3.3 V.
Figure 23. HVDA540 TXD, CANH, CANL and RXD
Waveforms at
1 Mbps
Data rate = 500 Kbps, Temp = 25°C, VCC = 5 V, Load = 60 Ω,
STB = 0, VIO = 3.3 V.
Figure 24. HVDA540 TXD, CANH, CANL and RXD
Waveforms at
500 Kbps
9.3 System Examples
Figure 25, Figure 26, and Figure 27 show three different example applications using the HVDA54x family of
transceivers. Different devices and configurations can be used depending on the I/O voltage levels supported by
the MCU and different operating modes required by the end application.
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23
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
www.ti.com
System Examples (continued)
VIGNITION
VOUT
VIN
3.3-V
Voltage
Regulator
(e.g. TPSxxxx)
VIO
VIO
VCORE
5
Port x
S
7
CANH
8
VCORE
MCU
HVDA542
(e.g. TMS 470)
CAN Transceiver
RXD
VIN
5-V
Voltage
Regulator
TXD
RXD
TXD
4
1
3
6
2
VCC
CANL
GND
(e.g. TPSxxxx)
VOUT
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Typical Application Using 3.3-V I/O Voltage Level and No Low-Power Mode
VBATTERY
VIN
VOUT
5-V Voltage
Regulator
(e.g. TPSxxxx)
VCC
VCC
Port x
STB
(e.g. TMS 470)
TXD
7
CANH
HVDA540-5
or
HVDA541-5
5-V MCU
RXD
3
8
RXD
4
TXD
1
CAN Transceiver
5
6
2
NC
CANL
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Typical Application Using 5-V MCU and Low-Power Mode
VBATTERY
VIN
VOUT
5-V Voltage
Regulator
(e.g. TPSxxxx)
VCC
VCC
Port x
S
3
8
7
CANH
HVDA542-5
5-V MCU
CAN Transceiver
(e.g. TMS 470)
RXD
TXD
RXD
4
TXD
1
5
NC
2
6
CANL
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Typical Application Using 5-V MCU and No Low-Power Mode
24
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SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
www.ti.com
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a
100-nF ceramic capacitor located as close to the VCC supply pins as possible. Either a linear regulator or
switched-mode power supply may be used. Power and ground nets should be routed on the PCB using planes or
wide traces so that series resistance and inductance are minimized.
11 Layout
11.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection device to protect
against EFT and surge transients that may occur in industrial enviroments. Because ESD and transients have a
wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must be
applied during PCB design. The HVDA54x-Q1 and HVDA54x-5-Q1 families come with high on-chip IEC ESD
protection, but if higher levels of system level immunity are desired external TVS diodes can be used. TVS
diodes and bus filtering capacitors should be placed as close to the onboard connectors as possible to prevent
noisy transient events from propagating further into the PCB and system.
• Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and
noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device,
D1, has been used for added protection. The production solution can be either bidirectional TVS diode or
varistor with ratings matching the application requirements. This example also shows optional bus filter
capacitors C4 and C5. Additionally (not shown) a series common mode choke (CMC) can be placed on the
CANH and CANL lines between the transceiver U1 and connector J1.
• Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
• Use supply (VCC) and ground planes to provide low inductance.
NOTE
High-frequency currents follows the path of least impedance and not the path of least
resistance.
•
•
•
•
•
•
•
Use at least two vias for supply (VCC) and ground connections of bypass capacitors and protection devices to
minimize trace and via inductance.
Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,
examples are C1, C2 on the VCC supply and C6 and C7 on the VIO supply.
Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C3. Split
termination provides common mode filtering for the bus. When bus termination is placed on the board instead
of directly on the bus, take additional care to ensure the terminating node is not removed from the bus thus
also removing the termination. See the application section for information on power ratings needed for the
termination resistor(s).
To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not
required.
Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used,
this is mandatory to ensure the bit timing into the device is met.
Terminal 5: For devices with a VIO input, bypass capacitors should be placed as close to the pin as possible
(example C6 and C7). In devices without a VIO input, this pin is not internally connected and can be left
floating or tied to any existing net (for example, a split pin connection).
Terminal 8: is shown assuming the mode terminal, STB, will be used. If the device is only used in normal
mode, R4 is not needed and R5 could be used for the pulldown resistor to GND.
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25
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
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11.2 Layout Examples
VCC or VIO
R5
R1
R2
TXD
R6
7
4
5
R7
C5
6
C6
C7
3
J1
C3
GND
D1
U1
U1
C2
C1
R3
C4
2
VCC
GND
8
1
GND
RXD
R4
STB
GND
VIO
GND
Figure 28. HVDA540/HVDA541 Layout Example
R5
R1
R2
TXD
R6
7
4
5
R7
C5
6
C6
C7
3
J1
C3
GND
D1
U1
U1
C2
C1
R3
C4
2
VCC
GND
8
1
GND
RXD
R4
S
VCC or VIO
GND
VIO
GND
Figure 29. HVDA542 Layout Example
26
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SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
www.ti.com
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
SN65HVDA54x-Q1 Errata (SLLZ073)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 6. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65HVDA540-Q1
Click here
Click here
Click here
Click here
Click here
SN65HVDA541-Q1
Click here
Click here
Click here
Click here
Click here
SN65HVDA542-Q1
Click here
Click here
Click here
Click here
Click here
SN65HVDA540-5-Q1
Click here
Click here
Click here
Click here
Click here
SN65HVDA541-5-Q1
Click here
Click here
Click here
Click here
Click here
SN65HVDA542-5-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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27
SN65HVDA540-Q1, SN65HVDA541-Q1
SN65HVDA542-Q1, SN65HVDA540-5-Q1
SN65HVDA541-5-Q1, SN65HVDA542-5-Q1
SLLS804D – MARCH 2009 – REVISED AUGUST 2016
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
HVDA5405QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
H5405Q
HVDA540QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
H540Q
HVDA5415QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
H5415Q
HVDA541QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
H541Q
HVDA5425QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
H5425Q
HVDA542QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
H542Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVDA540-Q1 :
• Catalog: SN65HVDA540
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
HVDA5405QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
HVDA540QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
HVDA5415QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
HVDA541QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
HVDA5425QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
HVDA542QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HVDA5405QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
HVDA540QDRQ1
SOIC
D
8
2500
350.0
350.0
43.0
HVDA5415QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
HVDA541QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
HVDA5425QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
HVDA542QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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