Texas Instruments | DS90UB928Q-Q1 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel (Rev. C) | Datasheet | Texas Instruments DS90UB928Q-Q1 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel (Rev. C) Datasheet

Texas Instruments DS90UB928Q-Q1 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel (Rev. C) Datasheet
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DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
DS90UB928Q-Q1 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With
Bidirectional Control Channel
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications AEC-Q100
– Device Temperature Grade 2: -40°C to +105°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level ±8 kV
– Device CDM ESD Classification Level C6
Bidirectional Control Channel Interface with I2C
Compatible Serial Control Bus
Low EMI FPD-Link Video Output
Supports High Definition (720p) Digital Video
RGB888 + VS, HS, DE and I2S Audio Supported
5 MHz to 85 MHz Pixel Clock Support
Up to 4 I2S Digital Audio Outputs for Surround
Sound Applications
4 Bidirectional GPIO Channels with 2 Dedicated
Pins
Single 3.3 V supply with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
AC-Coupled STP Interconnect Up to 10 Meters
DC-Balanced and Scrambled Data with
Embedded Clock
Adaptive Cable Equalization
Image Enhancement (White Balance & Dithering)
and Internal Pattern Generation
Backward Compatible Modes
Automotive Displays for Navigation
Rear Seat Entertainment Systems
Automotive Driver Assistance
Automotive Megapixel Camera Systems
3 Description
The DS90UB928Q-Q1 deserializer, in conjunction
with a DS90UB925Q-Q1 or DS90UB927Q-Q1
serializer, provides a solution for distribution of digital
video and audio within automotive infotainment
systems. The device converts a high-speed serialized
interface with an embedded clock, delivered over a
single signal pair (FPD-Link III), to four LVDS
data/control streams, one LVDS clock pair (OpenLDI
(FPD-Link)), and I2S audio data. The serial bus
scheme, FPD-Link III, supports high-speed forward
channel data transmission and low-speed full duplex
back channel communication over a single differential
link. Consolidation of audio, video data and control
over a single differential pair reduces the interconnect
size and weight, while also eliminating skew issues
and simplifying system design.
Adaptive input equalization of the serial input stream
provides compensation for transmission medium
losses and deterministic jitter. EMI is minimized by
the use of low voltage differential signaling.
Device Information(1)
PART NUMBER
PACKAGE
DS90UB928Q-Q1
WQFN (48)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Application Diagram
FPD-Link
(OpenLDI)
FPD-Link
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Style Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
RxIN3+/-
RxIN1+/RxIN0+/RxCLKIN+/-
PDB
I2S AUDIO
(Surround)
SCL
SDA
IDx
6
TxOUT3+/-
FPD-Link III
1 Pair/AC Coupled
RxIN2+/-
DOUT+
DOUT-
DS90UB927Q
Serializer
TxOUT2+/-
RIN+
TxOUT1+/TxOUT0+/-
RIN100Q STP Cable
CMF
CMF
OEN
OSS_SEL
PDB
MAPSEL
MAPSEL
LFMODE
LFMODE
REPEAT
REPEAT
BISTEN
BACKWD
MODE_SEL
DS90UB928Q
Deserializer
LVDS Display
720p or
Graphic
Processor
TxCLKOUT+/-
6
LOCK
PASS
I2S AUDIO
(Surround)
MCLK
SCL
SDA
IDx
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Application Diagram ..............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
1
2
4
7
Absolute Maximum Ratings ..................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
DC Electrical Characteristics .................................... 9
AC Electrical Characteristics................................... 11
Timing Requirements for the Serial Control Bus .... 12
Timing Requirements .............................................. 12
DC and AC Serial Control Bus Characteristics....... 13
Typical Characteristics .......................................... 17
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 31
8.5 Programming........................................................... 38
8.6 Register Maps ......................................................... 39
9
Application and Implementation ........................ 55
9.1
9.2
9.3
9.4
Application Information............................................
Typical Application ..................................................
AV Mute Prevention ................................................
OEN Toggling Limitation .........................................
55
55
58
58
10 Power Supply Recommendations ..................... 58
10.1 Power Up Requirements and PDB Pin ................. 58
11 Layout................................................................... 60
11.1 Layout Guidelines ................................................. 60
11.2 Layout Example .................................................... 61
12 Device and Documentation Support ................. 63
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
63
63
63
63
63
63
13 Mechanical, Packaging, and Orderable
Information ........................................................... 63
5 Revision History
Changes from Revision B (January 2015) to Revision C
Page
•
Added "OpenLDI". ................................................................................................................................................................. 1
•
Added AV Mute Prevention section. ...................................................................................................................................... 2
•
Added OEN Toggling Limitation. ........................................................................................................................................... 2
•
Changed the shared function. ............................................................................................................................................... 4
•
Added the shared function ..................................................................................................................................................... 5
•
Changed Pin name .............................................................................................................................................................. 11
•
Added Input Jitter specification. ........................................................................................................................................... 11
•
Added I2S Set-up Time. ...................................................................................................................................................... 12
•
Added I2S Hold Time. ......................................................................................................................................................... 12
•
Added Read Register at the first step. ................................................................................................................................ 26
•
Changed the updated GPIO Configuration table. ................................................................................................................ 27
•
Changed to one tenth of Resistor value ............................................................................................................................... 33
•
Changed and swapped IDEAL RATIO and IDEAL VR2 values. .......................................................................................... 38
•
Changed to one tenth of Resistor value ............................................................................................................................... 38
•
Changed and Revised data to 0x01 ..................................................................................................................................... 45
•
Changed and revised GPIO Direction description. .............................................................................................................. 47
•
Changed and revised Register Type to RW from R. ........................................................................................................... 48
•
Added and disclosed Link Error Count Register. ................................................................................................................ 51
•
Added and disclosed LVDS Setting Register. ..................................................................................................................... 52
•
Changed and revised Register Address. ............................................................................................................................. 54
•
Added AV Mute Prevention section. .................................................................................................................................... 58
•
Added OEN Toggling Limitation. ......................................................................................................................................... 58
•
Changed and updated Power-Up Requirements and PDB. ................................................................................................. 58
2
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SNLS417C – MARCH 2013 – REVISED JULY 2016
Revision History (continued)
Changes from Revision A (April 2013) to Revision B
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SNLS417C – MARCH 2013 – REVISED JULY 2016
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6 Pin Configuration and Functions
MAPSEL
CAPLV25
26
25
OEN
30
LOCK
VDD33_B
31
27
LFMODE
32
28
CAPL12
33
CAPLV12
RES0
34
PASS
OSS_SEL
35
29
I2S_DD/GPIO3
36
RHS Package
48-Pin WQFN
Top View
I2S_DC/GPIO2
37
24
TxOUT0-
VDD33_A
38
23
TxOUT0+
RES1
39
22
TxOUT1-
RIN+
40
21
TxOUT1+
RIN-
41
20
TxOUT2-
CMF
42
19
TxOUT2+
BISTC/INTB_IN
43
18
TxCLKOUT-
CMLOUTP
44
17
TxCLKOUT+
CMLOUTN
45
16
TxOUT3-
CAPR12
46
15
TxOUT3+
CAPP12
47
14
GPIO0/SWC
MODE_SEL
48
13
GPIO1/SDOUT
DS90UB928Q-Q1
TOP VIEW
10
11
12
I2S_WC/GPIO_REG7
MCLK
IDx
8
I2S_CLK/GPIO_REG8
9
7
I2S_DA/GPIO_REG6
BISTEN
6
4
SDA
VDDIO
3
I2S_DB/GPIO_REG5
5
2
CAPI2S
SCL
1
PDB
DAP = GND
Pin Functions
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
FPD-LINK OUTPUT INTERFACE
TxCLKOUT-
18
O, LVDS
Inverting LVDS Clock Output
The pair requires external 100 Ω differential termination for standard LVDS levels
TxCLKOUT+
17
O, LVDS
True LVDS Clock Output
The pair requires external 100 Ω differential termination for standard LVDS levels
TxOUT[3:0]-
16, 20, 22,
24
O, LVDS
Inverting LVDS Data Outputs
Each pair requires external 100 Ω differential termination for standard LVDS levels
TxOUT[3:0]+
15, 19, 21,
23
O, LVDS
True LVDS Data Outputs
Each pair requires external 100 Ω differential termination for standard LVDS levels
LVCMOS INTERFACE
GPIO[1:0]
13, 14
I/O, LVCMOS General Purpose IO
with pulldown Shared with SDOUT, SWC
GPIO[3:2]
36, 37
I/O, LVCMOS General Purpose I/O
with pulldown Shared with I2S_DA I2S_WC
4
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Pin Functions (continued)
PIN
NAME
GPIO_REG[8
:5]
NO.
8, 10, 7, 3
I/O, TYPE
DESCRIPTION
I/O, LVCMOS General Purpose I/O, register access only
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
I2S_DA
I2S_DB
I2S_DC
I2S_DD
7
3
37
36
O, LVCMOS
Digital Audio Interface I2S Data Outputs
Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
INTB_IN
43
I, LVCMOS Interrupt Input
with pulldown Shared with BISTC
MCLK
I2S_WC
I2S_CLK
11
10
8
O, LVCMOS
SDOUT
SWC
13, 14
Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs
I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8
I/O, LVCMOS Auxiliary Digital Audio Interface I2S Data Output and Word Clock
with pulldown Shared with GPIO1 and GPIO0
CONTROL AND CONFIGURATION
BISTC
43
I, LVCMOS BIST Clock Select
with pulldown Shared with INTB_IN
Requires a 10 kΩ pullup if set HIGH
BISTEN
9
I, LVCMOS BIST Enable
with pulldown Requires a 10 kΩ pullup if set HIGH
IDx
12
LFMODE
32
I, LVCMOS Low Frequency Mode Select
with pulldown LFMODE = 0, 15 MHz ≤ TxCLKOUT ≤ 85 MHz (Default)
LFMODE = 1, 5 MHz ≤ TxCLKOUT < 15 MHz
Requires a 10 kΩ pullup if set HIGH
MAPSEL
26
I, LVCMOS FPD-Link Output Map Select
with pulldown MAPSEL = 0, LSBs on TxOUT3± (Default)
MAPSEL = 1, MSBs on TxOUT3±
Requires a 10 kΩ pullup if set HIGH
MODE_SEL
48
OEN
30
I, LVCMOS Output Enable
with pulldown Requires a 10 kΩ pullup if set HIGH
See Table 5
OSS_SEL
35
I, LVCMOS Output Sleep State Select
with pulldown Requires a 10 kΩ pullup if set HIGH
See Table 5
PDB
1
I, LVCMOS
SCL
5
I/O, Open
Drain
I2C Clock Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
SDA
4
I/O, Open
Drain
I2C Data Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
I, Analog
I, Analog
I2C Address Select
External pullup to VDD33 is required under all conditions. DO NOT FLOAT.
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.
See Table 7
Device Configuration Select
Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4-channel (I2S_B),
and Long Cable (LCBL) modes
Connect to external pullup to VDD33 and pulldown to GND resistors to create a voltage
divider. DO NOT FLOAT
See Table 6
Power-down Mode Input Pin
Must be driven or pulled up to VDD33. Refer to Power Up Requirements and PDB PinPower
Up Requirements and PDB Pin in .
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down
When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state,
the PLL is shutdown, and IDD is minimized. Control Registers are RESET.
STATUS
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Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
LOCK
27
O, LVCMOS
LOCK Status Output
0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states
controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.
1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL
Route to test point or pad (Recommended). Float if unused.
PASS
28
O, LVCMOS
PASS Status Output
0: One or more errors were detected in the received BIST payload (BIST Mode)
1: Error-free transmission (BIST Mode)
Route to test point or pad (Recommended). Float if unused.
FPD-LINK III SERIAL INTERFACE
CMF
42
Analog
Common Mode Filter
Requires a 0.1 µF capacitor to GND
CMLOUTN
45
O, LVDS
Inverting Loop-through Driver Output
Monitor point for equalized forward channel differential signal. Connect a 100 Ω resistor
between CMLOUTN and CMLOUTP pins to monitor.
CMLOUTP
44
O, LVDS
True Loop-through Driver Output
Monitor point for equalized forward channel differential signal. Connect a 100 Ω resistor
between CMLOUTN and CMLOUTP pins to monitor.
RIN-
41
I/O, LVDS
FPD-Link III Inverting Input
The output must be AC-coupled with a 0.1 µF capacitor. This pin has 100 Ω (typ.) internal
termination between RIN- and RIN+ pins.
RIN+
40
I/O, LVDS
FPD-Link III True Input
The output must be AC-coupled with a 0.1 µF capacitor. This pin has 100 Ω (typ.) internal
termination between RIN- and RIN+ pins.
POWER AND GROUND (1)
GND
DAP
Ground
Large metal contact at the bottom center of the device package
Connect to the ground plane (GND) with at least 9 vias
VDD33_A
VDD33_B
38
31
Power
3.3 V Power to on-chip regulator
Each pin requires a 4.7 µF capacitor to GND
VDDIO
6
Power
1.8 V/3.3 V LVCMOS I/O Power
Requires a 4.7 µF capacitor to GND
REGULATOR CAPACITOR
CAPI2S
CAPLV25
CAPLV12
CAPR12
CAPP12
2
25
29
46
47
CAP
Decoupling capacitor connection for on-chip regulator
Each requires a 4.7 µF decoupling capacitor to GND
CAPL12
33
CAP
Decoupling capacitor connection for on-chip regulator
Requires two 4.7 µF decoupling capacitors to GND
39, 34
GND
Reserved
Connect to GND
OTHER
RES[1:0]
(1)
6
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
(2)
MIN
MAX
UNIT
Supply Voltage – VDD33
(3)
−0.3
4
V
Supply Voltage – VDDIO
(3)
−0.3
4
V
−0.3
(VDDIO +
0.3)
V
−0.3
2.75
V
150
°C
150
°C
LVCMOS I/O Voltage
Deserializer Input Voltage
Junction Temperature
−65
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see product folder at www.ti.com and SNOA549.
The DS90UB928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less
than 1.5 ms with a monotonic rise.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic
discharge
VALUE
UNIT
Human body model (HBM), per AEC Q100-002, all pins (1)
±8000
V
Charged device model (CDM), per AEC Q100-011, all pins
±1250
V
Machine model (MM)
±250
V
±15000
V
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pins 40, 41, 44, and 45)
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
(ISO10605)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pins 40, 41, 44, and 45)
±15000
V
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
(ISO10605)
RD = 2 kΩ, CS = 150 pF or
330 pF
Air Discharge (Pins 40, 41, 44, and 45)
±15000
V
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
3
3.3
3.6
V
Connect VDDIO to 3.3 V and use 3.3 V IOs
3
3.3
3.6
V
Connect VDDIO to 1.8 V and use 1.8 V IOs
1.71
1.8
1.89
V
−40
25
105
°C
85
MHz
Supply Voltage (VDD33) (1)
LVCMOS Supply Voltage (VDDIO)
(1) (2)
Operating Free Air
Temperature (TA)
PCLK Frequency (out of TxCLKOUT±)
5
Supply Noise (3)
(1)
(2)
(3)
UNIT
100 mVP-P
The DS90UB928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less
than 1.5 ms with a monotonic rise.
VDDIO should not exceed VDD33 by more than 300 mV (VDDIO < VDD33 + 0.3 V).
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies
with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.
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7.4 Thermal Information
DS90UB928Q-Q1
THERMAL METRIC (1)
RHS (WQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
26.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
4.4
°C/W
RθJB
Junction-to-board thermal resistance
4.3
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
4.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.8
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(1) (2) (3)
MIN
TYP
MAX
UNIT
2.0
VDDIO
V
GND
0.8
V
+10
μA
3.3 V LVCMOS I/O
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
VIH
High Level Input Voltage
2.0
VDDIO
V
VIL
Low Level Input Voltage
GND
0.7
V
IIN
Input Current
VIN = 0 V or VIN = 3.0 V to 3.6 V
+10
μA
VOH
HIGH Level Output Voltage
IOH = -4 mA
VDDIO
V
VOL
LOW Level Output Voltage
IOL = +4 mA
IOS
Output Short Circuit Current
VOUT = 0 V (5)
IOZ
Tri-state Output Current
VOUT = 0 V or VDDIO, PDB = L
(1)
(2)
(3)
(4)
(5)
GPIO[3:0],
REG_GPIO[8:
5], LFMODE,
MAPSEL,
BISTEN,
BISTC,
= 3.0 V to 3.6 V
INTB_IN,
OEN,
OSS_SEL
VDDIO = 3.0 V to 3.6 V
VIN = 0 V or VIN
(4)
PDB
−10
−10
(4)
GPIO[3:0],
REG_GPIO[8:
5], MCLK,
I2S_WC,
I2S_CLK,
I2S_D[A:D],
LOCK, PASS
±1
±1
2.4
0
0.4
−55
−20
V
mA
+20
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO ≥ 3.0 V.
IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(1) (2) (3)
MIN
TYP
MAX
UNIT
1.8 V LVCMOS I/O
VIH
High Level Input Voltage
VDDIO = 1.71 V to 1.89 V
VIL
Low Level Input Voltage
IIN
Input Current
VIN = 0 V or VIN = 1.71 V to
1.89 V
VOH
HIGH Level Output Voltage
IOH = -4 mA
VOL
LOW Level Output Voltage
IOL = +4 mA
IOS
Output Short Circuit Current
VOUT = 0 V (5)
IOZ
TRI-STATE® Output Current
VOUT = 0 V or VDDIO, PDB = L,
GPIO[3:0],
REG_GPIO[8:
5], LFMODE,
MAPSEL,
BISTEN,
BISTC,
INTB_IN,
OEN,
OSS_SEL
0.65 *
VDDIO
VDDIO
V
0
0.35 *
VDDIO
V
-10
10
μA
GPIO[3:0],
REG_GPIO[8:
5], MCLK,
I2S_WC,
I2S_CLK,
I2S_D[A:D],
LOCK, PASS
VDDIO 0.45
VDDIO
V
0
0.45
-35
-20
V
mA
20
μA
FPD-LINK (OpenLDI) LVDS OUTPUT
VOD
VODp-p
Output Voltage Swing (singleended)
Differential Output Voltage
Register 0x4B[1:0] = b'00
RL = 100 Ω
140
200
300
Register 0x4B[1:0] = b'01
RL = 100 Ω
220
300
380
Register 0x4B[1:0] = b'00
RL = 100 Ω
mV
TxCLK±,
TxOUT[3:0]±
400
mV
Register 0x4B[1:0] = b'01
RL = 100 Ω
ΔVOD
Output Voltage Unbalance
VOS
Common Mode Voltage
ΔVOS
Offset Voltage Unbalance
IOS
Output Short Circuit Current
VOUT = GND
IOZ
Output TRI-STATE® Current
OEN = GND, VOUT = VDDIO or
GND, 0.8 V≤VIN≤1.6 V
600
RL = 100 Ω
1.125
1
50
1.25
1.375
1
50
-5
-500
mV
V
mV
mA
500
μA
50
mV
FPD-LINK III RECEIVER
VTH
Input Threshold High
VTL
Input Threshold Low
VID
Input Differential Threshold
VCM
Common-mode Voltage
RT
Internal Termination Resistance
(Differential)
VCM = 2.1 V (Internal VBIAS)
-50
mV
100
RIN±
2.1
80
mV
V
100
120
Ω
VDD33= 3.6 V
190
250
mA
VDDIO = 3.6 V
0.1
1
mA
VDDIO = 1.89 V
0.1
1
mA
VDD33= 3.6 V
185
mA
VDDIO = 3.6 V
0.1
mA
VDDIO = 1.89 V
0.1
SUPPLY CURRENT
IDD1
IDDIO1
IDD2
Checkerboard Pattern
Supply Current
RL = 100 Ω,
PCLK = 85 MHz
Random Pattern
IDDIO2
IDDZ
IDDIOZ
10
Supply Current — Power Down
PDB = 0 V, All other LVCMOS
inputs = 0 V
mA
VDD33 = 3.6 V
3
8
mA
VDDIO = 3.6 V
100
500
μA
VDDIO = 1.89 V
50
250
μA
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7.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
(1) (2) (3)
PIN/FREQ.
MIN
TYP
MAX
UNIT
GPIO[3:0],
PCLK = 5
MHz to 85
MHz
2/PCLK
s
20
µs
2
ms
GPIO
tGPIO,FC
GPIO Pulse Width, Forward
Channel
See
(4)
tGPIO,BC
GPIO Pulse Width, Back Channel
See
(4)
GPIO[3:0]
PDB Reset Low Pulse
See
(4)
PDB
RESET
tLRST
LOOP-THROUGH MONITOR OUTPUT
EW
Differential Output Eye Opening
Width
EH
Differential Output Eye Height
RL = 100 Ω, Jitter freq > f/40
CMLOUTP,
CMLPUTN
0.4
UI
300
mV
FPD-LINK LVDS OUTPUT
tTLHT
Low to High Transition Time
tTHLT
High to Low Transition Time
tDCCJ
Cycle-to-Cycle Output Jitter
RL = 100 Ω
TxCLK±,
TxOUT[3:0]±
0.25
PCLK = 5 MHz
TxCLK±
PCLK = 85 MHz
tTTPn
Transmitter Pulse Position
5 MHz ≤ PCLK ≤ 85 MHz
n = [6:0] for bits [6:0]
See Figure 13
ΔtTTP
Offset Transmitter Pulse Position
(bit 6 - bit 0)
PCLK = 85 MHz
tDD
Delay Latency
tTPDD
Power Down Delay Active to OFF
tTXZR
Enable Delay OFF to Active
TxOUT[3:0]±
0.5
ns
0.25
0.5
ns
170
275
ps
35
55
0.5 + n
UI
0.1
UI
147*T
T
900
µs
6
ns
FPD-LINK III INPUT
IJT
Input Jitter (5)
PCLK = 5 MHz to 85 MHz
Sinusoidal Jitter Frequency >
PCLK / 15
RIN±
tDDLT
Lock Time (4)
5 MHz ≤ PCLK ≤ 85 MHz
RIN±, LOCK
CL = 8 pF
LOCK, PASS
0.35
UI
6
40
ms
3
7
ns
2
5
ns
LVCMOS OUTPUTS
tCLH
Low-to-High Transition Time
tCHL
High-to-Low Transition Time
BIST MODE
tPASS
BIST PASS Valid Time
PASS
800
ns
2
ns
2/PCLK
or >77
ns
I2S TRANSMITTER
tJ
Clock Output Jitter
TI2S
I2S Clock Period
Figure 10, (4) (6)
THC
I2S Clock High Time
Figure 10, (6)
(1)
(2)
(3)
(4)
(5)
(6)
MCLK
PCLK=5 MHz to 85 MHz
I2S_CLK,
PCLK = 5
MHz to 85
MHz
I2S_CLK
0.35
TI2S
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by design and is not tested in production.
UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35 × PCLK). The UI scales with PCLK frequency.
I2S specifications for tLC and tHC pulses must each be greater than 1 PCLK period to ensure sampling and supersedes the 0.35*TI2S_CLK
requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK.
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
TLC
I2S Clock Low Time
Figure 10, (6)
I2S_CLK
tSR_I2S
I2S Set-up Time
Figure 10, (6)
tHR_I2S
I2S Hold Time
Figure 10, (6)
(1) (2) (3)
MIN
TYP
MAX
UNIT
0.35
TI2S
I2S_WC
I2S_D[A:D]
0.2
TI2S
I2S_WC
I2S_D[A:D]
0.2
TI2S
7.7 Timing Requirements for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
(1) (2)
MIN
fSCL
SCL Clock Frequency
tLOW
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tBUF
tr
(1)
(2)
(3)
100
kHz
Fast Mode
0
400
kHz
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Hold time for a start or a
repeated start condition
Standard Mode
4.0
µs
(3)
Fast Mode
0.6
µs
Set Up time for a start or a
repeated start condition
Standard Mode
4.7
µs
(3)
Fast Mode
0.6
µs
Data Hold Time
Standard Mode
SCL Low Period
SCL High Period
Data Set Up Time
Fast Mode
0
3.45
µs
0
0.9
µs
Standard Mode
250
Fast Mode
100
ns
ns
4
µs
Set Up Time for STOP
Condition
Standard Mode
(3)
Fast Mode
0.6
µs
Bus Free Time
Between STOP and START
Standard Mode
4.7
µs
(3)
Fast Mode
1.3
µs
SCL & SDA Rise Time,
Standard Mode
(3)
SCL & SDA Fall Time,
tf
TYP
4.7
(3)
tSU;STO
UNIT
0
Standard Mode
(3)
tSU;DAT
MAX
Standard Mode
(3)
1000
ns
Fast Mode
300
ns
Standard Mode
300
ns
Fast mode
300
ns
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Specification is ensured by design and is not tested in production.
7.8 Timing Requirements
MIN
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time – READ
tHD;DAT
Hold Up Time – READ
12
NOM
MAX
UNIT
430
ns
20
ns
Figure 16
560
ns
Figure 16
615
ns
SDA, RPU = 10 kΩ, Cb ≤
400 pF, Figure 16
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7.9 DC and AC Serial Control Bus Characteristics
Over 3.3 V supply and temperature ranges unless otherwise specified.
PARAMETER
(1) (2) (3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input High Level
SDA and SCL
0.7*
VDDIO
VDD33
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.3*
VDD33
V
VHY
Input Hysteresis
50
VOL
SDA or SCL, IOL = 1.25 mA
Iin
SDA or SCL, VIN = VDDIO or GND
tSP
Input Filter
Cin
Input Capacitance
(1)
(2)
(3)
mV
0
0.36
V
-10
10
µA
SDA or SCL
50
ns
5
pF
The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not
ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
+VOD
TxCLKOUT
-VOD
+VOD
TxOUT3
-VOD
+VOD
TxOUT2
-VOD
+VOD
TxOUT1
-VOD
+VOD
TxOUT0
-VOD
Cycle N+1
Cycle N
Figure 1. Checkerboard Data Pattern
EW
VOD (+)
RIN
(Diff.)
EH
0V
EH
VOD (-)
tBIT (1 UI)
Figure 2. CML Output Driver
VDDIO
80%
20%
GND
tCLH
tCHL
Figure 3. LVCMOS Transition Times
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START
STOP
BIT SYMBOL N+3 BIT
§
§
§
START
STOP
BIT SYMBOL N+2 BIT
§
§
START
STOP
BIT SYMBOL N+1 BIT
§
START
STOP
BIT SYMBOL N BIT
RIN
§
§
DCA, DCB
tDD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Latency Delay
PDB
VILmax
RIN
X
tTPDD
LOCK
Z
PASS
Z
TxCLKOUT
Z
TxOUT[3:0]
Z
Figure 5. FPD-Link & LVCMOS Power Down Delay
PDB
LOCK
tTXZR
OEN
VIHmin
Z
TxCLKOUT
Z
TxOUT[3:0]
Figure 6. FPD-Link Outputs Enable Delay
PDB
VIH(min)
RIN±
tDDLT
LOCK
VOH(min)
TRI-STATE
Figure 7. CML PLL Lock Time
14
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RIN+
VTL
VCM
VTH
RIN-
GND
Figure 8. FPD-Link III Receiver DC VTH/VTL Definition
VDDIO
I2S_CLK,
MCLK
1/2 VDDIO
GND
GPIO,
I2S_WC,
I2S_D[D:A]
VDDIO
VOHmin
VOLmax
GND
tROH
tROS
Figure 9. Output Data Valid (Setup and Hold) Times
tI2S
tLC_I2S
tHC_I2S
VIH
I2S_CLK
VIL
tSR_I2S
tHR_I2S
VIH
I2S_WC
I2S_D[A,B,C,D]
VIL
Figure 10. Output State (Setup and Hold) Times
+VOD
80%
TxOUT[3:0]
TxCLKOUT
(Differential)
0V
20%
-VOD
tLHT
tHLT
TxOUT[3:0]+
TxCLKOUT+
TxOUT[3:0]TxCLKOUT-
Single-Ended
Figure 11. Input Transition Times
VOD-
VOD+
VOS
(TxOUT[3:0]+) (TxOUT[3:0]-) or
(TxCLKOUT+) (TxCLKOUT-)
VOD+
VODp-p
0V
VOD-
Differential
GND
Figure 12. FPD-Link Single-Ended and Differential Waveforms
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T
TxCLKOUT±
bit 1
TxOUT[3:0]±
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
tTTP1
0.5UI
tTTP2
1.5UI
tTTP3
2.5UI
3.5UI
2¨tTTP
tTTP4
tTTP5
4.5UI
tTTP6
5.5UI
tTTP7
6.5UI
Figure 13. FPD-Link Transmitter Pulse Positions
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tIJIT
= RxIN_TOL (Left + Right)
- tIJIT
Sampling Window = 1 UI
Figure 14. Receiver Input Jitter Tolerance
BISTEN
1/2 VDDIO
tPASS
PASS
(w/errors)
1/2 VDDIO
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 15. BIST PASS Waveform
SDA
tf
tHD;STA
tLOW
tr
tr
tBUF
tf
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 16. Serial Control Bus Timing Diagram
16
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7.10 Typical Characteristics
Input to Serializer
Output at Deserializer
Figure 17. Serializer Output Stream with 48 MHz Input Clock
Figure 18. 48 MHz Clock at Serializer and Deserializer
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8 Detailed Description
8.1 Overview
The DS90UB928Q-Q1 receives a 35-bit symbol over a single serial FPD-Link III pair operating at up to 2.975
Gbps line rate and converts this stream into an FPD-Link Interface (4 LVDS data channels + 1 LVDS Clock). The
FPD-Link III serial stream contains an embedded clock, video control signals, and the DC-balanced video data
and audio data which enhance signal quality to support AC coupling.
The DS90UB928Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream.
The DS90UB928Q-Q1 deserializer incorporates an I2C-compatible interface. The I2C-compatible interface allows
programming of serializer or deserializer devices from a local host controller. In addition, the
serializer/deserializer devices incorporate a bidirectional control channel (BCC) that allows communication
between serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link
from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either
side of the serial link.
The DS90UB928Q-Q1 deserializer is intended for use with DS90UB925Q-Q1 or DS90UB927Q-Q1 serializers,
but is also backward compatible with DS90UR905Q and DS90UR907Q FPD-Link II serializers.
8.2 Functional Block Diagram
OEN
OSS_SEL
REGULATOR
Parallel to Serial
RIN-
TxOUT3±
Data Receive
RIN+
DC Balance Decoder
Serial to Parallel
CMF
TxOUT2±
TxOUT1±
TxOUT0±
TxCLKOUT±
8
BISTEN
BISTC
LFMODE
MAPSEL
PDB
SCL
SCA
IDx
MODE_SEL
Error
Detector
Timing and
Control
Clock and
Data
Recovery
I2S / GPIO
PASS
LOCK
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8.3 Feature Description
8.3.1 High Speed Forward Channel Data Transfer
The High-Speed Forward Channel is composed of a 35-bit frame containing video data, sync signals, I2C, and
I2S audio transmitted from serializer to deserializer. Figure 19 illustrates the serial stream PCLK cycle. This data
payload is optimized for signal transmission over an AC-coupled link. Data is randomized, DC-balanced and
scrambled.
C0
C1
Figure 19. FPD-Link III Serial Stream
The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 85 MHz (LFMODE=0).
This corresponds to an application payload rate range of 175 Mbps to 2.975 Gbps, with an actual line rate range
of 525 Mbps to 2.975 Gbps.
8.3.2 Low-Speed Back Channel Data Transfer
The Low-Speed Back Channel of the DS90UB928Q-Q1 provides bidirectional communication between the
display and host processor. The back channel control data is transferred over the single serial link along with the
high-speed forward data, DC balance coding and embedded clock information. Together, the forward channel
and back channel for the bidirectional control channel (BCC). This architecture provides a backward path across
the serial link together with a high speed forward channel. The back channel contains the I2C, CRC and 4 bits of
standard GPIO information with 10 Mbps line rate.
8.3.3 Backward Compatible Mode
The DS90UB928Q-Q1 is also backward compatible to the DS90UR905Q and DS90UR907Q FPD-Link II
serializes with 15 MHz to 65 MHz PCLK frequencies supported. It receives 28-bits of data over a single serial
FPD-Link II pair operating at a payload rate of 420 Mbps to 1.82 Gbps. This backward compatibility configuration
is provided through the MODE_SEL pin or programmed through the device control registers (Table 8). The
bidirectional control channel, bidirectional GPIOs, I2S, and interrupt (INTB) are not active in this mode. However,
local I2C access to the serializer is still available.
8.3.4 Input Equalization
An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces
medium-induced deterministic jitter. It supports STP cables up to 10 meters total cable length with 3 inline
connectors at maximum serializer stream payload rate of 2.975 Gbps.
The adaptive equalizer may be set to a Long Cable Mode (LCBL), using the MODE_SEL pin (Table 6). This
mode is typically used with longer cables where it may be desirable to start adaptive equalization from a higher
default gain. In this mode, the device attempts to lock from a minimum floor AEQ value, defined by a value
stored in the control registers (Table 8).
8.3.5 Common Mode Filter Pin (CMF)
The deserializer provides access to the center tap of the internal CML termination. A 0.1 μF capacitor must be
connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 41). This
increases noise rejection capability in high-noise environments.
8.3.6 Power Down (PDB)
The deserializer has a PDB input pin to enable or power down the device. This pin may be controlled by an
external device, or through VDDIO, where VDDIO = 3 V to 3.6 V or VDD33. To save power, disable the link when the
display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before VDD33 and VDDIO have
reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before
releasing or driving high (See ). If the PDB is pulled up to VDDIO = 3 V to 3.6 V or VDD33 directly, a 10 kΩ pullup
resistor and a >10 µF capacitor to ground are required (see ).
Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,
PDB must be held low for a minimum of 2 ms (see ).
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Feature Description (continued)
8.3.7 Video Control Signals
The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations
relative to the video pixel clock period (PCLK). By default, the device applies a minimum pulse width filter on
these signals to help eliminate spurious transitions.
Normal Mode Control Signals (VS, HS, DE) have the following restrictions:
• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 8. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum
pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 8. DE can have at most two transitions per 130 PCLKs.
8.3.8 EMI Reduction Features
8.3.8.1 LVCMOS VDDIO Option
The 1.8 V/3.3 V LVCMOS inputs and outputs are powered from a separate VDDIO supply pin to offer
compatibility with external system interface signals. Note: When configuring the VDDIO power supplies, all the
single-ended control input pins (except PDB) for device need to scale together with the same operating VDDIO
levels. If VDDIO is selected to operate in the 3.0 V to 3.6 V range, VDDIO must be operated within 300 mV of VDD33
(See Recommended Operating Conditions).
8.3.9 Built In Self Test (BIST)
An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high-speed serial link and the lowspeed back channel without external data connections. This is useful in the prototype stage, equipment
production, in-system test, and system diagnostics.
8.3.9.1 BIST Configuration and Status
The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may
select either an external PCLK or the 33 MHz internal oscillator clock (OSC) frequency. In the absence of PCLK,
the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration
register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the back
channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received
containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel
frame.
The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a
half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.
See Figure 20 for the BIST mode flow diagram.
8.3.9.1.1 Sample BIST Sequence
1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the
deserializer BISTC pin.
2. The serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced,
scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer
and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer
goes high, and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the
PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be
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Feature Description (continued)
monitored and counted to determine the payload error rate.
3. To stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test
result is held on the PASS pin. If the test ran error free, the PASS output remains HIGH. If there one or more
errors were detected, the PASS output outputs constant LOW. The PASS output state is held until a new
BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may
be of any length.
The link returns to normal operation after the deserializer BISTEN pin is low. Figure 21 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In
most cases it is difficult to generate errors due to the robustness of the link (differential data transmission, and so
forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or
reducing signal condition enhancements (Rx equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 20. BIST Mode Flow Diagram
8.3.9.2 Forward Channel and Back Channel Error Checking
The deserializer, on locking to the serial stream, compares the recovered serial stream with all zeroes and
records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer.
Forward channel errors may also be read from register 0x25 (Table 8).
The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,
as indicated by link detect status (register bit 0x1C[0] - Table 8). CRC errors are recorded in an 8-bit register in
the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer
enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST
mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or
the serializer enters BIST mode again.
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Feature Description (continued)
DES Outputs
BISTEN
(DES)
TxCLKOUT
Case 1 - Pass
TxOUT[3:0]
7 bits/frame
DATA
(internal)
PASS
Prior Result
PASS
DATA
(internal)
PASS
X
X
X
FAIL
Prior Result
Normal
SSO
Case 2 - Fail
X = bit error(s)
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 21. BIST Waveforms
8.3.10 Internal Pattern Generation
The DS90UB928Q-Q1 deserializer features an internal pattern generator. It allows basic testing and debugging
of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of
panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no
input is applied. If no clock is received, the test pattern can be configured to use a programmed oscillator
frequency. For detailed information, refer to TI Application Note: (AN-2198).
8.3.10.1 Pattern Options
The DS90UB928Q-Q1 deserializer pattern generator is capable of generating 17 default patterns for use in basic
testing and debugging of panels. Each pattern can be inverted using register bits (see Table 8). The 17 default
patterns are listed as follows:
1. White/Black (default/inverted)
2. Black/White
3. Red/Cyan
4. Green/Magenta
5. Blue/Yellow
6. Horizontally Scaled Black to White/White to Black
7. Horizontally Scaled Black to Red/Cyan to White
8. Horizontally Scaled Black to Green/Magenta to White
9. Horizontally Scaled Black to Blue/Yellow to White
10. Vertically Scaled Black to White/White to Black
11. Vertically Scaled Black to Red/Cyan to White
12. Vertically Scaled Black to Green/Magenta to White
13. Vertically Scaled Black to Blue/Yellow to White
14. Custom Color / Inverted configured in PGRS
15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL)
16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL
17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the autoscrolling feature
22
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Feature Description (continued)
8.3.10.2 Color Modes
By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue
outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 8). In 18-bit
mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least
significant bits are 0.
8.3.10.3 Video Timing Modes
The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern
Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not
present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel
clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator
uses custom video timing as configured in the control registers. The internal timing generation may also be
driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with
External Clock are enabled by the control registers (Table 8). If internal clock generation is used, register 0x39
bit 1 must be set.
8.3.10.4 External Timing
In external timing mode, the pattern generator passes the incoming DE, HS, and VS signals unmodified to the
video control outputs after a two-pixel clock delay. It extracts the active frame dimensions from the incoming
signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS
signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without
DE asserted.
8.3.10.5 Pattern Inversion
The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes
the output pattern to be bitwise-inverted. For example, the full-screen Red pattern becomes full-screen cyan, and
the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.
8.3.10.6 Auto Scrolling
The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of
enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may
appear in any order in the sequence and may also appear more than once.
8.3.10.7 Additional Features
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It
consists of the Pattern Generator Indirect Address (PGIA — Table 8) and the Pattern Generator Indirect Data
(PGID — Table 8).
8.3.11 Image Enhancement Features
Several image enhancement features are provided. The White Balance LUTs allow the user to define and map
the color profile of the display. Adaptive Hi-FRC Dithering enables the presentation of 'true color' images on an
18-bit display.
8.3.11.1 White Balance
The White Balance feature enables similar display appearance when using LCD’s from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, and B to
maintain specified color temperature. Programmable control registers are used to define the contents of three
LUTs (8-bit color value for Red, Green and Blue) for the White Balance Feature. The LUTs map input RGB
values to new output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256
entries, 8-bits per entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable.
Calibrated values are loaded into registers through the I2C interface (deserializer is a slave device). This feature
may also be applied to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is
enabled and configured via serial control bus register.
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Feature Description (continued)
8.3.11.1.1 LUT Contents
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to “0” by the user.
When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique
8-bit entries. The 8-bit white balanced data is then available at the output of the deserializer, and driven to the
display.
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to “0” by the user. When 24-bit (888) input data is being driven to a 24bit display, each LUT (R, G and B) must contain 256 unique 8-bit entries. The 8-bit white balanced data is then
available at the output of the deserializer, and driven to the display.
Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode
of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white
point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are
available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the
deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the
user must configure the deserializer to enable the FRC2 function.
Examples of the three types of LUT configurations described are shown in Figure 22.
8.3.11.1.2 Enabling White Balance
The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be
followed by the user.
To initialize white balance after power-on:
1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third
BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance. By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature via the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller via I2C. This provides the user with the
flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT values. The
host controller loads the updated LUT values via the serial bus interface. There is no need to disable the white
balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be
seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When
reloading, partial LUT updates may be made.
24
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Feature Description (continued)
8-bit in / 8 bit out
Gray level
Entry
Data Out
(8-bits)
00000000b
N/A
N/A
N/A
00000100b
N/A
N/A
N/A
00001000b
N/A
N/A
N/A
248
249
250
251
252
253
254
255
11111000b
N/A
N/A
N/A
11111100b
N/A
N/A
N/A
0
1
2
3
4
5
6
7
8
9
10
11
00000001b
N/A
N/A
N/A
00000110b
N/A
N/A
N/A
00001011b
N/A
N/A
N/A
248
249
250
251
252
253
254
255
11111010b
N/A
N/A
N/A
11111111b
N/A
N/A
N/A
«
«
0
1
2
3
4
5
6
7
8
9
10
11
Data Out
(8-bits)
«
11111010b
11111010b
11111011b
11111011b
11111110b
11111101b
11111101b
11111111b
Data Out
(8-bits)
«
248
249
250
251
252
253
254
255
6-bit in / 8 bit out
Gray level
Entry
«
00000000b
00000001b
00000011b
00000011b
00000110b
00000110b
00000111b
00000111b
00001000b
00001010b
00001001b
00001011b
«
0
1
2
3
4
5
6
7
8
9
10
11
6-bit in / 6 bit out
Gray level
Entry
Figure 22. White Balance LUT Configuration
8.3.11.2 Adaptive Hi-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per sub-pixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled via serial control bus register. Two FRC functional blocks are available, and may be independently
enabled. FRC1 precedes the white balance LUT, and is intended to be used when 24-bit data is being driven to
an 18-bit display with a white balance LUT that is calibrated for an 18-bit data source. The second FRC block,
RC2, follows the white balance block and is intended to be used when fine adjustment of color temperature is
required on an 18-bit color display, or when a 24-bit source drives an 18-bit display with a white balance LUT
calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to device control registers via the serial bus
interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off subpixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 23. The 1 or 0 value shown in the table
describes whether the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated
LSBs are “001”.
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Feature Description (continued)
Frame = 0, Line = 0
F0L0
Pixel Index
PD1
Pixel Data one
Cell Value 010
R[7:2]+0, G[7:2]+1, B[7:2]+0
LSB=001
three lsb of 9 bit data (8 to 9 for Hi-Frc)
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
F0L0
010
000
000
000
000
000
010
000
F0L1
101
000
000
000
101
000
000
000
R = 4/32
F0L2
000
000
010
000
010
000
000
000
G = 4/32
F0L3
000
000
101
000
000
000
101
000
B = 4/32
F1L0
000
000
000
000
000
000
000
000
F1L1
000
111
000
000
000
111
000
000
R = 4/32
F1L2
000
000
000
000
000
000
000
000
G = 4/32
F1L3
000
000
000
111
000
000
000
111
B = 4/32
F2L0
000
000
010
000
010
000
000
000
F2L1
000
000
101
000
000
000
101
000
R = 4/32
F2L2
010
000
000
000
000
000
010
000
G = 4/32
F2L3
101
000
000
000
101
000
000
000
B = 4/32
F3L0
000
000
000
000
000
000
000
000
F3L1
000
000
000
111
000
000
000
111
R = 4/32
F3L2
000
000
000
000
000
000
000
000
G = 4/32
F3L3
000
111
000
000
000
111
000
000
B = 4/32
LSB=001
LSB = 001
Figure 23. Default FRC Algorithm
8.3.12 Serial Link Fault Detect
The DS90UB928Q-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the
Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x1C (Table 8). The device will detect any of
the following conditions:
1. Cable open
2. RIN+ to - short
3. RIN+ to GND short
4. RIN- to GND short
5. RIN+ to battery short
6. RIN- to battery short
7. Cable is linked incorrectly (RIN+/RIN- connections reversed)
NOTE
The device will detect any of the above conditions, but does not report specifically which
one has occurred.
8.3.13 Oscillator Output
The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost.
This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable)
Table 8.
8.3.14 Interrupt Pin (INTB / INTB_IN)
1. Read ISR register 0xC7 (Table 8)
2. On the serializer, set register (ICR) 0xC6[5] = 1 and 0xC6[0] = 1 (Table 8) to configure the interrupt.
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Feature Description (continued)
3. On the serializer, read from ISR register 0xC7 to arm the interrupt for the first time.
4. When INTB_IN is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.
5. The external controller detects INTB = LOW and reads the ISR register (Table 8) to determine the interrupt
source. Reading this register also clears and resets the interrupt.
The INTB_IN signal is sampled and required approximately 8.6 µs of the minimum setup and hold time.
8.6 µs = 30 bit per back channel fram / ( 5 Mbps rate × ±30% Variation) = 30 / (5e6 × 0.7)
Note that -30% is the worst case.
8.3.15 General-Purpose I/O
8.3.15.1 GPIO[3:0]
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back
channel (inputs) mode. GPIO modes may be configured from the registers (Table 8). GPIO[1:0] are dedicated
pins and GPIO[3:2] are shared with I2S_DC and I2S_DD respectively. Note: if the DS90UB928Q-Q1 is paired
with a DS90UB925Q-Q1 serializer, the devices must be configured into 18-bit mode to allow usage of GPIO pins
on the serializer. To enable 18-bit mode, set serializer register 0x12[2] = 1. 18-bit mode will be auto-loaded into
the deserializer from the serializer. See Table 2 for GPIO enable and configuration.
Table 1. DS90UB925Q-Q1 GPIO Enable and Configuration
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
GPIO3
DS90UB925Q-Q1
0x0F = 0x03
0x0F = 0x05
DS90UB928Q-Q1
0x1F = 0x05
0x1F = 0x03
DS90UB925Q-Q1
0x0E = 0x30
0x0E = 0x50
DS90UB928Q-Q1
0x1E = 0x50
0x1E = 0x30
GPIO1/GPIO1
(SER/DES)
DS90UB925Q-Q1
N/A
0x0E = 0x05
DS90UB928Q-Q1
N/A
0x1E = 0x03
GPO_REG5/GPIO1
(SER/DES)
DS90UB925Q-Q1
0x10 = 0x03
N/A
DS90UB928Q-Q1
0x1E = 0x05
N/A
GPIO0/GPIO0
(SER/DES)
DS90UB925Q-Q1
N/A
0x0D = 0x05
DS90UB928Q-Q1
N/A
0x1D = 0x03
GPO_REG4/GPIO0
(SER/DES)
DS90UB925Q-Q1
0x0F = 0x30
N/A
DS90UB928Q-Q1
0x1D = 0x05
N/A
GPIO2
Table 2. DS90UB927Q-Q1 GPIO Enable and Configuration
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
GPIO3
DS90UB927Q-Q1
0x0F = 0x03
0x0F = 0x05
DS90UB928Q-Q1
0x1F = 0x05
0x1F = 0x03
DS90UB927Q-Q1
0x0E = 0x30
0x0E = 0x50
DS90UB928Q-Q1
0x1E = 0x50
0x1E = 0x30
DS90UB927Q-Q1
0x0E = 0x03
0x0E = 0x05
DS90UB928Q-Q1
0x1E = 0x05
0x1E = 0x03
DS90UB927Q-Q1
0x0D = 0x03
0x0D = 0x05
DS90UB928Q-Q1
0x1D = 0x05
0x1D = 0x03
GPIO2
GPIO1
GPIO0
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The input value present on GPIO[3:0] may also be read from register, or configured to local output mode
(Table 8).
8.3.15.2 GPIO[8:5]
GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local
register bits only. Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into
GPIO_REG mode. See Table 3 for GPIO enable and configuration.
Note: Local GPIO value may be configured and read either through local register access, or remote register
access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not
transported from serializer to deserializer as is the case for GPIO[3:0].
Table 3. GPIO_REG and GPIO Local Enable and Configuration
DESCRIPTION
REGISTER CONFIGURATION
GPIO_REG8
0x21 = 0x01
Output, L
0x21 = 0x09
Output, H
0x21 = 0x03
Input, Read: 0x6F[0]
GPIO_REG7
GPIO_REG6
GPIO_REG5
GPIO3
GPIO2
GPIO1
GPIO0
FUNCTION
0x21 = 0x01
Output, L
0x21 = 0x09
Output, H
0x21 = 0x03
Input, Read: 0x6E[7]
0x20 = 0x01
Output, L
0x20 = 0x09
Output, H
0x20 = 0x03
Input, Read: 0x6E[6]
0x20 = 0x01
Output, L
0x20 = 0x09
Output, H
0x20 = 0x03
Input, Read: 0x6E[5]
0x1F = 0x01
Output, L
0x1F = 0x09
Output, H
0x1F = 0x03
Input, Read: 0x6E[3]
0x1E = 0x01
Output, L
0x1E = 0x09
Output, H
0x1E = 0x03
Input, Read: 0x6E[2]
0x1E = 0x01
Output, L
0x1E = 0x09
Output, H
0x1E = 0x03
Input, Read: 0x6E[1]
0x1D = 0x01
Output, L
0x1D = 0x09
Output, H
0x1D = 0x03
Input, Read: 0x6E[0]
8.3.16 I2S Audio Interface
The DS90UB928Q-Q1 deserializer features six I2S output pins that, when paired with a DS90UB927QQ1serializer, supports surround-sound audio applications. The bit clock (I2S_CLK) supports frequencies between
1 MHz and the smaller of <PCLK/2 or <13 MHz. Four I2S data outputs carry two channels of I2S-formatted
digital audio each, with each channel delineated by the word select (I2C_WC) input. The I2S audio interface is
not available in Backwards Compatibility Mode (BKWD = 1).
Deserializer
MCLK
I2S_CLK
I2S_WC
I2S_Dx
System Clock
Bit Clock
Word Select 4
Data
I2S Receiver
Figure 24. I2S Connection Diagram
28
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I2S_WC
I2S_CLK
I2S_Dx
MSB
LSB
MSB
LSB
Figure 25. I2S Frame Timing Diagram
When paired with a DS90UB925Q-Q1, the DS90UB928Q-Q1 I2S interface supports a single I2S data output
through I2S_DA (24-bit video mode), or two I2S data outputs through I2S_DA and I2S_DB (18-bit video mode).
8.3.16.1 I2S Transport Modes
By default, packetized audio is received during video blanking periods in dedicated data island transport frames.
The transport mode is set in the serializer and auto-loaded into the deserializer by default. The audio
configuration may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired.
In frame transport, only I2S_DA is received to the DS90UB928Q-Q1 deserializer. Surround Sound Mode, which
transmits all four I2S data inputs (I2S_D[D:A]), may only be operated in Data Island Transport mode. This mode
is only available when connected to a DS90UB927Q-Q1 serializer. If connected to a DS90UB925Q-Q1serializer,
only I2S_DA and I2S_DB may be received.
8.3.16.2 I2S Repeater
I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via data
island transport on the FPD-Link interface during the video blanking periods. If frame transport is desired,
connect the I2S pins from the deserializer to all serializers. Activating surround-sound at the top-level serializer
automatically configures downstream serializers and deserializers for surround-sound transport utilizing Data
Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode must be explicitly
set in each serializer and deserializer control register throughout the repeater tree (Table 8).
A DS90UB928Q-Q1 deserializer configured in repeater mode may also regenerate I2S audio from its I2S input
pins in lieu of data island frames. See the Repeater Connection Diagram (Figure 35) and the I2C Control
Registers (Table 8) for additional details.
8.3.16.3 I2S Jitter Cleaning
The DS90UB928Q-Q1 features a standalone PLL to clean the I2S data jitter, supporting high-end car audio
systems. If I2S_CLK frequency is less than 1MHz, this feature must be disabled through register 0x2B[7]. See
Table 8.
8.3.16.4 MCLK
The deserializer has an I2S Master Clock Output (MCLK). It supports ×1, ×2, or ×4 of I2S CLK Frequency. When
the I2S PLL is disabled, the MCLK output is off. Table 4 covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are ×2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bits 0x3A[6:4] (I2S DIVSEL), shown in Table 8. To select
desired MCLK frequency, write 0x3A[7], then write to bit [6:4] accordingly.
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Table 4. Audio Interface Frequencies
SAMPLE RATE
(kHz)
I2S DATA WORD SIZE (BITS)
32
1.024
44.1
48
1.4112
16
96
6.144
32
1.536
44.1
2.117
24
96
9.216
32
2.048
44.1
2.8224
32
96
192
30
2.304
4.608
192
48
1.536
3.072
192
48
I2S_CLK (MHz)
3.072
6.144
12.288
MCLK OUTPUT (MHz)
REGISTER 0x3A[6:4]'b
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
I2S_CLK x1
011
I2S_CLK x2
100
I2S_CLK x4
101
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
I2S_CLK x1
011
I2S_CLK x2
100
I2S_CLK x4
110
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8.4 Device Functional Modes
8.4.1 Clock and Output Status
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the deserializer completes its lock sequence to the input serial
data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available
on the LVCMOS and LVDS outputs. The state of the outputs is based on the OEN and OSS_SEL setting
(Table 5) or register bit (Table 8).
Table 5. Output State Table
INPUTS
SERIAL
INPUT
OUTPUTS
LOCK
PASS
DATA/GPIO/I2S
TxCLKOUT/Tx
OUT[3:0]
X
Z
Z
Z
Z
L
L or H
L
L
L
H
L or H
Z
Z
Z
PDB
OEN
OSS_SEL
X
L
X
X
H
L
X
H
L
Static
H
H
L
L
L
L
L/OSC (Register
EN)
L
Static
H
H
H
L
Previous Status
L
Active
H
H
L
L
L
L
L
Active
H
H
H
H
Valid
Valid
Valid
8.4.2 FPD-Link Input Frame and Color Bit Mapping Select
The DS90UB928Q-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2
different mapping schemes, shown in Figure 26, or MSBs on TxOUT[3], shown in Figure 27. Each frame
corresponds to a single pixel clock (PCLK) cycle. The LVDS clock output from TxCLKOUT± follows a 4:3 duty
cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending
with two high. The mapping scheme is controlled by MAPSEL pin or by Register (Table 8).
TxCLKOUT
Previous cycle
Current cycle
TxOUT3
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
G[0]
(bit 23)
R[1]
(bit 22)
R[0]
(bit 21)
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[7]
(bit 17)
B[6]
(bit 16)
B[5]
(bit 15)
B[4]
(bit 14)
TxOUT1
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
TxOUT0
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
Figure 26. 24-bit Color FPD-Link Mapping: LSBs on TxOUT3 (MAPSEL=L)
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TxCLKOUT
Previous cycle
Current cycle
TxOUT3
B[7]
(bit 26)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
R[7]
(bit 22)
R[6]
(bit 21)
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
TxOUT1
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
TxOUT0
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 27. 24-bit ColorFPD-Link Mapping: MSBs on TxOUT3 (MAPSEL=H)
TxCLKOUT
Previous cycle
Current cycle
TxOUT3
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
TxOUT1
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
TxOUT0
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 28. 18-bit Color FPD-Link Mapping (MAPSEL = L)
TxCLKOUT
Previous cycle
Current cycle
TxOUT3
DE
(bit 20)
TxOUT2
B[5]
(bit 26)
B[4]
(bit 25)
G[5]
(bit 24)
G[4]
(bit 23)
R[5]
(bit 22)
R[4]
(bit 21)
VS
(bit 19)
HS
(bit 18)
B[3]
(bit 17)
B[2]
(bit 16)
B[1]
(bit 15)
B[0]
(bit 14)
G[3]
(bit 11)
G[2]
(bit 10)
G[1]
(bit 9)
G[0]
(bit 8)
R[2]
(bit 4)
R[1]
(bit 3)
R[0]
(bit 2)
TxOUT1
R[3]
(bit 5)
TxOUT0
Figure 29. 18-bit Color FPD-Link Mapping (MAPSEL = H)
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8.4.3 Low Frequency Optimization (LFMODE)
The LFMODE is set via register (Table 8) or by the LFMODE Pin. This mode optimizes device operation for
lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE=0, default), the
TxCLKOUT± PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High (LFMODE=1), the
TxCLKOUT± frequency is between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB
reset is required. When LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by
four. Thus, for the operating range of 5 MHz to <15 MHz, the line rate is 700 Mbps to <2.1 Gbps with an effective
data payload of 175 Mbps to 525 Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative
to the input data rate remains the same.
8.4.4 Mode Select (MODE_SEL)
Device configuration may be done via the MODE_SEL pin or via register (Table 7). A pullup resistor and a
pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (VR4) and
VDD33 to select one of the 9 possible selected modes. See Figure 30 and Table 6.
VDD33
R3
VR4
MODE_SEL
R4
Deserializer
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Figure 30. MODE_SEL Connection Diagram
Table 6. Configuration Select (MODE_SEL)
NO.
Ideal Ratio
(VR4/VDD33)
Ideal
VR4 (V)
Suggested
Resistor R3
(kΩ, 1% tol)
Suggested
Resistor R4
(kΩ, 1% tol)
REPEAT
BKWD
I2S_B
LCBL
1
0
0
OPEN
40.2
L
L
L
L
2
0.120
0.397
29.4
4.02
L
L
H
L
3
0.164
0.540
25.5
4.99
H
L
L
L
4
0.223
0.737
26.7
7.68
H
L
H
L
5
0.286
0.943
25.5
10.2
L
L
L
H
6
0.365
1.205
22.6
13.0
L
L
H
H
7
0.446
1.472
20.5
16.5
H
L
L
H
8
0.541
1.786
16.2
19.1
H
L
H
H
9
0.629
2.075
12.4
21.0
L
H
L
L
8.4.5 Repeater Configuration
The supported Repeater application provides a mechanism to extend transmission over multiple links to multiple
display devices.
For the repeater application, this document refers to the DS90UB927Q-Q1 or DS90UB925Q-Q1 as the
Transmitter (TX), and refers to the DS90UB928Q-Q1 or DS90UB926Q-Q1 as the Receiver (RX). shows the
maximum configuration supported for Repeater implementations. Two levels of Repeaters are supported with a
maximum of three Transmitters per Receiver.
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1:3 Repeater
1:3 Repeater
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
RX
TX
Source
TX
RX
TX
TX
1:3 Repeater
RX
1:3 Repeater
RX
Figure 31. Maximum Repeater Application
In a repeater application, the I2C interface at each TX and RX is configured to transparently pass I2C
communications upstream or downstream to any I2C device within the system. This includes a mechanism for
assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.
Repeater Node
Transmitter
I2C
Master
Upstream
Transmitter
Downstream
Receiver
or
Repeater
I2C
Slave
I2C
FPD-Link
(LVDS)
Receiver
Transmitter
I2S Audio
Downstream
Receiver
or
Repeater
I2C
Slave
FPD-Link III interfaces
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Figure 32. 1:2 Repeater Configuration
34
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8.4.5.1 Repeater Connections
The Repeater requires the following connections between the Receiver and each Transmitter Figure 35.
1. Video Data – Connect all FPD-Link data and clock pairs
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 or VDDIO = 3.0 V to 3.6 V with
4.7 kΩ resistors.
3. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. REPEAT & MODE_SEL pins — All Transmitters and Receivers must be set into Repeater Mode.
6. Interrupt pin – Connect DS90UB928Q-Q1 INTB_IN pin to the DS90UB927Q-Q1 INTB pin. The signal must
be pulled up to VDDIO with a 10 kΩ resistor.
Deserializer
VDD33
Serializer
TxOUT0+
RxIN0+
TxOUT0-
RxIN0-
TxOUT1+
RxIN1+
TxOUT1-
RxIN1-
TxOUT2+
RxIN2+
TxOUT2-
RxIN2-
TxOUT3+
RxIN3+
TxOUT3-
RxIN3-
TxCLKOUT+
RxCLKIN+
TxCLKOUT-
RxCLKIN-
MODE_SEL
VDD33
REPEAT
I2S_CLK
I2S_CLK
I2S_WC
I2S_WC
I2S_Dx
I2S_Dx
Optional
VDD33
VDD33
VDDIO
IDx
INTB
INTB_IN
IDx
VDD33
SDA
SDA
SCL
SCL
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Figure 33. Repeater Connection Diagram
8.4.5.1.1 Repeater Fan-Out Electrical Requirements
Repeater applications requiring fan-out from one DS90UB928Q-Q1 deserializer to up to three DS90UB927Q-Q1
serializers requires special considerations for routing and termination of the FPD-Link differential traces.
Figure 36 details the requirements that must be met for each signal pair:
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L3 < 60 mm
TX
RX
R1=100
TX
R2=100
L1 < 75 mm
L2 < 60 mm
TX
L3 < 60 mm
Figure 34. FPD-Link Fan-Out Electrical Requirements
8.4.6 Repeater Connections
The Repeater requires the following connections between the Receiver and each Transmitter Figure 35.
1. Video Data – Connect all FPD-Link data and clock pairs
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 or VDDIO = 3 V to 3.6 V with
4.7 kΩ resistors.
3. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. REPEAT & MODE_SEL pins — All Transmitters and Receivers must be set into Repeater Mode.
6. Interrupt pin – Connect DS90UB928Q-Q1 INTB_IN pin to the DS90UB927Q-Q1 INTB pin. The signal must
be pulled up to VDDIO with a 10 kΩ resistor.
36
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Deserializer
Serializer
TxOUT0+
RxIN0+
TxOUT0-
RxIN0-
TxOUT1+
RxIN1+
TxOUT1-
RxIN1-
TxOUT2+
RxIN2+
TxOUT2-
RxIN2-
TxOUT3+
RxIN3+
TxOUT3-
RxIN3-
TxCLKOUT+
RxCLKIN+
TxCLKOUT-
RxCLKIN-
VDD33
MODE_SEL
VDD33
REPEAT
I2S_CLK
I2S_CLK
I2S_WC
I2S_WC
I2S_Dx
I2S_Dx
Optional
VDD33
VDD33
VDDIO
IDx
INTB
INTB_IN
IDx
VDD33
SDA
SDA
SCL
SCL
Copyright © 2016, Texas Instruments Incorporated
Figure 35. Repeater Connection Diagram
8.4.6.1 Repeater Fan-Out Electrical Requirements
Repeater applications requiring fan-out from one DS90UB928Q-Q1 deserializer to up to three DS90UB927Q-Q1
serializers requires special considerations for routing and termination of the FPD-Link differential traces.
Figure 36 details the requirements that must be met for each signal pair:
L3 < 60 mm
TX
RX
R1=100
TX
R2=100
L1 < 75 mm
L2 < 60 mm
TX
L3 < 60 mm
Figure 36. FPD-Link Fan-Out Electrical Requirements
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8.5 Programming
8.5.1 Serial Control Bus
The DS90UB928Q-Q1 may also be configured by the use of an I2C compatible serial control bus. Multiple
devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a
resistor divider (R1 and R2 — see Figure 37) connected to the IDx pin.
VDD33
VDD33
R1
VR2
4.7kQ
4.7kQ
IDx
R2
HOST
DES
SCL
SCL
SDA
SDA
To other
Devices
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Figure 37. Serial Control Bus Connection
The serial control bus consists of two signals and an address configuration pin. SCL is a Serial Bus Clock
Input/Output. SDA is the Serial Bus Data Input/Output signal. Both SCL and SDA signals require an external
pullup resistor to VDD33 or VDDIO = 3 V to 3.6 V. For most applications, a 4.7 kΩ pullup resistor to VDD33 is
recommended. The signals are either pulled HIGH, or driven LOW.
The IDx pin configures the control interface to one of 10 possible device addresses. Use a pullup resistor and a
pulldown resistor to set the appropriate voltage ratio between the IDx input pin (VR2) and VDD33, each ratio
corresponding to a specific device address. See .
Table 7. Serial Control Bus Addresses for IDx
NO.
IDEAL RATIO
VR2 / VDD33
IDEAL VR2
(V)
SUGGESTED
RESISTOR R1 kΩ
(1% tol)
SUGGESTED
RESISTOR R2 kΩ
(1% tol)
ADDRESS 7'b
ADDRESS 8'b
1
0
0
OPEN
40.2
0x2C
0x58
2
0.302
0.995
22.6
9.76
0x33
0x66
3
0.345
1.137
21.5
11.3
0x34
0x68
4
0.388
1.282
20.0
12.7
0x35
0x6A
5
0.428
1.413
18.7
14.0
0x36
0x6C
6
0.476
1.570
17.4
15.8
0x37
0x6E
7
0.517
1.707
15.4
16.5
0x38
0x70
8
0.560
1.848
15.0
19.1
0x39
0x72
9
0.605
1.997
13.7
21.0
0x3A
0x74
10
0.768
2.535
9.09
30.1
0x3B
0x76
38
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The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 38.
SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 38. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus LOW. If the address doesn't
match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled HIGH.
ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the master is reading data, the master ACKs after every
data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 39 and a WRITE is shown in Figure 40.
Register Address
Slave Address
A
2
S
A
1
A
0
0
Slave Address
a
c
k
a
c
k
A
2
S
A
1
A
0
Data
a
c
a
c
k
1 k
P
Figure 39. Serial Control Bus — READ
Register Address
Slave Address
A
2
S
A
1
A
0
Data
a
c
k
a
c
k
a
0 ck
P
Figure 40. Serial Control Bus — WRITE
To support I2C transactions over the BCC. the I2C Master located at the DS90UB928Q-Q1 deserializer must
support I2C clock stretching. For more information on I2C interface requirements and throughput considerations,
refer to AN-2173 I2C Communication Over FPD-Link III with Bidirectional Control Channel SNLA131.
8.6 Register Maps
Table 8. Serial Control Bus Registers (1)
(2)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
0
0x00
I2C Device ID
7:1
RW
IDx
Device ID
7–bit address of Deserializer
Note: Read-only unless bit 0 is set
0
RW
ID Setting
I2C ID Setting
0: Device ID is from IDx pin
1: Register I2C Device ID overrides IDx pin
(1)
(2)
Addresses not listed are reserved.
Do not alter Reserved fields from their default values.
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
1
0x01
Reset
7:3
2
40
0x02
General
Configuration 0
Register
Type
Default
(hex)
Function
0x04
Description
Reserved
2
RW
BC Enable
Back Channel Enable
0: Disable
1: Enable
1
RW
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
0: Normal operation (default)
1: Reset
0
RW
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
0: Normal operation (default)
1: Reset
7
RW
OEN
LVCMOS Output Enable. Self-clearing on loss of
LOCK
0: Disable, Tristate Outputs (default)
1: Enable
6
RW
OEN/OSS_
SEL
Override
Output Enable and Output Sleep State Select override
0: Disable over-write (default)
1: Enable over-write
5
RW
Auto Clock
Enable
OSC Clock Output. Enable On loss of lock, OSC
clock is output onto TxCLK±
0: Disable (default)
1: Enable
4
RW
OSS_SEL
Output Sleep State Select. Enable Select to control
output state during lock low period
0: Disable, Tri-State Outputs (default)
1: Enable
3
RW
BKWD
Override
Backwards Compatibility Mode Override
0: Use MODE_SEL pin (default)
1: Use register bit to set BKWD mode
2
RW
BKWD
Mode
Backwards Compatibility Mode Select
0: Backwards Compatibility Mode disabled (default)
1: Backwards Compatibility Mode enabled
1
RW
LFMODE
Override
Low Frequency Mode Override
0: Use LFMODE pin (default)
1: User register bit to set LFMODE
0
RW
LFMODE
Low Frequency Mode
0: 15 MHz ≤ PCLK ≤ 85 MHz (default)
1: 5 MHz ≤ PCLK < 15 MHz
0x00
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
3
0x03
Register Name
Bit
General
Configuration 1
7
Register
Type
Default
(hex)
Function
0xF0
Reserved
6
RW
Back
channel
CRC
Generator
Enable
Back Channel CRC Generator Enable
0: Disable
1: Enable (default)
5
RW
Failsafe
Outputs Failsafe Mode. Determines the pull direction
for undriven LVCMOS inputs
0: Pullup
1: Pulldown (default)
4
RW
Filter
Enable
HS, VS, DE two clock filter. When enabled, pulses
less than two full PCLK cycles on the DE, HS, and VS
inputs will be rejected
0: Filtering disable
1: Filtering enable (default)
3
RW
I2C PassThrough
I2C Pass-Through Mode
Read/Write transactions matching any entry in the
DeviceAlias registers will be passed through to the
remote serializer I2C interface.
0: Pass-Through Disabled (default)
1: Pass-Through Enabled
2
RW
Auto ACK
Automatically Acknowledge I2C transactions
independent of the forward channel Lock state.
0: Disable (default)
1: Enable
1
RW
DE Gate
RGB
Gate RGB data with DE signal. In DS90UH928, RGB
data is gated with DE in order to allow packetized
audio and block unencrypted data. In DS90UB928 or
in Backward Compatibility mode, RGB data is not
gated with DE by default. However, to enable
packetized audio in DS90UB928, this bit must be set.
This bit has no effect in DS90UH928.
0: Pass RGB data independent of DE in Backward
Compatibility mode or interfacing to DS90UB925 or
DS90UB927
1: Gate RGB data with DE in Backward Compatibility
mode or interfacing to DS90UB925 or DS90UB927
0
4
5
0x04
0x05
BCC Watchdog
Control
I2C Control 1
Description
Reserved
7:1
RW
0
RW
7
RW
6:4
3:0
0xFE
BCC
Watchdog
Timer
BCC Watchdog Timer The watchdog timer allows
termination of a control channel transaction if it fails to
complete within a programmed amount of time. This
field sets the Bidirectional Control Channel Watchdog
Timeout value in units of 2 ms. This field should not
be set to 0.
BCC
Watchdog
Disable
Disable Bidirectional Control Channel Watchdog
Timer
0: Enable (default)
1: Disable
I2C PassAll
I2C Pass-Through All Transactions. Pass all local I2C
transactions to the remote serializer.
0: Disable (default)
1: Enable
RW
I2C SDA
Hold
Internal I2C SDA Hold Time
This field configures the amount of internal hold time
is provided for the SDA input relative to the SCL input.
Units are 50 ns.
RW
I2C Filter
Depth
I2C Glitch Filter Depth
This field configures the maximum width of glitch
pulses on the SCL and SDA inputs that will be
rejected. Units are 5 ns.
0x1E
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
6
0x06
I2C Control 2
Bit
Register
Type
Default
(hex)
7
RW
0x00
6
RW
Function
Description
Forward
Channel
Sequence
Error
Control Channel Sequence Error Detected
Indicates a sequence error has been detected in
forward control channel. It this bit is set, an error may
have occurred in the control channel operation.
Clear
Sequence
Error
Clears the Sequence Error Detect bit This bit is not
self-clearing.
5
7
0x07
Remote ID
Reserved
4:3
RW
SDA Output SDA Output Delay
Delay
This field configures output delay on the SDA output.
Setting this value will increase output delay in units of
50ns. Nominal output delay values for SCL to SDA
are:
00: 250 ns (default)
01: 300 ns
10: 350 ns
11: 400 ns
2
RW
Local Write
Disable
Disable Remote Writes to Local Registers through
Serializer (Does not affect remote access to I2C
slaves)
0: Remote write to local device registers (default)
1: Stop remote write to local device registers
1
RW
I2C Bus
Timer
Speedup
Speed up I2C Bus Watchdog Timer
0: Timer expires after approximately 1 s (default)
1: Timer expires after approximately 50 µs
0
RW
I2C Bus
Timer
Disable
Disable I2C Bus Watchdog Timer.
When the I2C Watchdog Timer may be used to detect
when the I2C bus is free or hung up following an
invalid termination of a transaction. If SDA is high and
no signaling occurs for approximately 1 second, the
I2C bus is assumed to be free. If SDA is low and no
signaling occurs, the device will attempt to clear the
bus by driving 9 clocks on SCL
7:1
R
Remote ID
Remote Serializer ID
RW if bit 0 is set
0
RW
Freeze
Device ID
Freeze Serializer Device ID
0: Auto-load Serializer Device ID (default)
1: Prevent auto-loading of Serializer Device ID from
the remote device. The ID will be frozen at the value
written.
RW
0x00
Slave
Device ID0
7-bit Remote Slave Device ID 0
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[0], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
RW
0x00
Slave
Device ID1
8
0x08
Slave ID[0]
7:1
9
0x09
Slave ID[1]
7:1
0x00
0
0
42
Reserved
7-bit Remote Slave Device ID1
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[1], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
10
0x0A
Slave ID[2]
7:1
RW
0x00
Function
Description
Slave
Device ID2
7-bit Remote Slave Device ID2
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[2], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
11
0x0B
Slave ID[3]
7:1
Reserved
RW
0x00
Slave
Device ID3
0
12
0x0C
Slave ID[4]
7:1
Reserved
RW
0x00
Slave
Device ID4
0
13
0x0D
Slave ID[5]
7:1
14
0x0E
Slave ID[6]
7:1
15
0x0F
Slave ID[7]
7:1
16
0x10
Slave Alias[0]
7:1
7-bit Remote Slave Device ID4
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[4], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
RW
0x00
Slave
Device ID5
RW
0x00
Slave
Device ID6
RW
0x00
Slave
Device ID7
RW
0x00
Slave
Device
Alias 0
0
7-bit Remote Slave Device ID5
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[5], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
0
7-bit Remote Slave Device ID6
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[6], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
0
0
7-bit Remote Slave Device ID3
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[3], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
7-bit Remote Slave Device ID 7
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[7], the transaction will be re-mapped to this
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
7-bit Remote Slave Alias 0
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[0], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
17
0x11
Slave Alias[1]
7:1
RW
0x00
Function
Description
Slave
Device
Alias 1
7-bit Remote Slave Alias 1
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[1], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
0
18
0x12
Slave Alias[2]
7:1
Reserved
RW
0x00
Slave
Device
Alias 2
0
19
0x13
Slave Alias[3]
7:1
Reserved
RW
0x00
Slave
Device
Alias 3
0
20
0x14
Slave Alias[4]
7:1
21
0x15
Slave Alias[5]
7:1
22
0x16
Slave Alias[6]
7:1
23
0x17
Slave Alias[7]
7:1
RW
0x00
Slave
Device
Alias 4
RW
0x00
Slave
Device
Alias 5
RW
0x00
Slave
Device
Alias 6
RW
0x00
Slave
Device
Alias 7
7-bit Remote Slave Alias 4
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[4], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
0
7-bit Remote Slave Alias 5
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[5], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
0
44
7-bit Remote Slave Alias 3
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[3], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
0
0
7-bit Remote Slave Alias 2
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[2], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
7-bit Remote Slave Alias 6
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[6], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
7-bit Remote Slave Alias 7
Configures the physical I2C address of the remote
I2C Slave device attached to the remote Serializer. If
an I2C transaction is addressed to the Slave Alias
ID[7], the transaction will be re-mapped to the ID
address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
Reserved
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
24
0x18
Mailbox[0]
7:0
RW
25
0x19
Mailbox[1]
7:0
27
0x1B
Frequency
Counter
7:0
28
0x1C
General Status
7:4
Function
Description
0x00
Mailbox
Register 0
Mailbox Register 0
This register may be used to temporarily store
temporary data, such as status or multi-master
arbitration
RW
0x01
Mailbox
Register 1
Mailbox Register 1
This register may be used to temporarily store
temporary data, such as status or multi-master
arbitration
RW
0x00
Frequency
Count
Frequency Counter control
A write to this register will enable a frequency counter
to count the number of pixel clock during a specified
time interval. The time interval is equal to the value
written multiplied by the oscillator clock period
(nominally 50 ns). A read of the register returns the
number of pixel clock edges seen during the enabled
interval. The frequency counter will saturate at 0xff if it
reaches the maximum value. The frequency counter
will provide a rough estimate of the pixel clock period.
If the pixel clock frequency is known, the frequency
counter may be used to determine the actual oscillator
clock frequency.
0x00
Reserved
3
R
I2S Locked
I2S Lock Status
0: I2S PLL controller not locked (default)
1: I2S PLL controller locked to input I2S clock
2
R
CRC Error
CRC Error Detected
0: No CRC errors detected
1: CRC errors detected
0
R
LOCK
Deserializer CDR and PLL Locked to recovered clock
frequency
0: Deserializer not Locked (default)
1: Deserializer Locked to recovered clock
7:4
R
Revision ID
Device Revision ID:
0010: Production Device
3
RW
GPIO0
Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the
local GPIO direction is Output, and remote GPIO
control is disabled.
0: Output LOW (default)
1: Output HIGH
2
RW
GPIO0
Remote
Enable
Remote GPIO Control
0: Disable GPIO control from remote device (default)
1: Enable GPIO control from remote device. The
GPIO pin will be an output, and the value is received
from the remote device.
1
RW
GPIO0
Direction
Local GPIO Direction
0: Output (default)
1: Input
0
RW
GPIO0
Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
1
29
0x1D
GPIO0
Configuration
Reserved
0x20
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
30
0x1E
31
46
0x1F
Register Name
GPIO1 and
GPIO2
Configuration
GPIO3
Configuration
Bit
Register
Type
Default
(hex)
7
RW
0x00
6
Function
Description
GPIO2
Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the
local GPIO direction is Output, and remote GPIO
control is disabled.
0: Output LOW (default)
1: Output HIGH
RW
GPIO2
Remote
Enable
Remote GPIO Control
0: Disable GPIO control from remote device (default)
1: Enable GPIO control from remote device. The
GPIO pin will be an output, and the value is received
from the remote device.
5
RW
GPIO2
Direction
Local GPIO Direction
0: Output (default)
1: Input
4
RW
GPIO2
Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
3
RW
GPIO1
Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the
local GPIO direction is Output, and remote GPIO
control is disabled.
0: Output LOW (default)
1: Output HIGH
2
RW
GPIO1
Remote
Enable
Remote GPIO Control
0: Disable GPIO control from remote device (default)
1: Enable GPIO control from remote device. The
GPIO pin will be an output, and the value is received
from the remote device.
1
RW
GPIO1
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO1
Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
7:4
0x00
Reserved
3
RW
GPIO3
Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the
local GPIO direction is Output, and remote GPIO
control is disabled.
0: Output LOW (default)
1: Output HIGH
2
RW
GPIO3
Remote
Enable
Remote GPIO Control
0: Disable GPIO control from remote device (default)
1: Enable GPIO control from remote device. The
GPIO pin will be an output, and the value is received
from the remote device.
1
RW
GPIO3
Direction
Local GPIO Direction
0: Output (default)
1: Input
0
RW
GPIO3
Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
32
0x20
Register Name
GPIO_REG5
and
GPIO_REG6
Configuration
Bit
Register
Type
Default
(hex)
7
RW
0x00
Function
Description
GPIO_REG
6 Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, and the
local GPIO direction is Output.
0: Output LOW (default)
1: Output HIGH
6
Reserved
5
RW
GPIO_REG
6 Direction
Local GPIO Direction
0: Output (default)
1: Input
4
RW
GPIO_REG
6 Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
3
RW
GPIO_REG
5 Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, and the
local GPIO direction is Output.
0: Output LOW (default)
1: Output HIGH
1
RW
GPIO_REG
5 Direction
Local GPIO Direction
0: Output (default)
1: Input
0
RW
GPIO_REG
5 Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
7
RW
GPIO_REG
8 Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, and the
local GPIO direction is Output.
0: Output LOW (default)
1: Output HIGH
2
33
0x21
GPIO_REG7
and
GPIO_REG8
Configuration
Reserved
0x00
6
Reserved
5
RW
GPIO_REG
8 Direction
Local GPIO Direction
0: Output (default)
1: Input
4
RW
GPIO_REG
8 Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
3
RW
GPIO_REG
7 Output
Value
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, and the
local GPIO direction is Output.
0: Output LOW (default)
1: Output HIGH
2
Reserved
1
RW
GPIO_REG
7 Direction
Local GPIO Direction
0: Output (default)
1: Input
0
RW
GPO_REG
7 Enable
GPIO Function Enable
0: Enable normal operation (default)
1: Enable GPIO operation
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
34
0x22
Register Name
Data Path
Control
Bit
Register
Type
Default
(hex)
7
RW
0x00
Function
Override FC Override Configuration Loaded by Forward Channel
Configuratio 0: Allow forward channel loading of this register
n
(default)
1: Disable loading of this register from the forward
channel, keeping locally written values intact
Bits [6:0] are RW if this bit is set
6
35
0x23
Rx Mode Status
Reserved
5
RW
DE Polarity
This bit indicates the polarity of the DE (Data Enable)
signal.
0: DE is positive (active high, idle low) (default)
1: DE is inverted (active low, idle high)
4
RW
I2S
Repeater
Regen
Regenerate I2S Data From Repeater I2S Pins
0: Output packetized audio on RGB video output pins.
(default)
1: Repeater regenerates I2S from I2S pins
3
RW
I2S
Channel B
Enable
Override
I2S Channel B Override
0: Set I2S Channel B Disabled (default)
1: Set I2S Channel B Enable from register
2
RW
18-bit Video Video Color Depth Mode
Select
0: Select 24-bit video mode (default)
1: Select 18-bit video mode
1
RW
I2S
Transport
Select
Select I2S Transport Mode
0: Enable I2S Data Island Transport (default)
1: Enable I2S Data Forward Channel Frame
Transport
0
RW
I2S
Channel B
Enable
I2S Channel B Enable
0: I2S Channel B disabled (default)
1: Enable I2S Channel B
7
0x10
Reserved
6:4
36
48
0x24
BIST Control
Description
Reserved
3
R
LFMODE
Status
Low Frequency Mode (LFMODE) pin status
0: 15 MHz ≤ TxCLKOUT ≤ 85 MHz (default)
1: 5 MHz ≤ TxCLKOUT < 15 MHz
2
R
REPEAT
Status
Repeater Mode (REPEAT) pin Status
0: Non-repeater (default)
1: Repeater
1
R
BKWD
Status
Backward Compatible Mode (BKWD) Status
0: Compatible to DS90UB925Q-Q1/DS90UB927Q-Q1
(default)
1: Backward compatible to DS90UR905/7Q
0
R
I2S
Channel B
Status
I2S Channel B Mode (I2S_DB) Status
0: I2S_DB inactive (default)
1: I2S_DB active
7:4
0x08
Reserved
3
RW
BIST Pin
Config
BIST Pin Configuration
0: BIST enabled from register
1: BIST enabled from pin (default)
2:1
RW
OSC Clock
Source
Internal OSC clock select for Functional Mode or
BIST. Functional Mode when PCLK is not present and
0x03[1]=1.
00: 33 MHz Oscillator (default)
01: 33 MHz Oscillator
Note: In LFMODE=1, the internal oscillator is 12.5
MHz
0
RW
BIST
Enable
BIST Control
0: Disabled (default)
1: Enabled
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
37
0x25
BIST Error
7:0
R
38
0x26
SCL High Time
7:0
39
0x27
SCL Low Time
40
0x28
Data Path
Control 2
Function
Description
0x00
BIST Error
Count
Errors Detected During BIST
Records the number (up to 255) of forward-channel
errors detected during BIST. The value stored in this
register is only valid after BIST terminates (BISTEN =
0). Resets on PDB = 0 or start of another BIST
(BISTEN = 1).
RW
0x83
SCL High
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL
output when the deserializer is the Master on the local
I2C bus. Units are 50 ns for the nominal oscillator
clock frequency.
7:0
RW
0x84
SCL Low
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL
output when the deserializer is the Master on the local
I2C bus. This value is also used as the SDA setup
time by the I2C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional
Control Channel. Units are 50 ns for the nominal
oscillator clock frequency.
7
RW
0x00
Block I2S
Override Forward Channel Configuration
Auto Config 0: Enable forward-channel loading of this register
1: Disable loading of this register from the forward
channel, keeping local values intact
6:4
Reserved
3
RW
Aux I2S
Enable
Auxiliary I2S Channel Enable
0: Normal GPIO[1:0] operation
1: Enable Aux I2S channel on GPIO1 (AUX word
select) and GPIO0 (AUX data)
2
RW
I2S Disable
Disable All I2S Outputs
0: I2S Outputs Enabled (default)
1: I2S Outputs Disabled
RW
I2S
Surround
1
0
Reserved
Enable 5.1- or 7.1-channel I2S audio transport
0: 2-channel or 4-channel I2S audio is enabled as
configured in register or MODE_SEL (default)
1: 5.1- or 7.1-channel audio is enabled
Note that I2S Data Island Transport is the only option
for surround audio. Also note that in a repeater, this
bit may be overridden by the in-band I2S mode
detection.
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
41
0x29
FRC Control
42
0x2A
White Balance
Control
Bit
Register
Type
Default
(hex)
7
RW
0x00
6
Function
Description
Timing
Mode
Select
Select Display Timing Mode
0: DE only Mode (default)
1: Sync Mode (VS,HS)
RW
HS Polarity
Horizontal Sync Polarity Select
0: Active High (default)
1: Active Low
5
RW
VS Polarity
Vertical Sync Polarity Select
0: Active High (default)
1: Active Low
4
RW
DE Polarity
Data Enable Sync Polarity Select
0: Active High (default)
1: Active Low
3
RW
FRC2
Enable
FRC2 Enable
0: FRC2 disable (default)
1: FRC2 enable
2
RW
FRC1
Enable
FRC1 Enable
0: FRC1 disable (default)
1: FRC1 enable
1
RW
Hi-FRC2
Enable
Hi-FRC2 Enable
0: Hi-FRC2 enable (default)
1: Hi-FRC2 disable
0
RW
Hi-FRC1
Enable
Hi-FRC1 Enable
0: Hi-FRC1 enable (default)
1: Hi-FRC1 disable
7:6
RW
Page
Setting
Control/LUT Setting Page Select
00: Configuration Registers (default)
01: Red LUT
10: Green LUT
11: Blue LUT
5
RW
White
Balance
Enable
White Balance Enable
0: White Balance Disabled (default)
1: White Balance Enabled
4
RW
LUT Reload Enable LUT Reload
Enable
0: Reload Disable (default)
1: Reload Enable
0x00
3:0
43
0x2B
I2S Control
Reserved
7
RW
6
0x00
I2S PLL
Override
Override I2S PLL
0: PLL override disabled (default)
1: PLL override enabled
RW
I2S PLL
Enable
Enable I2S PLL
0: I2S PLL is on for I2S data jitter cleaning (default)
1: I2S PLL is off. No jitter cleaning
RW
I2S Clock
Edge
5:1
0
50
Reserved
I2S Clock Edge Select
0: I2S Data is strobed on the Falling Clock Edge
(default)
1: I2S Data is strobed on the Rising Clock Edge
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
53
0x35
AEQ Control
Bit
Register
Type
7
Default
(hex)
Function
0x00
Reserved
6
RW
AEQ
Restart
Restart AEQ adaptation from initial (Floor) values
0: Normal operation (default)
1: Restart AEQ adaptation
Note: This bit is not self-clearing. It must be set, then
reset.
5
RW
LCBL
Override
Override LCBL Mode Set by MODE_SEL
0: LCBL controlled by MODE_SEL pin
1: LCBL controlled by register
4
RW
LCBL
Set LCBL Mode
0: LCBL Mode disabled
1: LCBL Mode enabled. AEQ Floor value is controlled
from Adaptive EQ MIN/MAX register
3:0
57
0x39
PG Internal
Clock Enable
Reserved
7:2
1
0x00
RW
Reserved
PG INT
CLK
0
58
0x3A
I2S DIVSEL
65
68
0x3B
RW
6:4
RW
0x41
0x44
Adaptive EQ
Status
7:6
Link Error Count
7:5
Adaptive
Equalizer
Bypass
0x00
MCLK Div
Override
Override MCLK Divider Setting
0: No override for MCLK divider (default)
1: Override divider select for MCLK
MCLK Div
See Table 4
Reserved
Reserved
5:0
EQ Status
0x03
0x45
Adaptive EQ
MIN/MAX
Equalizer Status
Current equalizer level set by AEQ or Override
Register
Reserved
4
RW
Link Error
Count
Enable
Enable serial link data integrity error count
1: Enable error count
0: Disable
3:0
RW
Link Error
Count
Threshold
Link error count threshold. Counter is pixel clock
based. CLK0, CLK1, and DCA are monitored for link
errors, if error count is enabled Deserializer loose lock
once error count reaches threshold if disabled
Deserializer loose lock with one error.
7:5
RW
EQ Stage 1
Select
Value
EQ Stage 1 select value. Used if adaptive EQ is
bypassed. Used if adaptive EQ is bypassed.
0x60
4
69
Enable Pattern Generator Internal Clock
This bit must be set to use the Pattern Generator
Internal Clock Generation
0: Pattern Generator with external PCLK
1: Pattern Generator with internal PCLK
See TI Application Note ( ) for details
Reserved
7
3:0
59
Description
Reserved
3:1
RW
EQ Stage 2
Select
Value
EQ Stage 2 select value. Used if adaptive EQ is
bypassed Used if adaptive EQ is bypassed.
0
RW
Adaptive
EQ Bypass
Bypass Adaptive EQ
Overrides Adaptive EQ search and sets the EQ to the
static value configured in this register
0: Enable adaptive EQ (default)
1: Disable adaptive EQ (to write EQ select values)
7:4
RW
3:0
RW
0x88
Reserved
Adaptive
EQ Floor
Adaptive Equalizer Floor Value
Sets the AEQ floor value when Long Cable Mode
(LCBL) is enabled by register or MODE_SEL
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
Register Name
73
0x49
Map Select
Bit
Register
Type
Default
(hex)
7
R
0x00
6
5
Function
Description
MAPSEL
Pin Status
Returns Status of MAPSEL pin
RW
MAPSEL
Override
Map Select (MAPSEL) Setting Override
0: MAPSEL set from pin
1: MAPSEL set from register
RW
MAPSEL
Map Select (MAPSEL) Setting
0: LSBs on TxOUT3±
1: MSBs on TxOUT3±
4:0
75
0x4B
LVDS Setting
1:0
86
0x56
Loop-Through
Driver
Reserved
7:2
0x08
RW
7:4
3
Reserved
LVDS VOD
Control
0x08
RW
Reserved
LoopThrough
Driver
Enable
2:0
100
0x64
Pattern
Generator
Control
7:4
Enable CML Loop-Through Driver
(CMLOUTP/CMLOUTN)
0: Enable
1: Disable (default)
Reserved
RW
0x10
Pattern
Generator
Select
3
52
00: 400 mV differential (default)
01: 600 mV differential
Fixed Pattern Select
Selects the pattern to output when in Fixed Pattern
Mode. Scaled patterns are evenly distributed across
the horizontal or vertical active regions. This field is
ignored when Auto-Scrolling Mode is enabled.
xxxx: normal/inverted
0000: Checkerboard
0001: White/Black (default)
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontal Black-White/White-Black
0111: Horizontal Black-Red/White-Cyan
1000: Horizontal Black-Green/White-Magenta
1001: Horizontal Black-Blue/White-Yellow
1010: Vertical Black-White/White— Black
1011: Vertically Scaled Black to Red/White to Cyan
1100: Vertical Black-Green/White-Magenta
1101: Vertical Black-Blue/White-Yellow
1110: Custom color (or its inversion) configured in
PGRS, PGGS, PGBS registers
1111: VCOM
See TI App Note AN-2198 ().
Reserved
2
RW
Color Bars
Pattern
Enable Color Bars Pattern
0: Color Bars disabled (default)
1: Color Bars enabled
Overrides the selection from bits [7:4]
1
RW
VCOM
Pattern
Reverse
Reverse order of color bands in VCOM pattern
0: Color sequence from top left is (YCBR) (default)
1: Color sequence from top left is (RBCY)
0
RW
Pattern
Generator
Enable
Pattern Generator Enable
0: Disable Pattern Generator (default)
1: Enable Pattern Generator
See TI App Note AN-2198 ().
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
101
0x65
Register Name
Pattern
Generator
Configuration
Bit
Register
Type
7
Default
(hex)
Function
0x00
Description
Reserved
6
RW
Checkerboa Scale Checkerboard Patterns:
rd Scale
0: Normal operation (each square is 1x1 pixel)
(default)
1: Scale checkered patterns (VCOM and
checkerboard) by 8 (each square is 8x8 pixels)
Setting this bit gives better visibility of the checkered
patterns.
5
RW
Custom
Use Custom Checkerboard Color
Checkerboa 0: Use white and black in the Checkerboard pattern
rd
(default)
1: Use the Custom Color and black in the
Checkerboard pattern
4
RW
PG 18–bit
Mode
18-bit Mode Select:
0: Enable 24-bit pattern generation. Scaled patterns
use 256 levels of brightness. (default)
1: Enable 18-bit color pattern generation. Scaled
patterns will have 64 levels of brightness and the R,
G, and B outputs use the six most significant color
bits.
3
RW
External
Clock
Select External Clock Source:
0: Selects the internal divided clock when using
internal timing (default)
1: Selects the external pixel clock when using internal
timing. This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
2
RW
Timing
Select
Timing Select Control:
0: the Pattern Generator uses external video timing
from the pixel clock, Data Enable, Horizontal Sync,
and Vertical Sync signals. (default)
1: The Pattern Generator creates its own video timing
as configured in the Pattern Generator Total Frame
Size, Active Frame Size. Horizontal Sync Width,
Vertical Sync Width, Horizontal Back Porch, Vertical
Back Porch, and Sync Configuration registers.
1
RW
Color Invert
Enable Inverted Color Patterns:
0: Do not invert the color output. (default)
1: Invert the color output.
0
RW
Auto Scroll
Auto Scroll Enable:
0: The Pattern Generator retains the current pattern.
(default)
1: The Pattern Generator will automatically move to
the next enabled pattern after the number of frames
specified in the Pattern Generator Frame Time
(PGFT) register.
See TI App Note AN-2198 ().
102
0x66
PGIA
7:0
RW
0x00
PG Indirect
Address
This 8-bit field sets the indirect address for accesses
to indirectly-mapped registers. It should be written
prior to reading or writing the Pattern Generator
Indirect Data register.
See TI App Note AN-2198 ().
103
0x67
PGID
7:0
RW
0x00
PG Indirect
Data
When writing to indirect registers, this register
contains the data to be written. When reading from
indirect registers, this register contains the read back
value.
See TI App Note AN-2198 ().
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Register Maps (continued)
Table 8. Serial Control Bus Registers(1) (2) (continued)
ADD
(dec)
ADD
(hex)
110
0x6E
Register Name
Bit
Register
Type
Default
(hex)
GPI Pin Status
1
7
R
0x00
6
5
Function
Description
GPI7 Pin
Status
GPI7 Pin Status. Readable when REG_GPIO7 is set
as an input.
R
GPI6 Pin
Status
GPI6 Pin Status. Readable when REG_GPIO6 is set
as an input.
R
GPI5 Pin
Status
GPI5 Pin Status. Readable when REG_GPIO5 is set
as an input.
3
R
GPI3 Pin
Status
GPI3 Pin Status. Readable when GPIO3 is set as an
input.
2
R
GPI2 Pin
Status
GPI2 Pin Status. Readable when GPIO2 is set as an
input.
1
R
GPI1 Pin
Status
GPI1 Pin Status. Readable when GPIO1 is set as an
input.
0
R
GPI0 Pin
Status
GPI0 Pin Status. Readable when GPIO0 is set as an
input.
4
111
54
0x6F
Reserved
GPI Pin Status
2
7:1
0
R
0x00
RX ID
7:0
R
Reserved
GPI8 Pin
Status
GPI8 Pin Status. Readable when REG_GPIO8 is set
as an input.
0x5F
ID0
First byte ID code, ‘_’
240
0xF0
241
0xF1
7:0
R
0x55
ID1
Second byte of ID code, ‘U’
242
0xF2
7:0
R
0x42
ID2
Third byte of ID code. 'B'
243
0xF3
7:0
R
0x39
ID3
Forth byte of ID code: ‘9’
244
0xF4
7:0
R
0x32
ID4
Fifth byte of ID code: “2”
245
0xF5
7:0
R
0x38
ID5
Sixth byte of ID code: “8”
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90UB928Q-Q1 deserializer, in conjunction with a DS90UB925Q-Q1 or DS90UB927Q-Q1 serializer,
provides a solution for distribution of digital video and audio within automotive infotainment systems. It converts a
high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four
LVDS data/control streams, one LVDS clock pair (FPD-Link), and I2S audio data. The serial bus scheme, FPDLink III, supports high-speed forward channel data transmission and low-speed full duplex back channel
communication over a single differential link. Consolidation of audio, video data and control over a single
differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying
system design.
9.2 Typical Application
Figure 41 shows a typical application of the DS90UB928Q-Q1 deserializer for an 85 MHz 24-bit color display
application. Inputs utilize 0.1 µF coupling capacitors to the line, and the deserializer provides internal termination.
The voltage rating of the coupling capacitors must be ≥50 V and use a small body capacitor size, such as 0402
or 0602, to help ensure good signal integrity. The FPD-Link LVDS differential outputs require 100 Ω termination
resistors at the receiving device or display.
Bypass capacitors must be placed near the power supply pins. At a minimum, three 4.7 μF capacitors, one
placed at each power supply pin, are required for local device bypassing. If additional bypass capacitors are
used, place the smaller value components closer to the pin. Ferrite beads are required on the two supplies
(VDD33 and VDDIO) for effective noise suppression. Connect pins VDD33_A and VDD33_B directly to ensure ESD
performance. The interface to the display is FPD-Link LVDS. The VDDIO pin may be connected to 3.3 V or 1.8
V. Place a delay capacitor (>10 µF) and pullup resistor (10 kΩ) on the PDB signal to delay the enabling of the
device until power is stable.
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Typical Application (continued)
DS90UB928Q-Q1
3.3V / 1.8V
VDDIO
3.3V
VDD33_A
C6
FB1
FB2
C4
CAPLV25
VDD33_B
C7
C5
CAPLV12
CAPL12
C11
C8
CAPP12
C9
CAPR12
C12
C10
CAPI2S
C13
PASS
LOCK
C1
Serial
FPD-Link III
Interface
RIN+
RINC2
CMF
C3
TxCLKOUTRTERM
TxCLKOUT+
TxOUT3-
RTERM
TxOUT3+
TxOUT2CMLOUTP
CMLOUTN
RTERM
TxOUT2+
FPD-Link
Interface
TxOUT1OEN
OSS_SEL
BISTEN
TxOUT0-
MAPSEL
TxOUT0+
LFMODE
RTERM
VDD33
RPU
VDD33 or VDDIO=3.3V±0.3V
R5
INTB_IN
PDB
C14
IDx
SCL
SDA
VDD33
RPU
LVCMOS
Control
Interface
RTERM
TxOUT1+
R1
R2
VDD33
I2S / GPIO
Interface
4
GPIO[1:0]
MCLK
I2S_CLK
I2S_WC
I2S_Dx
R3
MODE_SEL
RESx
DAP (GND)
R4
NOTE:
FB1-FB2 (Optional): Impedance = 1kQ,
Low DC resistance (<1Q)
C1-C3 = 0.1 µF (50 WV; C1, C2: 0402; C3: 0603)
C4-C13 = 4.7 µF
C14 = > 10 µF
R1 and R2 (see IDx Resistor Value Table)
R3 and R4 (see MODE_SEL Resistor Value Table)
R5 = 10kQ
RPU = 4.7kQ
RTERM = 100Q
Figure 41. Typical Connection Diagram
56
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Typical Application (continued)
FPD-Link
(OpenLDI)
FPD-Link
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Style Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
RxIN3+/-
TxOUT2+/-
DOUT+
RxIN1+/RxIN0+/-
RIN+
DOUT-
RxCLKIN+/-
DS90UB927Q
Serializer
PDB
I2S AUDIO
(Surround)
TxOUT3+/-
FPD-Link III
1 Pair/AC Coupled
RxIN2+/-
6
SCL
SDA
IDx
TxOUT1+/TxOUT0+/-
RIN100Q STP Cable
CMF
CMF
OEN
OSS_SEL
PDB
MAPSEL
MAPSEL
LFMODE
LFMODE
REPEAT
REPEAT
BISTEN
BACKWD
MODE_SEL
DS90UB928Q
Deserializer
LVDS Display
720p or
Graphic
Processor
TxCLKOUT+/-
6
LOCK
PASS
I2S AUDIO
(Surround)
MCLK
SCL
SDA
IDx
Figure 42. Typical Display System Diagram
9.2.1 Design Requirements
For the typical design application, use the following as input parameters:
Table 9. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDDIO
1.8 V or 3.3 V
VDD33
3.3 V
AC Coupling Capacitor for RIN±
100 nF
PCLK Frequency
78 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Transmission Media
The DS90UB927Q-Q1 and DS90UB928Q-Q1 chipset is intended to be used in a point-to-point configuration
through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize
impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer must
have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the
quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical
environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, and so forth.) and the
application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye opening width (EW) and eye opening height (EH). A differential probe should be used to
measure across the termination resistor of 100 Ω between the CMLOUTP and CMLOUTN pins.
9.2.2.2 Display Application
The DS90UB928Q-Q1, in conjunction with the DS90UB925Q-Q1 or DS90UB927Q-Q1, is intended for interfacing
with a host (graphics processor) and a display supporting 24-bit color depth (RGB888) and high-definition (720p)
digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz together with three
control bits (VS, HS, and DE) and four I2S audio streams.
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9.2.3 Application Curves
Input to Serializer
Output at Deserializer
Figure 43. 78-MHz Clock at Serializer and Deserializer
Figure 44. CMLOUT of Deserializer from 48 MHz Input
Clock
9.3 AV Mute Prevention
The DS90UB928Q-Q1 may inadvertently enter the AV MUTE state if the serializer sends video data during
blanking period (DE = L) with a specific data pattern (24’h666666). Once the device enters the AV MUTE state,
the device mutes both audio and video outputs resulting in a black display screen. Setting the gate DE Register
0x04[4] on the serializer will prevent video signals from being sent during the blanking interval. This will ensure
AV MUTE mode is not entered during normal operation.
If unexpected AV MUTE state is seen, it is recommended to verify checking the data path control setting of the
paired Serializer. This setting is not accessible from DS90UB928Q-Q1.
9.4 OEN Toggling Limitation
EON should be enabled LVDS outputs after PDB turns to high state and the internal circuit is stabled. Since OEN
function is asynchronous signal to the internal digital blocks, repeated by OEN toggling may result in horizontal
pixel shift at the LVDS output. TO avoid this, recommend to reset by programming Register 0x01[0] for digital
blocks after OEN turn to ON state.
10 Power Supply Recommendations
10.1 Power Up Requirements and PDB Pin
When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before
the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs
(VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not
controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs
have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or
VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.
A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.
All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.
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Power Up Requirements and PDB Pin (continued)
t0
VDDIO
GND
t3
VDD33
GND
t1
VDD33
VPDB_HIGH
PDB(*)
VPDB_LOW
t4
GND
(*)
It is recommended to assert PDB (active High) with a microcontroller rather than an RC filter
network to help ensure proper sequencing of PDB pin after settling of power supplies.
Figure 45. Power Sequence
Table 10. Power-Up Sequencing Constraints
Symbol
Description
Test Conditions
VDDIO
VDDIO voltage range
VDD33
VDD33 voltage range
VPDB_LOW
PDB LOW threshold
Note: VPDB must not exceed
limit for respective I/O voltage
before 90% voltage of VDD33
VPDB_HIGH
PDB HIGH threshold
VDDIO = 3.3V ± 10%
t0
VDDIO rise time
These time constants are specified for
rise time of power supply voltage ramp
(10% - 90%)
t3
VDD33 rise time
t1
t4
VDDIO = 3.3V ± 10%
Min
Max
Units
3.0
Typ
3.6
V
1.71
1.89
V
3.0
3.6
V
0.8
V
2.0
V
0.05
1.5
ms
These time constants are specified for
rise time of power supply voltage ramp
(10% - 90%)
0.05
1.5
ms
VDD33 delay time
VIL of rising edge (VDDIO ) to VIL of
rising edge (VDD33)
The power supplies may be ramped
simultaneously. If sequenced, VDDIO
must be first.
0
Startup time
The part is powered up after the startup
time has elapsed from the moment PDB
goes HIGH. Local I2C is available to
read/write DS90Ux928Q-Q1 registers
after this time.
ms
1
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11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide
low-noise power to the device. Good layout practice also separates high frequency or high-level inputs and
outputs to minimize unwanted stray noise, feedback, and interference. Power system performance may be
greatly improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement utilizes
the plane capacitance for the PCB power system and has low inductance, which has proven effectiveness
especially at high frequencies, and makes the value and placement of external bypass capacitors less critical.
External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use
values in the range of 0.01 μF to 10 μF. Tantalum capacitors may be in the 2.2 μF to 10 μF range. The voltage
rating of the capacitors must be at least 5X the power supply voltage being used.
TI recommends LCC surface mount capacitors due to their smaller parasitic properties. When using multiple
capacitors per supply pin, locate the smaller value closer to the pin. TI recommends a large bulk capacitor at the
point of power entry, which smooths low frequency switching noise. Connect power and ground pins directly to
the power and ground planes with bypass capacitors connected to the plane with via on both ends of the
capacitor. Connecting power or ground pins to an external bypass capacitor increases the inductance of the
path. TI recommends a small body size X7R chip capacitor, such as 0603 or 0805, for external bypass. Because
a small body sized capacitor has less inductance. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 MHz to 30 MHz. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Put in xref to Pin Functions table typically provide guidance on which circuit blocks are connected to
which power pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits
such as PLLs. This device requires only one common ground plane to connect all device related ground pins.
Use at least a four layer board with a power and ground planes. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ω
are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise
will appear as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.
At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device
ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB
ground plane. More information on the WQFN package, including PCB design and manufacturing requirements,
is provided in AN-1187 Leadless Leadframe Package (LLP) SNOA401.
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
Table 11. No Pullback WQFN Stencil Aperture Summary
DEVICE
DS90UB928QQ1
PIN
COUNT
MKT Dwg
PCB I/O
Pad Size
(mm)
PCB
PITCH
(mm)
PCB DAP
SIZE (mm)
STENCIL I/O
APERTURE
(mm)
STENCIL DAP
Aperture (mm)
NUMBER of
DAP
APERTURE
OPENINGS
48
RHS0048A
0.25 x 0.4
0.5
5.1 x 5.1
0.25 x 0.6
5.1 x 5.1
1
Figure 46 shows the PCB layout example derived from the layout design of the DS90UB928QEVM evaluation
board. The graphic and layout description are used to determine both proper routing and proper solder
techniques when designing the Serializer board.
60
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11.1.1 CML Interconnect Guidelines
See Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines SNLA008 and
Application Note 905 Transmission Line RAPIDESIGNER Operation and Applications Guide SNLA035 for
full details.
• Use 100 Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– – S = space between the pair
– – 2S = space between pairs
– – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual (SNLA187).
11.2 Layout Example
Length-Matched
OpenLDI Traces
High-Speed Traces
AC Capacitors
Figure 46. DS90UB928Q-Q1 Deserializer Example Layout
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Layout Example (continued)
Figure 47. 48-Pin WQFN Stencil Example of Via and Opening Placement
62
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SNLS417C – MARCH 2013 – REVISED JULY 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines, SNLA008
• AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide, SNLA035
• AN-1187 Leadless Leadframe Package (LLP), SNOA401
• LVDS Owner’s Manual, SNLA187
• AN-2173 I2C Communication Over FPD-Link III with Bidirectional Control Channel, SNLA131
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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63
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90UB928QSQ/NOPB
ACTIVE
WQFN
RHS
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB928QSQ
DS90UB928QSQE/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB928QSQ
DS90UB928QSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB928QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DS90UB928QSQ/NOPB
WQFN
RHS
48
DS90UB928QSQE/NOPB
WQFN
RHS
DS90UB928QSQX/NOPB
WQFN
RHS
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UB928QSQ/NOPB
WQFN
RHS
48
1000
367.0
367.0
38.0
DS90UB928QSQE/NOPB
WQFN
RHS
48
250
210.0
185.0
35.0
DS90UB928QSQX/NOPB
WQFN
RHS
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHS0048A
WQFN - 0.8 mm max height
SCALE 1.800
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
A
B
PIN 1 INDEX AREA
0.5
0.3
7.15
6.85
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
(0.2)
5.1 0.1
(A) TYP
24
13
44X 0.5
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
12
25
EXPOSED
THERMAL PAD
2X
5.5
49
SYMM
SEE TERMINAL
DETAIL
1
PIN 1 ID
(OPTIONAL)
36
48
37
SYMM
48X
0.5
0.3
48X
0.30
0.18
0.1
0.05
C A B
4214990/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 5.1)
SYMM
37
48
48X (0.6)
1
36
48X (0.25)
(1.05) TYP
44X (0.5)
(1.25) TYP
49
SYMM
(6.8)
(R0.05)
TYP
( 0.2) TYP
VIA
25
12
13
24
(1.25)
TYP
(1.05)
TYP
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214990/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.625) TYP
(1.25)
TYP
37
48
48X (0.6)
1
36
49
48X (0.25)
44X (0.5)
(1.25)
TYP
(0.625) TYP
SYMM
(6.8)
(R0.05) TYP
METAL
TYP
25
12
13
16X
( 1.05)
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4214990/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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