Texas Instruments | TPD3S716-Q1 Automotive USB 2.0 Interface Protection with Adjustable Current Limit and Short-to-Battery, Short-Circuit Protection (Rev. C) | Datasheet | Texas Instruments TPD3S716-Q1 Automotive USB 2.0 Interface Protection with Adjustable Current Limit and Short-to-Battery, Short-Circuit Protection (Rev. C) Datasheet

Texas Instruments TPD3S716-Q1 Automotive USB 2.0 Interface Protection with Adjustable Current Limit and Short-to-Battery, Short-Circuit Protection (Rev. C) Datasheet
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TPD3S716-Q1
SLVSDH9C – MARCH 2016 – REVISED JUNE 2016
TPD3S716-Q1 Automotive USB 2.0 Interface Protection with Adjustable Current Limit and
Short-to-Battery, Short-Circuit Protection
1 Features
3 Description
•
The TPD3S716-Q1 is a single-chip solution for shortto-battery, short-circuit, and ESD protection with an
adjustable current-limit for the USB connector’s VBUS
and data lines in automotive applications. The
integrated data switches provide best-in-class
bandwidth for minimal signal degradation while
simultaneously providing 18 V short-to-battery
protection. The high bandwidth of 1 GHz allows for
USB2.0 high-speed data rates for applications like
Car Play. Extra margin in bandwidth above 720-MHz
also helps to maintain a clean USB 2.0 eye diagram
with the long captive cables that are common in the
automotive USB environment. The short-to-battery
protection isolates the internal system circuits from
any over-voltage conditions at the VBUS_CON, VD+,
and VD– pins. On these pins, the TPD3S716-Q1 can
handle over-voltage protection up to 18 V for hot plug
and DC events. The over-voltage protection circuit
provides the most reliable short-to-battery isolation in
the industry, shutting off the data switches in 200 ns
and protecting the upstream circuitry from harmful
voltage and current spikes.
1
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified (Grade 1)
– Operating Temperature Range: –40°C to
+125°C
Short-to-Battery (up to 18 V) and Short-to-Ground
Protection on VBUS_CON
Short-to-Battery (up to 18 V) and Short-to-VBUS
Protection on VD+, VD–
IEC 61000-4-2 ESD Protection on VBUS_CON,
VD+, VD–
– ±8-kV Contact Discharge
– ±15-kV Air Gap Discharge
ISO 10605 330-pF, 330-Ω ESD Protection on
VBUS_CON, VD+, VD–
– ±8-kV Contact Discharge
– ±15-kV Air Gap Discharge
Low RON nFET VBUS Switch (63 mΩ typical)
High Speed Data Switches (1-GHz, 3-dB
Bandwidth)
Adjustable Hiccup Current Limit up to 2.4 A
Fast Over-voltage Response Time
– 2-µs typical (VBUS switch)
– 200-ns typical (Data switches)
Independent VBUS and Data enable pins for
configuring both Host and Client/OTG mode
Fault Output Signal
Thermal Shutdown Feature
Flow-through layout in 16-Pin SSOP Package
(4.9 mm x 3.9 mm)
The VBUS_CON pin also provides an adjustable current
limited load switch and handles short-to-ground
protection. The device supports VBUS currents up to
2.4 A, allowing support for charging USB BC1.2, USB
Type-C 5V/1.5A, and proprietary charging schemes
up to 2.4 A. The separate enable pins for data and
VBUS allow for both host and client-OTG mode.
TPD3S716-Q1 also integrates system level IEC
61000-4-2 and ISO 10605 ESD protection on its
VBUS_CON, VD+, and VD– pins removing the need to
provide external high voltage, low capacitance
diodes.
Device Information(1)
2 Applications
•
•
End Equipment
– Head Units
– Rear Seat Entertainment
– Telematics
– USB Hubs
– Navigation Modules
– Media Interface
Interfaces
– USB 2.0
PART NUMBER
PACKAGE
TPD3S716-Q1
BODY SIZE (NOM)
SSOP (16)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
5V
TPD3S716-Q1
VBUS_CON
VBUS
1 µF
100 V
X7R
D±
VBUS_SYS
10 NŸ
100 µF
7V
FLT
VDt
USB
Transceiver
Dt
10 nH
D+
USB2.0
CMC
10 nH
VD+
D+
GND
VEN
From Processor
DEN
From Processor
GND
IADJ
RADJ
VIN
3.3 V
1 µF
7V
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD3S716-Q1
SLVSDH9C – MARCH 2016 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
4
5
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings—AEC Specification .............................
ESD Ratings—IEC Specification ..............................
ESD Ratings—ISO Specification ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Characteristics...............................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
10 Power Supply Recommendations ..................... 23
10.1 VBUS Path.............................................................. 23
10.2 VIN Pin................................................................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
11.3 Layout Optimized for Thermal Performance ......... 24
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
Changes from Revision B (April 2016) to Revision C
Page
•
Changed Adjustable Hiccup Current Limit from 1.7 A to 2.4 A in the Features section ........................................................ 1
•
Updated Description section................................................................................................................................................... 1
•
Changed Current through VBUS switch from 1.7 A to 2.4 A .................................................................................................... 5
•
Updated the RADJ minimum resistance to 57 kΩ in Recommended Operating Conditions table ........................................... 5
•
aDDED new current limit values to Electrical Characteristics table ...................................................................................... 6
•
Updated Figure 21 ............................................................................................................................................................... 14
•
Updated IVBUS Operating Maximum in Figure 28 to go up to 2.4 A ...................................................................................... 21
Changes from Revision A (April 2016) to Revision B
•
Made changes to the Electrical Characteristics table............................................................................................................. 1
Changes from Original (March 2016) to Revision A
•
2
Page
Page
Changed device status from Product Preview to Production Data ....................................................................................... 1
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Product Folder Links: TPD3S716-Q1
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SLVSDH9C – MARCH 2016 – REVISED JUNE 2016
5 Pin Configuration and Functions
DBQ Package
16-Pin SSOP
Top View
NC
1
16
IADJ
VBUS_CON
2
15
VBUS_SYS
VBUS_CON
3
14
VBUS_SYS
GND
4
13
GND
VD±
5
12
D±
VD+
6
11
D+
VEN
7
10
FLT
DEN
8
9
VIN
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
NC
NC
2
VBUS_CON
O
No connect, leave floating or connect to ground. Do not connect to VBUS_CON
3
VBUS_CON
O
4
GND
Ground
5
VD–
I/O
Connect to USB connector D–; provides IEC 61000-4-2 ESD protection
6
VD+
I/O
Connect to USB connector D+; provides IEC 61000-4-2 ESD protection
7
VEN
I
Enable Active-Low Input. Drive VEN low to enable the VBUS path of the device. Drive VEN high to
disable the VBUS path of the device
8
DEN
I
Enable Active-Low Input. Drive DEN low to enable the data path of the device. Drive DEN high to
disable the data path of the device
Connect to USB connector VBUS; provides IEC 61000-4-2 ESD protection
Connect to PCB ground plane
9
VIN
I
Connect to 3.3-V I/O. Controls the OVP threshold for VD+/VD–
10
FLT
O
Open-Drain fault pin. See the Detailed Description section for operation
11
D+
I/O
Connect to the internal transceiver D+ pin
12
D–
I/O
Connect to the internal transceiver D– pin
13
GND
Ground
14
VBUS_SYS
I
15
VBUS_SYS
I
16
IADJ
I
Connect to PCB ground plane
Connect to internal VBUS plane
Connect to a resistor to GND to adjust the current limit threshold
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
VBUS_CON
Supply voltage from USB connector
–0.3
18
V
VBUS_SYS
Internal Supply DC voltage Rail on the PCB
–0.3
6
V
VD+, VD–
Voltage range from connector-side USB data lines
–0.3
18
V
D+, D–
Voltage range for internal USB data lines
–0.3
VIN + 0.3
V
VIN
Voltage range for VIN supply input
–0.3
4
V
7
V
7
V
DEN
Voltage on enable pins
VEN
IBUS
Maximum DC output current on VBUS_CON pin
VIADJ
Voltage range for IADJ pin
VFLT
Voltage range for the FLT pin
TA
Operating free air temperature
TSTG
Storage temperature
(1)
(2)
(3)
(3)
(3)
2.4
A
–0.3
VVBUS_SYS +
0.3
V
–0.3
7
V
–40
125
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
Thermal limits and power dissipation limits must be observed.
6.2 ESD Ratings—AEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
±4000
Charged-device model (CDM), per AEC Q100-011
UNIT
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
IEC 61000-4-2, VBUS_CON,
VD+, VD– pins
Contact discharge (1)
±8000
Air-gap discharge (1)
±15000
UNIT
V
See Figure 20 for details on system level ESD testing setup.
6.4 ESD Ratings—ISO Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
ISO 10605 (330 pF, 330 Ω),
VBUS_CON, VD+, VD– pins
Contact discharge (1)
±8000
Air-gap discharge (1)
±15000
UNIT
V
See Figure 20 for details on system level ESD testing setup.
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VBUS_CON
Supply voltage from USB connector
VBUS_SYS
Internal supply DC voltage Rail on the PCB
VD+, VD–
Voltage range from connector-side USB data lines
D+, D–
VIN
4
NOM
MAX
UNIT
5.9
V
4.75
5.9
V
0
VIN + 0.3
V
Voltage range for internal USB data lines
0
VIN + 0.3
V
Voltage range for VIN supply
3
3.6
V
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SLVSDH9C – MARCH 2016 – REVISED JUNE 2016
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
(1)
UNIT
IBUS
Current through VBUS switch
VEN, DEN
Voltage range for enable
CSYS
Input capacitance (2)
VBUS_SYS pin
CLOAD
Output load capacitance (2)
VBUS_CON pin
1
CVIN
VIN capacitance (2)
VIN pin
1
µF
RADJ
Resistance of RADJ resistor (2)
IADJ pin
57
kΩ
(1)
(2)
2.4
0
A
5.9
V
100
µF
µF
Depending on your IBUS current level, maximum operating junction temperature derating may be required. For IBUS > 1.5A, care should
be taken in the PCB design to improve the board's thermal coefficient. Please see both the Power Dissipation and Junction Temperature
and Layout Optimized for Thermal Performance sections for more details.
See the Figure 22 for configuration details.
6.6 Thermal Information
TPD3S716-Q1
THERMAL METRIC (1)
DBQ (SSOP)
UNIT
16 PINS
θJA
Junction-to-ambient thermal resistance
98.8
°C/W
θJCtop
Junction-to-case (top) thermal resistance
48.0
°C/W
θJB
Junction-to-board thermal resistance
41.6
°C/W
ψJT
Junction-to-top characterization parameter
8.5
°C/W
ψJB
Junction-to-board characterization parameter
41.2
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
°C/W
θJA(Custom)
See the Layout Optimized for Thermal Performance section
57.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics
over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON =
float (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT CONSUMPTION
IVBUS_SLEEP
VBUS Sleep current consumption
Measured at VBUS_SYS pin, VEN = 5 V, DEN = 5 V
IVBUS
VBUS Operating current consumption
Measured at VBUS_SYS pin
45
150
µA
285
380
µA
IVIN
Leakage current for VIN
Measured at VIN pin, VIN = 3.6 V
ION(LEAK)
Leakage into VBUS_SYS while shorted to
battery and powered on
Measured flowing into VBUS_SYS pin, VBUS_SYS = 5
V, VBUS_CON = 18 V
12
20
µA
225
300
µA
IOFF(LEAK)
Leakage through VBUS path while
shorted to battery and unpowered
Measured flowing out of VBUS_SYS pin, VBUS_SYS = 0
V, VBUS_CON = 18 V
50
µA
ID(OFF_LEAK)
Leakage out of data path while shorted
to battery and unpowered
Measured flowing out of D+ or D– pins, VBUS_SYS =
0 V, VD+ or VD– = 18 V, VIN = 0 V, D+/D– = 0 V
–1
1
µA
ID(ON_LEAK)
Leakage out of data path while shorted
to battery and powered on
Measured flowing out of D+ or D– pins, VBUS_SYS =
5 V, VD+ or VD– = 18 V, VIN = 3.3 V, D+/D– = 0 V
–1
1
µA
IVD(OFF_LEAK)
Leakage into data path while shorted to
battery and unpowered
Measured flowing in to VD+ or VD– pins, VBUS_SYS
= 0 V, VD+ or VD– = 18 V, VIN = 0 V, D+/D– = 0 V
85
µA
IVD(ON_LEAK)
Leakage into data path while shorted to
battery and powered on
Measured flowing in to VD+ or VD– pins, VBUS_SYS
= 5 V, VD+ or VD– = 18 V, VIN = 3.3 V D+/D– = 0
V
85
µA
Undervoltage lockout
rising for VIN
Ramp VIN up until VBUS and Data FETs turn on,
VEN =0 V, DEN = 0 V
2.6
2.7
2.9
Ramp VIN down until VBUS and Data FETs turn off,
VEN =0 V, DEN = 0 V
2.5
2.6
2.8
VIN PIN
VUVLO(RISING)
VUVLO(FALLING)
Undervoltage lockout
falling for VIN
VIN
V
VEN, DEN, FLT PINS
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Electrical Characteristics (continued)
over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON =
float (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.2
TYP
MAX
UNIT
VIH
High-level input voltage
VEN, DEN
Set VEN (DEN)= 0 V; Sweep VEN (DEN) to 1.4 V;
Measure when VBUS (Data) FET turns off
VIL
Low-level input voltage
VEN, DEN
Set VEN (DEN) = 3.3 V; Sweep VEN (DEN) from
3.3 V to 0.5 V; Measure when VBUS (Data) FET
turns on
0.8
V
IIL
Input Leakage Current
VEN, DEN
V(VEN) (V(DEN))= 3.3 V ; Measure Current into VEN
(DEN) pin
1
µA
VOL
Low-level output
voltage
FLT
IOL = 3 mA
0.4
V
ILIM
Overcurrent limit, RADJ
= 280 kΩ ± 1%
VBUS
Progressively load VBUS_CON until device asserts
FLT
505
620
mA
ILIM
Overcurrent limit, RADJ
= 158 kΩ ± 1%
VBUS
Progressively load VBUS_CON until device asserts
FLT
0.905
1.1
A
ILIM
Overcurrent limit, RADJ
= 143 kΩ ± 1%
VBUS
Progressively load VBUS_CON until device asserts
FLT
1.005
1.2
A
ILIM
Overcurrent limit, RADJ
= 93.1 kΩ ± 1%
VBUS
Progressively load VBUS_CON until device asserts
FLT
1.505
1.8
A
ILIM
Overcurrent limit, RADJ
= 76.8 kΩ ± 1%
VBUS
Progressively load VBUS_CON until device asserts
FLT
1.8
2.16
A
ILIM
Overcurrent limit, RADJ
= 66.5 kΩ ± 1%
VBUS
Progressively load VBUS_CON until device asserts
FLT
2.105
2.57
A
ILIM
Overcurrent limit, RADJ
= 57.6 kΩ ± 1%
VBUS
Progressively load VBUS_CON until device asserts
FLT
2.405
2.93
A
ILIM
Overcurrent limit, IADJ =
GND
VBUS
Progressively load VBUS_CON until device asserts
FLT
550
700
850
mA
ILIM
Overcurrent limit, IADJ =
VBUS_SYS
VBUS
Progressively load VBUS_CON until device asserts
FLT
1.1
1.4
1.7
A
V
OCP CIRCUIT—VBUS
OVER TEMPERATURE PROTECTION
TSD(RISING)
The rising over-temperature protection
shutdown threshold
VBUS_SYS = 5 V, VEN = 0 V, DEN = 0 V, No Load
on VBUS_CON, TA stepped up until FLT is asserted
150
165
180
℃
TSD(FALLING)
The falling over-temperature protection
shutdown threshold
VBUS_SYS = 5 V, VEN = 0 V, DEN = 0 V, No Load
on VBUS_CON, TA stepped down from TSD(RISING)
until FLT is deasserted
125
130
142
℃
TSD(HYST)
The over-temperature protection
shutdown threshold hysteresis
TSD(RISING) – TSD(FALLING)
10
35
55
℃
VOVP(RISING)
Input overvoltage
protection threshold
VBUS_CON
Increase VBUS_CON from 5 V to 7 V. Measure when
FLT is asserted
5.6
5.8
6
V
VHYS(OVP)
Hysteresis on OVP
VBUS_CON
Difference between rising and falling OVP
thresholds on VBUS_CON
VOVP(FALLING)
Input overvoltage
protection threshold
VBUS_CON
Decrease VBUS_CON from 7 V to 5 V. Measure
when FLT is deasserted
5.52
5.75
5.98
V
VREV_SUPPLY(RISING)
Reverse supply
detection threshold
VBUS_CON –
VBUS_SYS
Set VBUS_SYS to 5 V. Increase VBUS_CON from
VBUS_SYS to VBUS_SYS + 300 mV. Measure the value
of VBUS_CON – VBUS_SYS when FLT asserts.
25°C ≤ TA ≤ 125°C
140
200
260
mV
VREV_SUPPLY(FALLING)
Reverse supply
detection threshold
VBUS_CON –
VBUS_SYS
Set VBUS_SYS to 5 V. Decrease VBUS_CON from
VBUS_SYS + 300 mV to VBUS_SYS. Measure the value
of VBUS_CON – VBUS_SYS when FLT deasserts.
25°C ≤ TA ≤ 125°C
70
120
165
mV
VREV_SUPPLY(HYST)
Hysteresis on reverse
supply detection
VBUS_CON –
VBUS_SYS
Difference between rising and falling reverse
supply detection thresholds
VUVLO(SYS_RISING)
Undervoltage lockout
rising for VBUS_SYS
VBUS_SYS
VBUS_SYS voltage rising from 0 V to 5 V
3.1
3.3
3.6
V
VHYS(UVLO_SYS)
VBUS_SYS UVLO
Hysteresis
VBUS_SYS
Difference between rising and falling UVLO
thresholds on VBUS_SYS
50
75
100
mV
VUVLO(SYS_FALLING)
Undervoltage lockout
falling for VBUS_SYS
VBUS_SYS
VBUS_SYS voltage falling from 5 V to 2.9 V
3
3.2
3.5
V
OVP CIRCUIT—VBUS
6
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50
mV
80
mV
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Electrical Characteristics (continued)
over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON =
float (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
VBUS_CON
Increase VBUS_CON voltage from 0 V until the
device transitions from the short-circuit to overcurrent mode of operation
2.5
2.6
2.7
V
Short-to-ground
comparator falling
threshold
VBUS_CON
Set VBUS_SYS = 5 V; VIN = 3.3 V; VEN = 0 V, DEN =
0 V; Decrease VBUS_CON voltage from 5 V until the
device transitions from the over-current to shortcircuit mode of operation
2.4
2.5
2.6
V
VSHRT(HYST)
Short-to-ground
comparator hysteresis
VBUS_CON
Difference between VSHRT(RISING) and VSHRT(FALLING)
ISHRT
Short-to-ground current
source
VBUS_CON
Current sourced from VBUS_SYS when device is in
short-circuit mode
VSHRT(RISING)
Short-to-ground
comparator rising
threshold
VSHRT(FALLING)
TEST CONDITIONS
125
150
UNIT
mV
350
mA
OVP CIRCUIT—VD+/VD–
VOVP(RISING)
Input overvoltage
protection threshold
VD+/VD–
Increase VD+ or VD– (with D+ and D–) from 3.3 V
to 4.5 V. Measure the value at which FLT is
asserted
VHYS(OVP)
Hysteresis on OVP
VD+/VD–
Difference between rising and falling OVP
thresholds on VD+/VD–
VOVP(FALLING)
Input overvoltage
protection threshold
VD+/VD–
Decrease VD+ or VD– (with D+ or D–) from 4.5 V
to 2 V. Measure the value at FLT is deasserted
V(VBUS_STB)
VBUS hotplug short-tobattery tolerance
VBUS_CON
V(DATA_STB)
Data line hotplug shortto-battery tolerance
VD+/VD–
VIN + 0.6
VIN +
0.8
VIN + 1
50
VIN +
0.525
VIN +
0.75
V
mV
VIN +
0.975
V
18
V
18
V
SHORT TO BATTERY
Charge battery-equivalent capacitor to test voltage
then discharge to pin under test through a 1 meter,
18 gauge wire. (See Figure 19 for more details)
DATA LINE SWITCHES—VD+ to D+ or VD– to D–
CON
Equivalent On Capacitance
Capacitance of D+/D– switches when enabled –
measure on connector side at VDx = 0.4 V
6.9
RON
On Resistance
Measure resistance between D+ and VD+ or D–
and VD–, voltage between 0 V and 0.4 V
4
6.5
Ω
RON(Flat)
On Resistance flatness
Measure resistance between D+ and VD+ or D–
and VD–, sweep voltage between 0 V and 0.4 V
0.2
1
Ω
BWON
On Bandwidth (–3dB)
Measure S21 bandwidth from D+ to VD+ or D– to
VD– with voltage swing = 400 mVpp, VCM= 0.2 V
910
MHz
BWON_DIFF
On Bandwidth (–3dB)
Measure SDD21 bandwidth from D+ to VD+ and D–
to VD– with voltage swing = 800 mVpp differential,
VCM= 0.2 V
1050
MHz
Xtalk
Crosstalk
Measure S21 bandwidth from D+ to VD– or D– to
VD+ with voltage swing = 400 mVpp. Make sure to
terminate open sides to 50 ohms. f = 480 MHz
–28
dB
R(DISCHARGE)
Output discharge resistance
VEN = 5 V, DEN = 5 V, Set VBUS_CON = 5 V and
measure current flow to ground
18
30
kΩ
RON
VBUS path ON resistance
VBUS_CON = 5 V, IOUT = 1.5 A. See Figure 29 for a
plot of the maximum VBUS RON possible at a given
junction temperature
63
135
mΩ
pF
nFET SWITCH—VBUS
6.8 Timing Characteristics
over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, D+/D– = 45 Ω to GND,
VD+/VD–/VBUS_CON = float (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE PIN
tON_HOST
Host mode enable on time
Time between VEN and DEN asserted low and VBUS and
Data FETs turn on, CVBUS_CON = 0 µF
5.7
ms
tON_CLIENT
Client mode enable on time
Time between DEN asserted low and Data FETs turn on.
VEN remains high
2.4
ms
tOFF_HOST
Host mode disable time
Time between VEN and DEN deasserted high and VBUS
and Data FETs turn off, CVBUS_CON = 0 µF
30
µs
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Timing Characteristics (continued)
over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, D+/D– = 45 Ω to GND,
VD+/VD–/VBUS_CON = float (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time between DEN deasserted high and Data FETs turn
off. VEN remains high
5
µs
tHOST_TO_CLIE Host to Client mode transition
time
NT
Time between VEN deasserted high and VBUS FET turns
off. DEN remains low, CVBUS_CON = 0 µF
70
µs
tCLIENT_TO_HO Client to Host mode transition
time
ST
Time between VEN asserted low and VBUS FET turns on.
DEN remains low, CVBUS_CON = 0 µF
3.4
ms
tOFF_CLIENT
Client mode disable time
OVER CURRENT PROTECTION
tBLANK
Overcurrent blanking time
Time from overcurrent condition until FLT assertion and
VBUS FET turn off
tRETRY
Overcurrent retry time
Time from overcurrent FET shut off until FET turns back
on
tRECV
Overcurrent recovery time
2
ms
100
ms
Time from end of tRETRY until FLT deassertion if
overcurrent condition is removed
8
ms
OVER VOLTAGE PROTECTION
tOVP_response
OVP Response time – VBUS
Measured from OVP Condition to FET turnoff
2
4
µs
tOVP_response
OVP Response time – data
switches
Measured from OVP Condition to FET turnoff
200
ns
tOVP_FLT_ASSE
OVP FLT assertion time
Measured from an OVP Condition to FLT assertion
14
µs
RT
SHORT TO GROUND PROTECTION
Time from short condition until current falls below 120%
of ISHRT, CVBUS_CON = 0 µF
tSHRT
Short to ground response time
tSHRT_FLTZ
Short to ground FLT assertion Time from short condition until FLT is asserted,
time
CVBUS_CON = 0 µF
2
4
20
µs
µs
REVERSE SUPPLY DETECTION
tREV_SUPPLY_
Reverse supply blanking time
Time from reverse current condition until FLT assertion
2
ms
BLANK
8
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6.9 Typical Characteristics
140
80
120
60
100
40
20
60
Voltage (V)
Voltage (V)
80
40
20
0
0
-20
-40
-20
-60
-40
VDD-
-60
-80
-10
0
10
20
30
40 50 60
Time (ns)
70
80
90 100 110
0
10
20
D001
Figure 1. 8-kV IEC Contact Waveform
1
8
0.75
7
0.5
6
0.25
5
0
-0.25
-0.5
40 50 60
Time (ns)
70
80
90 100 110
D002
VBUS_CON
/VEN
/FLT
4
3
2
-0.75
1
VD+
VD-
-1
-5
0
5
10
Voltage (V)
15
20
0
-15
25
-10
D003
Figure 3. Data Line I-V Curve
-5
Time (ms)
0
5
D004
D003
Figure 4. VBUS tON Time
100
6
5
80
4
60
RON (:)
Leakage Current (PA)
30
Figure 2. –8-kV IEC Contact Waveform
Voltage (V)
Current (mA)
VDD-
-80
-100
-10
40
3
2
20
-40 C
25 C
85 C
130 C
1
Unpowered
Powered, Enabled
0
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
0.1
D007
Figure 5. VD± Leakage Current at 18-V across Temperature
0.2
Bias Voltage (V)
0.3
0.4
D008
Figure 6. Data Switch RON vs Bias Voltage
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1000
4
800
3
600
2
400
1
200
Voltage (V)
0
-4.8 -4.4
-3.6 -3.2 -2.8 -2.4
Time (ms)
-2
4
1000
3
750
2
500
1
250
0
-40
0
-4
5
1500
VBUS_CON
IVBUS_CON
1250
/FLT
-1.6 -1.2 -0.8
6.5
Voltage (V) or Current (A) on VBUS_CON
Voltage (V) or Current (A)
7.5
5.5
4.5
3.5
2.5
1.5
0.5
-0.5
-1.5
100
120
-3
2
7
12
Time (Ps)
17
22
27
30
140
0
160
D010
12.5
VBUS_CON
IVBUS_CON 10
VBUS_SYS
/FLT
7.5
40
30
20
5
10
2.5
0
0
-10
-2.5
-20
-10
0
10
20
30
Time (Ps)
D011
Figure 9. VBUS Short-to-Ground Response Waveform
-5
40
D012
Figure 10. VBUS Short-to-18 V Response Waveform
25
12.5
VDIVDD/FLT
8.5
20
Voltage (V) or Current (A)
10.5
Voltage (V) or Current (A)
40
60
80
Time (ms)
50
VBUS_CON
IVBUS_CON
VBUS_SYS
/FLT
8.5
6.5
4.5
2.5
VDIVDD/FLT
15
10
5
0
0.5
-0.25
0.25
Time (Ps)
0.75
-5
-0.5
0
0.5
Time (Ps)
D014
Figure 11. Data Switch Short-to-5 V Response Waveform
10
20
Figure 8. Overcurrent tBLANK_RETRY Response Waveform
9.5
-1.5
-0.75
0
D009
Figure 7. Overcurrent tBLANK Response Waveform
-2.5
-8
-20
Voltage (V) on VBUS_SYS and /FLT
5
7
6
Voltage (V)
6
1600
VBUS_CON
IVBUS_CON 1400
/FLT
1200
Current (mA)
8
Current (mA)
Typical Characteristics (continued)
1
D005
Figure 12. Data Switch Short-to-18 V Response Waveform
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Typical Characteristics (continued)
24
19
7.5
14
5
9
2.5
4
0
-1
-1
0
-10
-20
Crosstalk (dB)
12.5
VDIVD10
D/FLT
Voltage (V) on D- and FLT
Voltage (V) or Current (A) on VD-
29
9
Time (Ps)
14
-40
-50
-60
-70
D- to VD+
D+ to VD-
-80
-2.5
4
-30
0
19
1E+9
2E+9
Frequency (Hz)
D013
Figure 13. Data Switch Short-to-18 V Response Waveform
(Long)
3E+9
D017
Figure 14. Data Switch Crosstalk
Figure 15. USB2.0 Eye Diagram (no TPD3S716-Q1)
Figure 16. USB2.0 Eye Diagram (with TPD3S716-Q1)
0
0
-3
Insertion Loss (dB)
Instertion Loss (dB)
-1
-2
-3
-4
-6
-9
-5
-6
1E+7
1E+8
Frequency (Hz)
1E+9
3E+9
-12
1E+7
D015
Figure 17. Data Switch Differential Bandwidth
1E+8
Frequency (Hz)
1E+9
3E+9
D016
Figure 18. Data Switch Single-Ended Bandwidth
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7 Parameter Measurement Information
5V
VBUS_SYS
VBUS_CON
STB Strike Points
1 µF
100 V
X7R
FLT
VD±
D±
VD+
D+
GND
VEN
10 nH
USB2.0
CMC
45 Ÿ
10 nH
45 Ÿ
1-m Cable
DC Power
Supply
100 µF
7V
10 NŸ
From GPIO
DEN
STB
Strike
Output
From GPIO
IADJ
RADJ
22 mF
35 V
TPD3S716-Q1
VIN
3.3 V
1 µF
7V
STB Test Aparatus
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Short-to-Battery System Test Setup
5V
VBUS_CON
VBUS_SYS
ESD Strike Points
1 µF
100 V
X7R
10 NŸ
100 µF
7V
FLT
VD±
D±
VD+
D+
GND
VEN
10 nH
USB2.0
CMC
45 Ÿ
10 nH
45 Ÿ
From GPIO
DEN
From GPIO
IADJ
RADJ
TPD3S716-Q1
VIN
3.3 V
1 µF
7V
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Figure 20. ESD System Test Setup
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8 Detailed Description
8.1 Overview
The TPD3S716-Q1 provides a single-chip ESD protection and over voltage protection solution for automotive
USB interfaces. It offers short to battery protection up to 18 V and short to ground protection on VBUS_CON. The
TPD3S716-Q1 also provides a FLT pin that indicates to the system if a fault condition has occurred. The
TPD3S716-Q1 offers ESD clamps on the VBUS_CON, VD+, and VD– pins, therefore eliminating the need for
external TVS clamp circuits in the application.
The TPD3S716-Q1 has internal circuitry that controls the turnon of the internal nFET switches. An internal
oscillator controls the timers that enable the switches and resets the open-drain FLT output. If VBUS_CON and
VD+/VD– are less than VOVP, the switches are enabled. After an internal delay the charge-pump starts-up and
turns on the internal nFET switches through a soft start. At any time, if any of the external USB pins rise above
their respective VOVP thresholds, the nFET switches are turned OFF and the FLT pin is pulled LOW.
8.2 Functional Block Diagram
VBUS_CON
VBUS_SYS
Short to
Ground
Detection
ESD
Clamp
Undervoltage
Lockout
+
Overcurrent
Detection
Overvoltage
Protection
IADJ
RADJ
VEN
FLT
Control Logic
DEN
VIN
VD+
D+
ESD
Clamps
VD±
D±
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8.3 Feature Description
8.3.1 AEC-Q100 Qualified
The TPD3S716-Q1 is an automotive qualified device according to the AEC-Q100 standards. The TPD3S716-Q1
is qualified to operate from –40 to +125°C ambient temperature.
8.3.2 Short-to-Battery and Short-to-Ground Protection on VBUS_CON
The VBUS_CON pin is protected against shorts to battery and shorts to ground.
If a voltage on VBUS_CON is detected as too low (below the VSHRT threshold) after the device is enabled, the
device enters short-circuit protection mode and asserts FLT. It sources the ISHRT current until it detects the
voltage rising above the VSHRT threshold, where it resumes standard operating mode and deasserts FLT.
If a voltage above the VOVP threshold is detected by the device, it shuts off all FETs and assert a fault on the FLT
pin. When the excessive voltage is removed, the device automatically re-enables and FLT deasserts.
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Feature Description (continued)
8.3.3 Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
The VD+ and VD– pins are protected against shorts to battery and shorts to bus. The OVP threshold on the VD+
and VD– pins is low enough that it protects against shorts to VBUS.
When a voltage above the VOVP threshold is detected by the device, it shuts off all FETs and asserts a fault on
the FLT pin. When the excessive voltage is removed, the device automatically re-enables and FLT deasserts.
8.3.4 ESD Protection on VBUS_CON, VD+, VD–
The protected pins (VBUS_CON, VD+, VD–) are tested to pass the IEC 61000-4-2 ESD standard up to Level 4 ESD
protection. Additionally, these pins are tested against ISO 10605 with the 330-pF, 330- Ω equivalent network.
This guarantees passing of at least ±8-kV contact discharge and ±15-kV air gap discharge according to both
standards. See Figure 20 for the test set-up used for testing IEC 61000-4-2 and ISO 10605.
8.3.5 Low RON nFET VBUS Switch
The VBUS switch has a low RON that provides minimal voltage droop from system to connector. Typical resistance
is 63 mΩ and is specified for 135 mΩ at 150°C junction temperature.
8.3.6 High Speed Data Switches
The D+ and D– switches have a very low capacitance and a high bandwidth (1-GHz typical), allowing for a clean
USB 2.0 eye diagram.
8.3.7 Adjustable Hiccup Current Limit up to 2.4-A
The VBUS path of this device has an integrated overcurrent protection circuit. The current limit threshold for the
overcurrent protection is adjustable via an external resistor RADJ to GND on the IADJ pin. Equation 1 to Equation 3
approximate the minimum, nominal, and maximum current limit values for TPD3S716-Q1 assuming a 1% tolerant
resistor:
ILIM (A)
ILIM(TYP) = 143 × RADJ(–0.983)
ILIM(MIN) = 129 × RADJ(–0.981) – 0.02
ILIM(MAX) = 141.5 × RADJ(–0.962) + 0.015
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
50
(1)
(2)
(3)
ILIM(MIN)
ILIM(TYP)
ILIM(MAX)
70
90 110 130 150 170 190 210 230 250 270
RADJ (k:)
D009
Figure 21. TPD3S716-Q1 Current Limit Thresholds vs. RADJ
Equation 1, Equation 2 and Equation 3 are useful for approximating the current limit threshold of TPD3S716-Q1;
however, they do not constitute as part of TI's published device specifications for purposes of TI's product
warranty. For the officially tested current limit threshold values, see the Electrical Characteristics table.
When the VBUS current exceeds the overcurrent threshold, the device goes into a fault state where it limits the
current to the overcurrent threshold value and asserts the FLT pin. After a short blanking time, the device cycles
on and off to try to check if the connected device is still in overcurrent.
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Feature Description (continued)
8.3.8 Fast Over-Voltage Response Time
The over-voltage FETs are designed to have a fast turnoff time to protect the upstream SoC as quickly as
possible. Typical response time for complete turnoff is 2 µs for the VBUS path and 200 ns for the data path.
8.3.9 Independent VBUS and Data Enable Pins for Configuring both Host and Client/OTG Mode
The TPD3S716-Q1 has two enable inputs to turn on and off the device's internal FETs. The VEN pin disables
and enables the VBUS path. The DEN pin disables and enables the data path. Independent control of the VBUS
and data paths enables the TPD3S716-Q1 to be configured for both USB Host and Client/OTG mode. See
Table 1.
8.3.10 Fault Output Signal
The TPD3S716-Q1 has a fault pin ,FLT that indicates when there is any sort of fault condition because of an
OVP, OCP, short-circuit, reverse-current, or thermal shutdown event occurring.
8.3.11 Thermal Shutdown Feature
In the event that the device exceeds the maximum allowable junction temperature, the thermal shutdown circuit
disables the VBUS and data switches and assert the fault pin low.
8.3.12 16-Pin SSOP Package
The TPD3S716-Q1 is packaged in a standard 16-pin SSOP leaded package.
8.3.13 Reverse Current Detection
If VBUS_CON exceeds VBUS_SYS by a voltage greater than VREV_SUPPLY(RISING) for tREV_SUPPLY_BLANK, then TPD3S716Q1 detects this reverse current condition and asserts the fault pin. When VBUS_CON – VBUS_SYS falls below
VREV_SUPPLY(FALLING), the fault pin is be deasserted and TPD3S716-Q1 enters back into its normal operating
mode.
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8.4 Device Functional Modes
8.4.1 Normal Operation
The TPD3S716-Q1 operates in normal operation modes when enabled, both VBUS_SYS and VIN are above their
UVLO thresholds, and the device is not in any fault conditions. Table 1 shows the normal operating modes of the
TPD3S716-Q1.
Table 1. Device Normal Operating Mode Table
MODE
VEN
DEN
VBUS PATH
USB Host
0
0
ON
DATA PATH
ON
Power Only
0
1
ON
OFF
USB Client/OTG
1
0
OFF
ON
Disabled
1
1
OFF
OFF
8.4.2 Overvoltage Condition
When the VD+, VD–, or VBUS_CON pins exceed their OVP threshold, the device enters the overvoltage state. All
FETs are disabled and the FLT pin is asserted. When the protected pins drop below their OVP threshold, the
device automatically turns back on and deasserts the FLT pin. An overvoltage condition is only detected on an
enabled path. For example, if the data path is enabled and the VBUS path is disabled (USB Client/OTG mode), if
an overvoltage condition occurs on VBUS_CON, the fault pin is not be asserted. However, because the FETs of
disabled paths are already turned off, proper protection from overvoltage conditions are still guaranteed by the
device on disabled paths.
8.4.3 Overcurrent Condition
When the current through the VBUS path exceeds the ILIM current threshold, the device enters into the overcurrent
state. The TPD3S716-Q1 limits current to the ILIM threshold by dropping voltage across the VBUS FET to maintain
constant current. When it continues to sense an overcurrent condition for the blanking time (tBLANK), the device
disables itself for the retry time (tRETRY) and then retry automatically for the retry time (tBLANK_RETRY). In the event
that the current is below the overcurrent threshold, the device deasserts fault and resumes normal operation.
8.4.4 Short-Circuit Condition
If the voltage on the VBUS_CON side is pulled below the VSHRT threshold while the device is enabled, the
TPD3S716-Q1 enters the short-circuit mode. It sources a constant current of ISHRT until it rises above the VSHRT
threshold. When that occurs, the device automatically re-enters normal operation and deasserts the fault pin.
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8.4.5 Device Logic Table
Table 2 shows the TPD3S716-Q1 logic table.
Table 2. TPD3S716-Q1 Logic Table
Mode
VEN
DEN
VBUS_CON
VDx
IVBUS
VBUS_SYS
,
VIN
TJ
FLT
VBUS PATH
DATA PATH
Unpowered
X
X
X
X
None
< UVLO
X
H
OFF
OFF
Disabled
H
H
X
X
None
> UVLO
< TSD
H
OFF
OFF
< OVP & <
VBUS_SYS +
200 mV(typical) &
> VSHRT
< OVP
< OCP
> UVLO
< TSD
H
ON
ON
Host
L
L
Client/OTG
H
L
X
< OVP
None
> UVLO
< TSD
H
OFF
ON
X
< OCP
> UVLO
< TSD
H
ON
OFF
Power Only
L
H
< OVP & <
VBUS_SYS +
200 mV(typical) &
> VSHRT
Thermal
Shutdown
X
X
X
X
None
> UVLO
> TSD
L
OFF
OFF
Host: VBUS
OVP Fault
L
L
> OVP
X
None
> UVLO
< TSD
L
OFF
OFF
Host: Data
OVP Fault
L
L
X
> OVP
None
> UVLO
< TSD
L
OFF
OFF
Host: OCP
Fault
L
L
< OVP & <
VBUS_SYS +
200 mV(typical) &
> VSHRT
X
> OCP
> UVLO
< TSD
L
CURRENT
LIMITED, AUTORETRY
AUTO-RETRY
Host: ShortCircuit Fault
L
L
< VSHRT
X
X
> UVLO
< TSD
L
CURRENT LIMITED
250 mA (typical)
OFF
Host: RCP
Fault
L
L
< OVP & >
VBUS_SYS +
200 mV (typical)
X
X
> UVLO
< TSD
L
ON
ON
OTG: Data
OVP Fault
H
L
X
> OVP
None
> UVLO
< TSD
L
OFF
OFF
Power Only:
VBUS OVP
Fault
L
H
> OVP
X
None
> UVLO
< TSD
L
OFF
OFF
Power Only:
OCP Fault
L
H
X
X
> OCP
> UVLO
< TSD
L
CURRENT
LIMITED, AUTORETRY
OFF
Power Only:
ShortCircuit Fault
L
H
< VSHRT
X
X
> UVLO
< TSD
L
CURRENT LIMITED
250 mA (typical)
OFF
Power Only:
RCP Fault
L
H
< OVP & >
VBUS_SYS +
200 mV (typical)
X
X
> UVLO
< TSD
L
ON
OFF
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD3S716-Q1 offers fully featured automotive USB2.0 protection including short-to-battery, overcurrent, and
ESD protection. Care must be taken during the implementation to make sure the device provides adequate
protection to the system.
9.2 Typical Application
Figure 22 shows a fully featured USB2.0 high speed port, with an 18-V short-to-battery requirement on the
connector side.
5V
TPD3S716-Q1
VBUS_CON
VBUS
1 µF
100 V
X7R
D±
VBUS_SYS
100 µF
7V
10 NŸ
FLT
USB
Transceiver
VDt
Dt
VD+
D+
GND
VEN
From Processor
DEN
From Processor
10 nH
D+
10 nH
USB2.0
CMC
GND
IADJ
RADJ
VIN
3.3 V
1 µF
7V
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Typical Application Configuration for TPD3S716-Q1
9.2.1 Design Requirements
Table 3 shows the TPD3S716-Q1 input parameters for this application example.
Table 3. Design Parameters
18
DESIGN PARAMETER
EXAMPLE VALUE
Short-to-battery tolerance on VD+, VD–, VBUS_CON
18 V
Max current in normal operation on VBUS
1.5 A
Current Limit Setting on VBUS
1.505 A (minimum)
Maximum Ambient Temperature Requirement
105°C
USB Data Rate
480 Mbps
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9.2.2 Detailed Design Procedure
The following parameters must be known to the designer to begin the design process:
• Short-to-battery tolerance on connector pins
• Maximum current in normal operation on VBUS
• Maximum operating ambient temperature
• USB Data Rate
9.2.2.1 Short-to-Battery Tolerance
The TPD3S716-Q1 is capable of handling up to 18 V DC on the VD+, VD–, and VBUS_CON pins. In the event of a
short-to-battery on VBUS_CON, significant ringing would be expected because of the hot plug-like nature of the
short-to-battery event. In typical ceramic capacitor configurations, a standard RLC response is expected which
results in a ringing of nearly two times the applied DC voltage. The TPD3S716-Q1 is capable of withstanding the
transient ringing from hot plug-like events, assuming some precautions are taken.
Careful capacitor selection on the VBUS_CON pin must be observed. A capacitor with a low derating percentage
under the applied voltages must be used to prevent excess ringing. In the example, a 1-µF, 100-V tolerant
ceramic X7R capacitor is used. It is best practice to carefully select the capacitors used in this circuit to prevent
derating-based voltage spikes under hot plug events. See Figure 25 and Figure 26 to compare ringing of a 50-V
capacitor to a 100-V capacitor. Figure 27 shows the 100-V capacitor with the TPD3S716-Q1 installed.
Another alternative to a high rated ceramic capacitor is to implement either a standard R-C snubber circuit, or a
small external TVS diode. Depending on the short-to-battery tolerance needed, no special precautions may be
needed.
9.2.2.2 Maximum Current on VBUS
The TPD3S716-Q1 is capable of operating up to 2.4 A maximum DC current. In this example, the maximum
current for USB2.0 BC1.2 of 1.5 A has been chosen.
9.2.2.3 Power Dissipation and Junction Temperature
This section demonstrates how to analyze the power dissipation and junction temperature of the TPD3S716-Q1
to validate that the application requirements of an IVBUS operating current level of 1.5 A and a maximum
operating ambient temperature of 105 °C can be met.
It is good design practice to estimate power dissipation and maximum expected junction temperature of
TPD3S716-Q1. This is important to insure the device does not go into thermal shutdown in normal operation and
that the long term reliability of the device is maintained. Using Equation 4 to Equation 6, the system designer can
control choices of the device's proximity to other power dissipating devices and the design of the printed circuit
board (PCB). These have a direct influence on maximum junction temperature. Other factors, such as airflow and
maximum ambient temperature, are often determined by system considerations. It is important to remember that
these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical.
For TPD3S716-Q1, the operating junction temperature must be kept below 150°C in order to prevent the device
from going into thermal shutdown. Equation 4 is used to calculate the junction temperature of the device:
TJ = TA + [(IOUT2 × RON) × RθJA]
where
•
•
•
•
•
IOUT = Rated OUT pin current (A)
RON = Power path on-resistance at an assumed TJ (Ω)
TA = Maximum ambient temperature (°C)
TJ = Maximum junction temperature (°C)
RθJA = Thermal resistance (°C/W)
(4)
This application example requires an IVBUS operating current level of 1.5 A. TPD3S716-Q1 has maximum junction
temperature derating requirements depending on the maximum operating current of the device according to
Equation 5:
TJ(MAX) = –15.6 × (IVBUS(MAX OPERATING)) + 161.5 (°C)
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where
•
•
TJ(MAX) = Maximum allowed junction temperature (°C)
IVBUS(MAX OPERATING) = Maximum IVBUS operating current (A)
(5)
See Figure 28 for a plot of the reliability curve equation. Using this equation, 138.1°C is the maximum allowed
junction temperature in this application.
This example requires a maximum operating ambient temperature of 105°C. To determine if this can be
supported using Equation 4, the maximum VBUS path RON must be determined. Equation 6 calculates the
maximum VBUS path RON possible for TPD3S716-Q1 for a given junction temperature:
RON(MAX) = (TJ + 183.15) / 2726.7 (Ω)
where
•
•
RON(MAX) = Maximum VBUS RON at a given junction temperature (Ω)
TJ = Device junction temperature (°C)
(6)
See Figure 29 for a plot of the maximum VBUS path RON vs. Junction Temperature curve. Using the above
equation, the maximum VBUS RON possible for TPD3S716-Q1 at 138.1°C is RON(MAX) = 0.118 Ω.
Using the calculated parameters for this example and the standard datasheet RθJA for TPD3S716-Q1, the
maximum operating ambient temperature possible in this example is TA = 111°C. Because this is greater than
the application requirement of 105°C, TPD3S716-Q1 can safely be operated at 1.5 A with RθJA = 98.8 (°C/W). If
the resulting ambient temperature in the above calculations resulted in a TA < 105 °C, methods for improving
RθJA would need to be taken. See the Layout Optimized for Thermal Performance section for guidelines on
improving RθJA for TPD3S716-Q1. The example given in the Layout Optimized for Thermal Performance yields
an RθJA = 57 (°C/W). Excellent thermal performance of TPD3S716-Q1 can be achieved with the proper PCB
layout.
9.2.2.4 USB Data Rate
The TPD3S716-Q1 is capable of operating at the maximum USB2.0 High Speed data rate of 480-Mbps because
of the high data switch bandwidth of 1-GHz (typical). In this design example the maximum data rate of 480-Mbps
has been chosen.
20
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9.2.3 Application Curves
Figure 23. USB2.0 Eye Diagram
(Board only, Through Path)
Figure 24. USB2.0 Eye Diagram
(System from Typical Application Schematic)
40
60
Voltage
Current
40
30
20
10
0
20
10
0
-10
-10
-20
-10
0
10
20
30
40
Time (Ps)
50
60
-20
-10
70
10
20
30
40
Time (Ps)
50
60
70
D018
Figure 26. 100-V, 1-µF X7R Ceramic Shorted to 18 V
165
35
Maximum Junction Temperature (qC)
Voltage
Current
30
Voltage (V) or Current (A)
0
D018
Figure 25. 50-V, 1-µF X7R Ceramic Shorted to 18-V (Not
Recommended)
25
20
15
10
5
0
-5
-10
-15
-20
Voltage
Current
30
Voltage (V) or Current (A)
Voltage (V) or Current (A)
50
160
155
150
145
140
135
130
125
120
-10
0
10
20
30
40
Time (Ps)
50
60
70
80
0
D018
Figure 27. TPD3S716-Q1 and 100-V, 1-µF X7R Shorted to
18 V (Powered Off)
0.4
0.8
1.2
1.6
IVBUS Operating Maximum (A)
2
2.4
D006
Figure 28. TPD3S716-Q1 IVBUS Temperature Derating Curve
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130
VBUS RON (m:) Maximum
120
110
100
90
80
70
60
50
40
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D006
Figure 29. TPD3S716-Q1 Maximum VBUS RON vs. Junction Temperature
22
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10 Power Supply Recommendations
10.1 VBUS Path
The VBUS_SYS pins provide power to the chip and supply current through the load switch to VBUS_CON. A 100-µF
bulk capacitor is recommended on VBUS_SYS to supply the USB port and maintain compliance. A 1-µF capacitor is
recommended on the VBUS_CON pin with adequate voltage rating to tolerate short-to-battery conditions. A supply
voltage above the UVLO threshold for VBUS_SYS must be supplied for the device to power on.
10.2 VIN Pin
The VIN pin provides a voltage reference for the data switch OVP level as well as a bypass for ESD clamping. A
1-µF capacitor must be placed as close to the pin as possible and the supply must be set to be above the UVLO
threshold for VIN.
11 Layout
11.1 Layout Guidelines
Proper routing and placement maintains signal integrity for high-speed signals. The following guidelines apply to
the TPD3S716-Q1:
• Place the bypass capacitors as close as possible to the VIN, VBUS_SYS, and VBUS_CON pins. Capacitors must be
attached to a solid ground. This minimizes voltage disturbances during transient events such as short-tobattery, ESD, or overcurrent conditions.
• High speed traces (data switch path) must be routed as straight as possible and any sharp bends must be
minimized.
Standard ESD recommendations apply to the VD+, VD–, and VBUS_CON pins as well:
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
Figure 30 shows a full layout for a standard USB2.0 port. A common mode choke and inductors are used on the
high speed data lines, and the requisite bypassing caps are placed on VBUS_CON, VBUS_SYS, and VIN.
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Layout Example (continued)
VBUS
IADJ
N.C.
D-
VBUS_CON
VBUS_SYS
VBUS_CON
VBUS_SYS
GND
GND
TPD3S716-Q1
D+
Legend
GND
USB2.0 Connector
VD-
D-
To Transceiver
VD+
D+
To Transceiver
To Processor
VEN
FLT
To Transceiver
To Processor
DEN
VIN
Pin to GND
VIA to 3.3V Plane
VIA to 5V Plane
VIA to GND Plane
Figure 30. Typical Layout Example for TPD3S716-Q1
11.3 Layout Optimized for Thermal Performance
Figure 31 and Figure 32 show images from a real PCB design optimized for the best thermal performance for
TPD3S716-Q1. This PCB layout has 6 layers (2 signal and 4 plane layers). The 2 signal layers are the outer
layers of the PCB and constructed with 2-oz copper, and the 4 internal plane layers are constructed with 1-oz
copper. Using this PCB layout yielded an RθJA(CUSTOM) = 57 (°C/W). The images contain rough dimensions of the
copper traces and pours used around the device. One key strategy to optimize thermal performance of the
device is to maximize the area of the copper pours and traces used to route the device power, GND, and signal
pins when possible. Another key strategy is to maximize the copper weight of the PCB metal layers. This
example demonstrates that excellent thermal performance can be achieved with TPD3S716-Q1 with the proper
PCB layout.
24
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Layout Optimized for Thermal Performance (continued)
Figure 31. Thermally Optimized PCB Layout Top Layer
Figure 32. Thermally Optimized PCB Layout Bottom Layer
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TPD3S716-Q1 Evaluation Module, SLVUAL9
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPD3S716QDBQRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SSOP
DBQ
16
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
RJ716Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2016
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPD3S716QDBQRQ1
Package Package Pins
Type Drawing
SSOP
DBQ
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD3S716QDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
.150-.157
[3.81-3.98]
NOTE 4
16X .008-.012
[0.21-0.30]
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 -8
.016-.035
[0.41-0.88]
(.041 )
[1.04]
DETAIL A
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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