Texas Instruments | SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver (Rev. D) | Datasheet | Texas Instruments SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver (Rev. D) Datasheet

Texas Instruments SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver (Rev. D) Datasheet
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SN65LVDS302
SLLS733D – JUNE 2006 – REVISED MAY 2016
SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver
1 Features
2 Applications
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1
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Serial Interface Technology
Compatible With FlatLink™3G such as
SN65LVDS301
Supports Video Interfaces up to 24-bit RGB Data
and 3 Control Bits Received over 1, 2 or 3
SubLVDS Differential Lines
SubLVDS Differential Voltage Levels
Up to 1.755-Gbps Data Throughput
Three Operating Modes to Conserve Power
– Active mode QVGA: 17 mW
– Typical Shutdown: 0.7 μW
– Typical Standby Mode: 27 μW Typical
Bus-Swap Function for PCB-Layout Flexibility
ESD Rating > 4 kV (HBM)
Pixel Clock Range of 4 MHz to 65 MHz
Failsafe on all CMOS Inputs
Packaged in 5-mm × 5-mm MicroStar Junior
μBGA® With 0.5-mm Ball Pitch
Very low EMI meets SAE J1752/3 'Kh'-spec
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Small Low-Emission Interface between Graphics
Controller and LCD Display
Cameras, Camcorders, Embedded Computers
Portable Multimedia Players
3 Description
The
SN65LVDS302
receiver
de-serializes
FlatLink™3G compliant serial input data to 27 parallel
data outputs. The SN65LVDS302 receiver contains
one shift register to load 30 bits from 1, 2 or 3 serial
inputs and latches the 24 pixel bits and 3 control bits
out to the parallel CMOS outputs after checking the
parity bit. If the parity check confirms correct parity,
the Channel Parity Error (CPE) output remains low. If
a parity error is detected, the CPE output generates a
high pulse while the data output bus disregards the
newly-received pixel. Instead, the last data word is
held on the output bus for another clock cycle.
Device Information(1)
PART NUMBER
PACKAGE
BGA MICROSTAR
JUNIOR (80)
SN65LVDS302
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Implementation Example
D
LC
Application
Processor
with CMOS
Video Interface
4
S31
LVD or 2
30
DS
LV
LVDS301
or
LVDS311
A
DAT
CLK
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65LVDS302
SLLS733D – JUNE 2006 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Input Electrical Characteristics.................................. 9
Output Electrical Characteristics............................... 9
Timing Requirements .............................................. 10
Switching Characteristics ........................................ 10
Device Power Dissipation ..................................... 11
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 16
7.1 Power Consumption Tests...................................... 20
7.2 Typical IC Power Consumption Test Pattern.......... 21
7.3 Maximum Power Consumption Test Pattern .......... 22
7.4 Output Skew Pulse Position and Jitter
Performance............................................................. 22
8
Detailed Description ............................................ 25
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
25
26
27
28
Application and Implementation ........................ 32
9.1 Application Information............................................ 32
9.2 Typical Applications ................................................ 36
10 Power Supply Recommendations ..................... 39
11 Layout................................................................... 39
11.1 Layout Guidelines ................................................. 39
11.2 Layout Example .................................................... 40
12 Device and Documentation Support ................. 41
12.1
12.2
12.3
12.4
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
41
13 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2012) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
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SLLS733D – JUNE 2006 – REVISED MAY 2016
5 Pin Configuration and Functions
ZQE Package
80-Pin BGA MICROSTAR JUNIOR
Top View
1
2
3
4
5
6
7
8
9
A
GND
R6/B1
R4/B3
R2/B5
R0/B7
G6/G1
G4/G3
G2/G5
GND
B
R7/B0
R5/B2
R3/B4
R1/B6
G7/G0
G5/G2
G3/G4
G1/G6
G0/G7
C
LS0
V
GND
B7/R0
B6/R1
D
D2+
LS1
B5/R2
B4/R3
E
D2–
GND
B3/R4
B2/R5
F
D1+
V
B1/R6
B0/R7
G
D1–
GND
F/S
PCLK
H
CPOL
GND
VS
HS
RXEN
DE
CPE
J
GND
LVDS
V
V
DD
PLLD
DDPLLD
LVDS
DDLVDS
V
GND
V
DD
GND
GND
GND
GND
V
GND
GND
GND
GND
V
GND
GND
GND
GND
V
GND
GND
GND
GND
V
DDPLLA
SWAP
DD
CLK+
GND
PLLA
CLK–
V
DDLVDS
D0+
GND
LVDS
D0–
DD
DD
DD
DD
Pin Functions
PIN
NAME
NO.
DESCRIPTION
I/O
CMOS
See
(1)
CMOS Out
Blue pixel data
G0 to G7
See
(1)
CMOS Out
Green pixel data
R0 to R7
See
(1)
CMOS Out
Red pixel data
B0 to B7
Channel parity error
CPE
J9
CMOS Out
This output indicates the detection of a parity error by generating an output high-pulse
for half of a PCLK clock cycle; this allows counting parity errors with a simple counter.
0: no error
high-pulse: bit error detected
(1)
Pin assignment depends on SWAP pin setting. Swappable pins are detailed in Table 1.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
H1
CMOS In
DESCRIPTION
Output clock polarity selection:
CPOL
0: rising edge clocking
1: falling edge clocking
DE
J8
CMOS Out
F/S
G8
CMOS In
Data Enable
CMOS bus rise time select:
1: fast output rise time
0: slow output rise time
HS
H9
LS0
C1
LS1
D2
PCLK
G9
CMOS Out
CMOS In
CMOS Out
Horizontal sync
Link select: determines active SubLVDS Data Links and PLL Range) (see Table 11)
Output Pixel Clock; rising or falling clock polarity is selected by control input CPOL
Disables the CMOS Drivers and turns off the PLL, putting device in shutdown mode. (2)
RXEN
J7
CMOS In
1: Receiver enabled
0: Receiver disabled (shutdown)
SWAP
J2
CMOS In
Bus swap: swaps the bus pins to allow device placement on top or bottom of PCB.
See pinout drawing and Table 1 for pin assignments.
0: data output from R7 to B0
1: data output from B0 to R7
VS
H8
CMOS Out
Vertical sync
CLK+,
CLK–
J3, J4
SubLVDS In
SubLVDS input pixel clock (polarity is fixed)
D0+, D0–
J5, J6
SubLVDS In
SubLVDS data link (active during normal operation)
D1+, D1–
F1, G1
SubLVDS In
SubLVDS data link (active during normal operation when LS0 = high and LS1 = low,
or LS0 = low and LS1 = high; high impedance if LS0 = LS1 = low); input can be left
open if unused.
D2+, D2–
D1, E1
SubLVDS In
SubLVDS data link (active during normal operation when LS0 = low and LS1 = high,
high-impedance when LS1 = low); input can be left open if unused.
C2, C4, C6,
D7 to G7
Power Supply
Supply voltage
VDDLVDS
H2, H5
Power Supply
SubLVDS I/O supply voltage
VDDPLLA
H3
Power Supply
PLL analog supply voltage
VDDPLLD
F2
Power Supply
PLL digital supply voltage
A1, A9, C5, C7,
D3 to D6, E3 to E6,
F3 to F6,
G3 to G6, H7
Ground
Supply ground
GNDLVDS
G2, H6, J1
Ground
SubLVDS ground
GNDPLLA
H4
Ground
PLL analog ground
GNDPLLD
E2
Ground
PLL digital ground
SUBLVDS
POWER SUPPLY
VDD
GND
(2)
4
RXEN input incorporates glitch suppression logic to avoid unwanted switching. The input must be pulled low for longer than 10 µs
continuously to force the receiver to enter Shutdown. The input must be pulled high for at least 10 μs continuously to activate the
receiver. An input pulse shorter than 5 µs is interpreted as glitch and becomes ignored. At power up, the receiver is enabled
immediately if RXEN = H and disabled if RXEN = L.
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Table 1. Swappable Pins
SIGNAL
B0
B1
B2
B3
B4
B5
B6
B7
(1)
SWAP
(1)
PIN
L
F9
H
B1
L
F8
H
A2
L
E9
H
B2
L
E8
H
A3
L
D9
H
B3
L
D8
H
A4
L
C9
H
B4
L
C8
H
A5
SIGNAL
G0
G1
G2
G3
G4
G5
G6
G7
SWAP (1)
PIN
L
B9
H
B5
L
B8
H
A6
L
A8
H
B6
L
B7
H
A7
L
A7
H
B7
L
B6
H
A8
L
A6
H
B8
L
B5
H
B9
SIGNAL
R0
R1
R2
R3
R4
R5
R6
R7
SWAP (1)
PIN
L
A5
H
C8
L
B4
H
C9
L
A4
H
D8
L
B3
H
D9
L
A3
H
E8
L
B2
H
E9
L
A2
H
F8
L
B1
H
F9
The SWAP pin is either set to GND (L) or VDD (H).
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
Voltage range at any input or output terminal
MIN
MAX
UNIT
VDD (2), VDDPLLA, VDDPLLD, VDDLVDS
–0.3
2.175
V
When VDDx > 0 V
–0.5
2.175
When VDDx ≤ 0 V
–0.5
VDD + 2.175
Ouput current, IO
±5
Storage temperature, Tstg
–55
(1)
(2)
V
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
Machine model
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
see
(1)
MIN NOM
MAX
UNIT
1.65
1.95
V
VDD
VDDPLLA
VDDPLLD
Supply voltages
1.8
VDDLVDS
Test set-up see Figure 21
VDDn(PP)
Supply voltage noise magnitude
50 MHz (all supplies)
TA
Operating free-air temperature
fCLK ≤ 50 MHz; f(noise) = 1 Hz to 2 GHz
100
fCLK > 50 MHz; f(noise) = 1 Hz to 1 MHz
100
fCLK > 50 MHz; f(noise) > 1 MHz
mV
40
–40
85
1-Channel receive mode, see Figure 35
4
15
2-Channel receive mode, see Figure 36
8
30
3-Channel receive mode, see Figure 37
20
65
35%
65%
°C
CLK+ and CLK–
fCLK±
Input Pixel clock frequency
Standby mode (2), see Figure 30
tDUTCLK
(1)
(2)
6
CLK Input Duty Cycle
500
MHz
kHz
Unused single-ended inputs must be held high or low to prevent them from floating.
PCLK input frequencies lower than 500 kHz forces the SN65LVDS302 into standby mode. Input frequencies from 500 kHz to 3 MHz
may or may not activate the SN65LVDS302. Input frequencies beyond 3 MHz activate the SN65LVDS302. TI recommends against input
frequencies from 500 kHz to 4 MHz, which can cause PLL malfunction.
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Recommended Operating Conditions (continued)
see (1)
MIN NOM
MAX
UNIT
mV
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
|VD0+ – VD0–|, |VD1+ – VD1–|, |VD2+ – VD2–|,
|VCLK+ – VCLK–| during normal operation
70
200
Receive or Acquire mode
0.6
1.2
|VID|
Magnitude of differential input voltage
VICM
Input voltage common mode range
ΔVICM
VICM(n) – VICM(m) with
Input voltage common mode variation
n = {D0, D1, D2, or CLK} and
between all SubLVDS inputs
m = {D0, D1, D2, or CLK}
–100
100
ΔVID
VID(n) – VID(m) with
Differential input voltage amplitude
n = {D0, D1, D2, or CLK} and
variation between all SubLVDS inputs
m = {D0, D1, D2, or CLK}
–10%
10%
tR/F
Input rise and fall time
RXEN at VDD; see figure 10
Input rise or fall time mismatch
between all SubLVDS inputs
tR(n) – tR(m) and tF(n) – tF(m) with
n = {D0, D1, D2, or CLK} and
m = {D0, D1, D2, or CLK}
ΔtR/F
Stand-by mode
0.9 × VDDLVDS
–100
V
mV
800
ps
100
ps
LS0, LS1, CPOL, SWAP, RXEN, F/S
VICMOSH
High-level input voltage
0.7 × VDD
VDD
V
VICMOSL
Low-level input voltage
0
0.3 × VDD
V
tinRXEN
RXEN input pulse duration
μs
10
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE
CL
Output load capacitance
10
pF
6.4 Thermal Information
SN65LVDS302
THERMAL METRIC (1)
ZQE
(BGA MICROSTAR JUNIOR)
UNIT
80 PINS
RθJA
Junction-to-ambient thermal resistance
74
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
40.1
°C/W
Junction-to-board thermal resistance
52.3
°C/W
ψJT
Junction-to-top characterization parameter
1.7
°C/W
ψJB
Junction-to-board characterization parameter
51.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
Alternating 1010 Test pattern (see Table 6). All CMOS outputs
terminated with 10 pF, F/S and RXEN at VDD. VIH = VDD, VIL = 0 V,
VDD = VDDPLLA = VDDPLLD = VDDLVDS
1ChM
Typical power test pattern (see Table 3). VID = 70 mV. All CMOS
outputs terminated with 10 pF, F/S at GND, and RXEN at VDD.
VIH = VDD, VIL = 0 V, VDD = VDDPLLA = VDDPLLD = VDDLVDS
RMS supply
current
14
fPCLK = 6 MHz
11.7
15.9
fPCLK = 15 MHz
19.3
25
fPCLK = 4 MHz
4.7
fPCLK = 6 MHz
6
fPCLK = 15 MHz
13.2
fPCLK = 8 MHz
UNIT
mA
mA
19.4
25
33
fPCLK = 30 MHz
26.8
37
fPCLK = 8 MHz
6.4
fPCLK = 22 MHz
13.7
fPCLK = 30 MHz
18.3
Alternating 1010 Test pattern (see Table 6). All CMOS outputs
terminated with 10 pF, F/S and RXEN at VDD. VIH = VDD, VIL = 0 V,
VDD = VDDPLLA = VDDPLLD = VDDLVDS
fPCLK = 20 MHz
17.1
27
fPCLK = 65 MHz
60.8
68
Typical power test pattern (see Table 5). VID = 70 mV. All CMOS
outputs terminated with 10 pF, F/S at GND, and RXEN at VDD.
VIH = VDD, VIL = 0 V, VDD = VDDPLLA = VDDPLLD = VDDLVDS
fPCLK = 20 MHz
8.6
fPCLK = 65 MHz
22.2
Standby mode;
RXEN = VIH
15
100
μA
Shutdown mode;
RXEN = VIL
0.4
10
μA
Typical power test pattern (see Table 4). VID = 70 mV. All CMOS
outputs terminated with 10 pF, F/S at GND, and RXEN at VDD.
VIH = VDD, VIL = 0 V, VDD = VDDPLLA = VDDPLLD = VDDLVDS
3ChM
CLK and D[0:2] inputs are left open. All control inputs held static high or low.
All CMOS outputs terminated with 10 pF. VIH = VDD, VIL = 0 V,
VDD = VDDPLLA = VDDPLLD = VDDLVDS
8
9.8
14.3
2ChM
(1)
MAX
fPCLK = 4 MHz
MIN
fPCLK = 22 MHz
Alternating 1010 Test pattern (see Table 6). All CMOS outputs
terminated with 10 pF, F/S and RXEN at VDD. VIH = VDD, VIL = 0 V,
VDD = VDDPLLA = VDDPLLD = VDDLVDS
IDD
TYP (1)
TEST CONDITIONS
mA
mA
mA
mA
All typical values are at 25°C and with 1.8-V supply unless otherwise noted.
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6.6 Input Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
Vthstby
Input voltage common mode threshold to switch
between receive and acquire mode and standby
mode
RXEN at VDD
1.3
VTHL
Low-level differential input voltage threshold
VD0+ – VD0–, VD1+ – VD1–,
VD2+ – VD2–, VCLK+ – VCLK–
–40
VTHH
High-level differential input voltage threshold
VD0+ – VD0–, VD1+ – VD1–,
VD2+ – VD2–, VCLK+ – VCLK–
40
mV
II+, II–
Input leakage current
VDD = 1.95 V, VI+ = VI–,
VI = 0.4 V and VI = 1.5 V
75
μA
IIOFF
Power-off input current
VDD = GND; VI = 1.5 V
–75
μA
RID
Differential input termination resistor value
122
Ω
CIN
Input capacitance
ΔCIN
Input capacitance variation
78
Measured between input
terminal and GND
0.9 × VDDLVDS
mV
100
1
Within one signal pair
pF
0.2
Between all signals
1
RBBDC Pull-up resistor for standby detection
21
V
30
39
pF
kΩ
LS0, LS1, CPOL, SWAP, RXEN, F/S
VIK
Input clamp voltage
(2)
II = –18 mA, VDD = VDD(min)
–1.2
V
0 V ≤ VDD ≤ 1.95 V;
VI = {GND, 1.95 V}
100
nA
IICMOS
Input current
CIN
Input capacitance
IIH
High-level input current
VIN = 0.7 × VDD
–200
200
nA
IIL
Low-level input current
VIN = 0.3 × VDD
–200
200
nA
VIH
High-level input voltage
0.7 × VDD
VDD
V
VIL
Low-level input voltage
0
0.3 × VDD
V
(1)
(2)
2
pF
All typical values are at 25°C and with 1.8-V supply unless otherwise noted.
Do not leave any CMOS Input unconnected or floating to minimize leakage currents. Every input must be connected to a valid logic level
VIH or VOL while power is supplied to VDD.
6.7 Output Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8 × VDD
VDD
V
0
0.2 × VDD
V
R[0:7], G[0:7], B[0:7], VS, HS, PCLK, CPE
1-ChM, F/S = L, IOH = –250 μA
VOH
High-level output current
2- or 3-ChM, F/S = L, IOH = –500 μA
1-ChM, F/S = H, IOH = –500 μA
2- or 3-ChM, F/S = H, IOH = –2 mA
1-ChM, F/S = L, IOL = 250 μA
VOL
Low-level output current
2- or 3-ChM, F/S = L, IOL = 500 μA
1-ChM, F/S = H, IOL = 500 μA
2- or 3-ChM, F/S = H, IOL = 2 mA
IOH
High-level output current
1-ChM, F/S = L
–250
2- or 3-ChM, F/S = L; 1-ChM, F/S = H
–500
2- or 3-ChM, F/S = H
1-ChM, F/S = L
IOL
Low-level output current
2- or 3-ChM, F/S = L; 1-ChM, F/S = H
2- or 3-ChM, F/S = H
μA
–2000
250
500
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2000
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6.8 Timing Requirements
PARAMETER
tRSKMx (1) (2)
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
Receiver input skew margin (3)
(see Figure 40)
MIN
1ChM: x = 0.29, fPCLK = 15 MHz,
RXEN at VDD, VIH = VDD, VIL = GND,
RL = 100 Ω, test setup as in Figure 22,
test pattern as in Table 8
fCLK = 15 MHz (4)
2ChM: x = 0.14, fPCLK = 30 MHz,
RXEN at VDD, VIH = VDD, VIL = GND,
RL = 100 Ω, test setup as in Figure 22,
test pattern as in Table 9
fCLK = 30 MHz (4)
3ChM: RXEN at VDD, VIH = VDD, VIL = GND,
test setup as in Figure 22,
test pattern as in Table 10
fCLK = 65 MHz (4)
UNIT
630
fCLK = 4 MHz to 15 MHz (5)
1 / (60 × fCLK) – 480
630
ps
fCLK = 8 MHz to 30 MHz (5)
1 / (30 × fCLK) – 480
360
fCLK = 20 MHz to 65 MHz
(5)
1 / (20 × fCLK) – 410
Receiver Input Skew Margin (tRSKM) is the timing margin available for transmitter output pulse position (tPPOS), interconnect skew, and
interconnect inter-symbol interference. tRSKM represents the reminder of the serial bit time not taken up by the receiver strobe
uncertainty;. The tRSKM assumes a bit error rate better than 10-12.
tRSKM is indirectly proportional to the internal set-up and hold time uncertainty, ISI and duty cycle distortion from the front end receiver,
the skew mismatch from CLK to data D0, D1, and D2, as well as the PLL cycle-to-cycle jitter.
This includes the receiver internal set-up and hold time uncertainty, all PLL related high-frequency random and deterministic jitter
components that impact the jitter budget, ISI and duty cycle distortion from the front end receiver, and the skew from CLK to data D0,
D1, and D2; The pulse position minimum and maximum variation is given with a bit error rate target of 10–12; Measurements of the total
jitter are taken over a sample amount of > 10–12 samples.
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges.
These Minimum and Maximum Limits are simulated only.
6.9 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
800
ps
–100
100
ps
1-channel mode, F/S = L
8
16
2-channel mode, F/S = L
4
8
3-channel mode, F/S = L
4
8
1-channel mode, F/S = H
4
8
2-channel mode, F/S = H
1
2
3-channel mode, F/S = H
1
2
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
tR/F
Input rise and fall time
RXEN at VDD; see Figure 24
ΔtR/F
Input rise or fall time
mismatch between all
SubLVDS inputs
tR(n) – tR(m) and tF(n) – tF(m) with
n = {D0, D1, D2, or CLK} and
m = {D0, D1, D2, or CLK}
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE
Rise and fall time
20% to 80% of VDD (2)
tR/F
tOUTP
PCLK output duty cycle
Output skew from PCLK
to R[0:7], G[0:7], B0:7],
HS, VS, and DE
tOSK
(3)
CL = 10 pF
(see Figure 23)
1-channel and 3-channel mode
45%
50%
55%
CPOL = VIL, 2-channel mode
48%
53%
59%
CPOL = VIH, 2-channel mode
41%
47%
52%
see Figure 23
–500
ns
500
ps
2.5 / fPCLK
s
3.8
μs
INPUT TO OUTPUT RESPONSE TIME
tPD(L)
Propagation delay time
from CLK+ input to PCLK
output
RXEN at VDD, VIH = VDD, VIL = GND, CL = 10 pF,
see Figure 28
tGS
RXEN glitch suppression
pulse width (4)
VIH = VDD, VIL = GND, RXEN toggles from
VIL to VIH; see Figure 29 and Figure 30
(1)
(2)
(3)
(4)
10
1.4 / fPCLK
1.9 / fPCLK
All typical values are at 25°C and with 1.8-V supply unless otherwise noted.
tR/F depends on the F/S setting and the capacitive load connected to each output. Some application information of how to calculate tR/F
based on the output load and how to estimate the timing budget to interconnect to an LCD driver are provided in the application section
near the end of this data sheet.
The output rise and fall time is optimized for an output load of 10 pF. The rise and fall time can be adjusted by changing the output load
capacitance.
The RXEN input incorporates a glitch-suppression logic to disregard short input pulses. tGS is the duration of either a high-to-low or lowto-high transition that is suppressed.
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Switching Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
Enable time from power
down (↑RXEN)
Time from RXEN pulled high to data outputs
enabled and outputs valid data; see Figure 30
2
ms
tpwrdn
Disable time from active
mode (↓RXEN)
RXEN is pulled low during receive mode;
time measurement until all outputs held static:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high,
DE = PCLK = low and PLL is Shutdown;
see Figure 30
11
μs
twakeup
Enable time from Standby
(↑↓CLK)
RXEN at VDD; device is in standby; time
measurement from CLK input starts switching to
PCLK and data outputs enabled and outputting
valid data; see Figure 31
2
ms
tsleep
Disable time from active
mode (CLK transitions to
high-impedance)
RXEN at VDD; device is receiving data; time
measurement from CLK input signal stops (input
open or input common mode VICM exceeds
threshold voltage Vthstby) until all outputs held
static: R[0:7] = G[0:7] = B[0:7] = VS = HS = high,
DE = PCLK = low and PLL is Shutdown;
see Figure 31
3
μs
fBW
PLL bandwidth (5)
Tested from CLK
input to PCLK output
tpwrup
(5)
2-ChM; fPCLK = 22 MHz
0.087 × fPCLK
3-ChM; fPCLK = 65 MHz
0.075 × fPCLK
MHz
When using the SN65LVDS302 receiver in conjunction with the SN65LVDS301 transmitter in one link, the PLL bandwidth of the
SN65LVDS302 receiver always exceed the bandwidth of the SN65LVDS301 transmit PLL. This ensures stable PLL tracking under all
operating conditions and maximizes the receiver skew margin.
6.10 Device Power Dissipation
PARAMETER
PD
Device Power
Dissipation
TEST CONDITIONS
TYP
MAX
VDDx = 1.8 V, TA = 25°C,
all outputs terminated with 10 pF
fCLK = 4 MHz
16.8
fCLK = 65 MHz
64.7
VDDx = 1.95 V, TA = –40°C,
all outputs terminated with 10 pF
fCLK = 4 MHz
27.4
fCLK = 65 MHz
128.8
mW
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6.11 Typical Characteristics
Some of the plots in this section show more than one curve representing various device pin relationships. Taken together, they represent a
working range for the tested parameter.
100.0
30
2-Channel Mode, 22 MHz (VGA), F/S = 1
25
STANDBY
2-Channel Mode, 11 MHz (HVGA), F/S = 1
10.0
IDDQ - mA
IDD - mA
20
2-Channel Mode, 22 MHz (VGA), F/S = 0
15
2-Channel Mode, 11 MHz (HVGA), F/S = 0
10
1.0
POWERDOWN
5
0.1
-50
0
-50
-30
-10
10
30
Temperature - °C
50
70
90
-30
-10
10
30
50
Temperature - °C
70
90
Figure 2. Quiescent Supply Current vs Temperature
Figure 1. Supply Current vs Temperature
40
40
35
35
30
30
25
25
2 - ChM, F/S = 1, typ pwr
1 - ChM, F/S = 1, jitter test
IDD - mA
IDD - mA
2 - ChM, F/S = 1, jitter test
20
1 - ChM,
F/S = 1,
typ pwr
1 - ChM F/S = 0, jitter test
15
20
15
10
10
2 - ChM F/S = 0, jitter test
5
5
1 - ChM, F/S = 0, typ pwr
2 - ChM, F/S = 0, typ pwr
0
0
0
5
10
f - Frequency - MHz
15
0
20
5
10
15
20
25
30
f - Frequency - MHz
Figure 3. Supply Current vs Frequency, 1-Channel Mode
Figure 4. Supply Current vs Frequency, 2-Channel Mode
450
40
3 - ChM, F/S = 1, jitter test
35
Limit with RSKM=130 ps
400
3 - ChM, F/S = 1, typ pwr
350
30
FL3G Limit
300
t(RSPOS)
IDD - mA
25
20
3 - ChM F/S = 0, jitter test
15
2-ChM 22 MHz (VVGA)
200
3-ChM 65 MHz
1-ChM 11 MHz (HVGA)
100
3 - ChM, F/S = 0, typ pwr
5
50
20
25
30
40
35
45
f - Frequency - MHz
50
55
60
Figure 5. Supply Current vs Frequency, 3-Channel Mode
12
250
150
10
0
15
3-ChM 56 MHz (XGA)
0
-40
-20
0
20
40
Temperature - °C
60
80
Figure 6. Receiver Strobe Position vs Temperature
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Typical Characteristics (continued)
12.0
900
3-ChM
10.0
3-ChM
8 MHz: 9%
3-ChM
2-ChM
Spec Limits
1-Ch Mode
700
Spec Limits
3-Ch Mode
3-ChM
Spec Limit 3ChM
1-ChM
600
Spec Limits
2-Ch Mode
CC Jitter - ps
PLL Bandwidth - %
2-ChM
8.0
800
Spec Limit 2ChM
6.0
4.0
500
400
300
200
3-ChM
2.0
2-ChM
100
0.0
0.0
0
10.0
20.0
30.0
40.0
50.0
Frequency - MHz
60.0
70.0
0
Figure 7. PLL Bandwidth
10
20
30
40
50
Frequency - MHz
60
70
Figure 8. PCLK Cycle-to-Cycle Output Jitter
2000
Receiver Strobe
Position uncertainty
1500
T(PPOS )
1000
Additional interconnect margin
RSKM - ps
500
225
Minimum desired interconnect budget
0
-225-
-500
-1000
-1500
-2000
120
170
220
270
320
370
420
dR - Mbps
Bit width
Trskm
1ChM
Trskm - Tppos
225ps
Figure 9. RSKM, 1-Channel Mode vs Bit Rate
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Typical Characteristics (continued)
2000
2000
1500
Bit width
Trskm - Tppos
1000
500
1000
0
225 ps
-500
220
270
320
dR - Mbps
Trskm
Bit width
Bit width
-1500
170
225 ps
-500
-1000
Trskm
-2000
120
225 ps
0
Trskm - Tppos
Trskm - Tppos
-1000
Trskm
Trskm - Tppos
500
225 ps
Time - ps
Time - ps
1500
Bit width
Trskm
370
-1500
-2000
200
420
Figure 10. RSKM, 2-Channel Mode vs Bit Rate
250
300
350
400 450
dR - Mbps
500
550
600
650
Figure 11. RSKM, 3-Channel Mode vs Bit Rate
249
Output Voltage Amplitude - mV
400 mV/div
Output Voltage Amplitude - mV
190
0
–190
3-Channel Mode,
f(PCLK) = 56 MHz
3-Channel Mode,
f(PCLK) = 56 MHz
–251
300 ps/div
Response Over 80-inch FR-4 + 1m Coax Cable
3.5 ns/div
Response With 10-pF Load
Figure 12. XGA 3-Channel Output Waveform
Figure 13. XGA 3-Channel Output Waveform
0.0
0.0
-2.0
-10.0
-4.0
Differential S11 - dB
CMNR - dB
-6.0
-8.0
-10.0
-12.0
-14.0
-20.0
-30.0
-40.0
-16.0
-50.0
-18.0
-20.0
0
-60.0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency - MHz
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency - MHz
Figure 14. Input Common-Mode Noise Rejection vs
Frequency
14
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Figure 15. Input Return Loss
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Typical Characteristics (continued)
-50
0.0
-60
Differential Xtalk - dB
-10.0
-70
-20.0
-80
-30.0
-100
dBc/Hz
-90
-40.0
f(PCLK) = 65 MHz
-110
-120
-130
-50.0
-140
-60.0
-150
-160
-70.0
-170
-80.0
-180
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency - MHz
10
1
100
100k
10M
1M
Figure 17. Phase Noise
Figure 16. Input Differential Crosstalk vs Frequency
9.0
12
8 MHz
9%
4 MHz
9%
11
20 MHz
8.7 %
8.5
Spec Limit
1 ChM
10
PLL - Bandwidth - %
PLL BW (% of PCLK Frequency)
10k
1k
FREQUENCY - Hz
9
8
7
Spec Limit
2 ChM
Spec Limit
3 ChM
8.0
15 MHz
8.1 %
30 MHz
8.1 %
7.5
65 MHz
7.5 %
7.0
6
6.5
5
4
0
100
200
300
400
500
PLL - Frequency - MHz
600
6.0
700
0
Figure 18. SN65LVDS302 PLL Bandwidth
10
20
50
30
40
PCLK - Frequency - MHz
70
60
Figure 19. SN65LVDS301 PLL Bandwidth
30
f(PCLK)=62 MHz
RADIATED EMISSION - dBmV
25
20
15
10
5
0
0
200
400
600
800
1000
1200
1400
1600
1800
2000
FREQUENCY - MHz
Figure 20. GTEM SAE J1752/3 EMI Test
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7 Parameter Measurement Information
SN65LVDS302
2
1
Noise
Generator
100 mV
1W
VDDPLLA
VDDPLLD
VDD
10 µF
VDDLVDS
GND
Note: The generator regulates the
noise amplitude at point 1
to the
target amplitude given under the table
Recommended Operating Conditions
1.8 V
Supply
1.6 H
Figure 21. Power Supply Noise Test Set-Up
To measure t RSKM, CLK is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance
or delay is then reduced until there are no data errors observed over 10-12 serial bit times. The magnitude of the advance or delay
is tRSKM
Programmable delay
CLK and Data
Pattern
Generator
CLK
D1
DUT:
SN65LVDS302
D2
Bit error
Detector
D3
Ideal receiver strobe position
tPG_ERROR
TRSKM(p)
C
TRSKM(n)
tbit
tRSKM
tPG_ERROR
tbit
C
- is the smaller of the two measured values tRSKM(p) and tRSKM(n)
- Test equipment (pattern generator) intrinsic output pulse position timing uncertainty
- serial bit time
- LVDS302 set-up and hold-time uncertainty
Note: C can be derived by subtracting the receiver skew margin t RSKM(p) + tRSKM(p) from one serial bit time
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Figure 22. Jitter Budget
16
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Parameter Measurement Information (continued)
tF
t setup
80% (VOH -V OL )
R[7:0], G[7:0],
B[7:0], HS, VS, DE
20% (VOH -V OL )
t hold
t OSK
tR
VOH
80% (VOH -V OL )
PCLK
50% (VOH
- –VOL)
(CPOL=0)
20% (VOH -VOL )
VOL
tR
tF
Note:
The Set-up and Hold-time of CMOS outputs R[7:0], G[7:0],
B[7:0], HS, VS, and DE in relation to PCLK can be
calulated by:
1
tS&H =
2 -rPCLK -tREF - tOSK - DtDUTP
Figure 23. Output Rise and Fall, Setup and Hold Time
VDx+ – VDx– , VCLK+ – VCLK–
tf
80%(VID)
100%(VIC)
tr
0V
20%(VID)
0%(VID)
Figure 24. SubLVDS Differential Input Rise and Fall Time Defintion
CLK+, Dx+
VDDLVDS
RID /2
R BBDC
Gain
Stage
RID/2
CLK–, Dx–
Standby
detection
line end
termination
ESD
Figure 25. Equivalent Input Circuit Design
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Parameter Measurement Information (continued)
I ICMOS
SWAP,
CPOL, LSx,
RXEN, F/S
CMOS Input
(V I++V I-)/2
I I+
V ICMOS
CLK+, Dx+
V ID
RGB, VS, HS,
CPE PCLK
IO
I ICLK-, DxV I+
V ICM
VO
V ISubLVDS Input
CMOS Output
Figure 26. I/O Voltage and Current Definition
RGB, VS, HS,
CPE, PCLK
VO
SN65LVDS302
CL=10 pF
Figure 27. CMOS Output Test Circuit, Signal and Timing Definition
18
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Parameter Measurement Information (continued)
R7(n–2)
D0+
Pixel(n)
Pixel(n–1)
R7(n–1)
R7 R6 R5 R4
Pixel(n+1)
R7(n)
R7(n+1)
CP R7
CP R7
CLK–
CLK+
tPD(L)
VDD/2
PCLK
(CPOL = 0)
Pixel(n–1)
CMOS Data Out
R7
R7(n–3)
R7(n–1)
R6
R6(n–3)
R6(n–1)
Figure 28. Propagation Delay Input to Output (LS0 = LS1 = 0)
V DD /2
RXEN
t GS
CLK
t PLL
VCO Internal Signal
PLL Approaches Lock
t pwrup
PCLK
R[7:0], G[7:0], B[7:0], VS, HS
DE
Figure 29. Receiver Phase Lock Loop Set Time and Receiver Enable Time
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Parameter Measurement Information (continued)
<20 ns
3 ms
Glitch shorter
than t GS will be
ignored
2 ms
less than 20ns
Spike will be
rejected
Glitch shorter
than tGS will be
ignored
RXEN
t pwrup
tpwrdn
PCLK
t GS
I CC
tGS
CLK
Receiver disabled
(OFF)
RX RX disabled
turns (OFF)
OFF
Receiver enabled
(ON)
Receiver aquires lock
Figure 30. Receiver Enable and Disable Glitch Suppression Time
CLK
t
t
wakeup
sleep
PCLK
R[7:0], G[7:0], B[7:0], VS, HS,
RX enabled
output data valid
Receiver aquires lock,
outputs still disabled
Receiver disabled
(OFF)
RX enabled;
output data
invalid
RX
disabled
(OFF)
Figure 31. Standby Detection
7.1 Power Consumption Tests
Table 2 shows an example test pattern word.
Table 2. Example Test Pattern Word
WORD
7
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
1
0x7C3E1E7
C
3
E
1
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7
0
20
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
E
7
B6
B5
B4
B3
B2
B1
B0
0
0
0
1
1
1
1
0
0
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VS HS DE
1
1
1
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7.2 Typical IC Power Consumption Test Pattern
Typical power-consumption test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit
receive words in 2-channel mode and five 30-bit receive words in 3-channel mode. The pattern repeats itself
throughout the entire measurement. It is assumed that every possible code on the RGB outputs has the same
probability to occur during typical device operation.
Table 3. Typical IC Power Consumption Test Pattern, 1-Channel Mode
WORD
TEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
1
0x0000007
2
0xFFF0007
3
0x01FFF47
4
0xF0E07F7
5
0x7C3E1E7
6
0xE707C37
7
0xE1CE6C7
8
0xF1B9237
9
0x91BB347
10
0xD4CCC67
11
0xAD53377
12
0xACB2207
13
0xAAB2697
14
0x5556957
15
0xAAAAAB3
16
0xAAAAAA5
Table 4. Typical IC Power Consumption Test Pattern, 2-Channel Mode
WORD
TEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
1
0x0000001
2
0x03F03F1
3
0xBFFBFF1
4
0x1D71D71
5
0x4C74C71
6
0xC45C451
7
0xA3aA3A5
8
0x5555553
Table 5. Typical IC Power Consumption Test Pattern, 3-Channel Mode
WORD
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
1
0xFFFFFF1
2
0x0000001
3
0xF0F0F01
4
0xCCCCCC1
5
0xAAAAAA7
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7.3 Maximum Power Consumption Test Pattern
The maximum (or worst-case) power consumption of the SN65LVDS302 is tested using the two different test
pattern shown in table. Test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit
receive words in 2-channel mode, and five 30-bit receive words in 3-channel mode. The pattern repeats itself
throughout the entire measurement. It is assumed that every possible code on RGB outputs has the same
probability to occur during typical device operation.
Table 6. Worst-Case Power Consumption Test Pattern
TEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
WORD
1
0xAAAAAA5
2
0x5555555
Table 7. Worst-Case Power Consumption Test Pattern
TEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
WORD
1
0x0000000
2
0xFFFFFF7
7.4 Output Skew Pulse Position and Jitter Performance
The following test patterns are used to measure the output skew pulse position and the jitter performance of the
SN65LVDS302. The jitter test pattern stresses the interconnect, particularly to test for ISI, using very long runlengths of consecutive bits, and incorporating very high and low data rates, maximizing switching noise. Each
pattern is self-repeating for the duration of the test.
Table 8. Receive Jitter Test Pattern, 1-Channel Mode
WORD
22
TEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
1
0x0000001
2
0x0000031
3
0x00000F1
4
0x00003F1
5
0x0000FF1
6
0x0003FF1
7
0x000FFF1
8
0x0F0F0F1
9
0x0C30C31
10
0x0842111
11
0x1C71C71
12
0x18C6311
13
0x1111111
14
0x3333331
15
0x2452413
16
0x22A2A25
17
0x5555553
18
0xDB6DB65
19
0xCCCCCC1
20
0xEEEEEE1
21
0xE739CE1
22
0xE38E381
23
0xF7BDEE1
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Table 8. Receive Jitter Test Pattern, 1-Channel Mode (continued)
WORD
TEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
24
0xF3CF3C1
25
0xF0F0F01
26
0xFFF0001
27
0xFFFC001
28
0xFFFF001
29
0xFFFFC01
30
0xFFFFF01
31
0xFFFFFC1
32
0xFFFFFF1
Table 9. Receive Jitter Test Pattern, 2-Channel Mode
WORD
TEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
1
0x0000001
2
0x000FFF3
3
0x8008001
4
0x0030037
5
0xE00E001
6
0x00FF001
7
0x007E001
8
0x003C001
9
0x0018001
10
0x1C7E381
11
0x3333331
12
0x555AAA5
13
0x6DBDB61
14
0x7777771
15
0x555AAA3
16
0xAAAAAA5
17
0x5555553
18
0xAAA5555
19
0x8888881
20
0x9242491
21
0xAAA5571
22
0xCCCCCC1
23
0xE3E1C71
24
0xFFE7FF1
25
0xFFC3FF1
26
0xFF81FF1
27
0xFE00FF1
28
0x1FF1FF1
29
0xFFCFFC3
30
0x7FF7FF1
31
0xFFF0007
32
0xFFFFFF1
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Table 10. Receive Jitter Test Pattern, 3-Channel Mode
WORD
24
TEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
1
0x0000001
2
0x0000001
3
0x0000003
4
0x0101013
5
0x0303033
6
0x0707073
7
0x1818183
8
0xE7E7E71
9
0x3535351
10
0x0202021
11
0x5454543
12
0xA5A5A51
13
0xADADAD1
14
0x5555551
15
0xA6A2AA3
16
0xA6A2AA5
17
0x5555553
18
0x5555555
19
0xAAAAAA1
20
0x5252521
21
0x5A5A5A1
22
0xABABAB1
23
0xFDFCFD1
24
0xCAAACA1
25
0x1818181
26
0xE7E7E71
27
0xF8F8F81
28
0xFCFCFC1
29
0xFEFEFE1
30
0xFFFFFF1
31
0xFFFFFF5
32
0xFFFFFF5
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8 Detailed Description
8.1 Overview
The SN65LVDS302 is a de-serialising device where the input serial data and clock are received through Sub
Low-Voltage Differential Signaling (SubLVDS) lines. The SN65LVDS302 supports three operating power modes
(Shutdown, Standby, and Active) to conserve power.
Two Link Select lines LS0 and LS1 select whether 1, 2, or 3 serial links are used. The RXEN input may be used
to put the SN65LVDS302 in a Shutdown mode. The SN65LVDS302 enters an active Standby mode if the
common mode voltage of the CLK input becomes shifted to VDDLVDS, as when the transmitter releases the CLK
output into high-impedance. This minimizes power consumption without the need of switching an external control
pin. The SN65LVDS302 is characterized for operation over ambient air temperatures of –40°C to 85°C. All
CMOS and SubLVDS signals are 2-V tolerant with VDD = 0 V. This feature allows signal power-up before VCC is
stabilized.
When receiving, the PLL locks to the incoming clock (CLK) and generates an internal high-speed clock at the line
rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the Pixel clock (PCLK) generated from
the internal high-speed clock. If no input CLK signal is present, the output bus is held static with the PCLK and
DE held low, while all other parallel outputs are pulled high.
The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of
the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7], VS, HS, DE. This
gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device
on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output
rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher load
designs.
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8.2 Functional Block Diagram
VDDLVDS
RBBDC
CPE
iPCLK
D0+
50
Parity
Check
SubLVDS
SWAP
F/S
AND
50
D0-
1
50
SubLVDS
50
D1VDDLVDS
RBBDC
D2+
50
RGB=1
HS=VS=1
DE=0
D2VDDLVDS
8
0
0
1
SubLVDS
50
8
Output Buffer
D1+
27-bit parallel
Register
Serial-to-parallel conversion
VDDLVDS
RBBDC
8
R[0:7]
G[0:7]
B[0:7]
HS
VS
standby or
pwr down
DE
RBBDC
CLK+
x10, x15, or x30
50
PLL
multiplier
SubLVDS
50
CLK-
x1
iPCLK
0
PCLK
1
standby
CPOL
Vthstby
RXEN
Glitch
Suppression
LS0
Control
LS1
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8.3 Feature Description
8.3.1 Swap Pin Functionality
The SWAP pin allows the pcb designer to reverse the RGB bus, minimizing potential signal crossovers due to
signal routing. The two drawings beneath show the RGB signal pin assignment based on the SWAP pin setting.
1
2
3
4
5
6
7
8
9
A
3
4
5
6
7
8
9
R4
R2
R0
G6
G4
G2
R5
R3
R1
G7
G5
G3
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
B1
B3
B5
B7
G1
G3
G5
B2
B4
B6
G0
G2
G4
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
B
R7
C
B0
C
D
F
2
A
R6
B
E
1
D
SN65LVDS302
Top View
E
F
G
SN65LVDS302
Top View
G
PCLK
PCLK
H
H
VS
J
VS
HS
HS
J
DE
DE
Figure 32. Pinout With SWAP PIN = GND
Figure 33. Pinout With SWAP PIN = VDD
8.3.2 Parity Error Detection and Handling
The SN65LVDS302 receiver performs error checking on the basis of a parity bit that is transmitted across the
subLVDS interface from the transmitting device. Once the SN65LVDS302 detects the presence of the clock and
the PLL has locked onto PCLK, then the parity is checked. Parity-error detection ensures detection of all single
bit errors in one pixel and 50% of all multi-bit errors.
The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS, and DE. Odd Parity
bit signalling is used. The parity error is output on the CPE pin. If the sum of the 27 data bits and the parity bit
result in an odd number, the receive data are assumed to be valid. The CPE output is held low. If the sum equals
an even number, parity error is declared. The CPE output indicates high for half a PCLK period. The CPE output
is set with the data bit transition and cleared after 1/2 the data bit time. This allows counting every detected parity
error with a simple counter connected to CPE.
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Feature Description (continued)
A Parity error is indicated by a
high pulse on CPE; the width of
the pulse is 1/2 the length of a
PCLK cycle
Also if there is a parity error detected then the
data on that PCLK cycle is not output. Instead,
the last valid data from a previous PCLK cycle
is repeated on the output bus. This is to prevent
any bit error that may occur on the LVDS link
from causing perturbations in VS, HS, or DE that
may be visually disruptive to a display.
CPE
R[0:7], G[0:7],
B[0:7], HS, VS, DE
PCLK
The reserved bits are not covered in the parity
calculations.
(CPOL=0)
When a parity error is
detected, the receiver outputs
the previous pixel on the bus
Hence no data transitions
occur.
Figure 34. Parity Error Detection and Handling
8.4 Device Functional Modes
8.4.1 Deserialization Modes
The SN65LVDS302 receiver has three modes of operation controlled by link-select pins LS0 and LS1. Table 11
shows the deserializer modes of operation.
Table 11. Logic Table: Link Select Operating Modes
LS1
LS0
MODE OF OPERATION
DATA LINKS STATUS
0
0
1ChM
1-channel mode (30-bit serialization rate)
D0 active;
D1, D2 disabled
0
1
2ChM
2-channel mode (15-bit serialization rate)
D0, D1 active;
D2 disabled
1
0
3ChM
3-channel mode (10-bit serialization rate)
D0, D1, D2 active
1
1
Reserved
Reserved
8.4.1.1 1-Channel Mode
While LS0 and LS1 are held low, the SN65LVDS302 receives payload data over a single SubLVDS data pair,
D0. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 30. The internal
high speed clock is used to shift in the data payload on D0 and to deserialize 30 bits of data. Figure 35 illustrates
the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is divided by
a factor of 30 to recreate the pixel clock and the data payload with the pixel clock is presented on the output bus.
The reserved bits and parity bit are not output. While in this mode, the PLL can lock to a clock that is in the range
of 4 MHz through 15 MHz. This mode is intended for smaller video display formats that do not need the full
bandwidth capabilities of the SN65LVDS302.
CLK CLK +
D0 +/- CHANNEL res res CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE res res CP R7 R6
Figure 35. Data and Clock Input in 1-ChM (LS0 and LS1 = low)
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8.4.1.2 2-Channel Mode
While LS0 is held high and LS1 is held low, the SN65LVDS302 receives payload data over two SubLVDS data
pairs, D0 and D1. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 15.
The internal high speed clock is used to shift in the data payload on D0 and D1 and to deserialize 15 bits of data
from each pair. Figure 36 illustrates the timing and the mapping of the data payload into the 30-bit frame. The
internal high speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel
clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode the PLL
can lock to a clock that is in the range of 8 MHz through 30 MHz.
CLK CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP R7 R6
D1 +/- CHANNEL res G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE res G3 G2
Figure 36. Data and Clock Input in 2-ChM (LS0 = high; LS1 = low)
8.4.1.3 3-Channel Mode
While LS0 is held low and LS1 is held high the SN65LVDS302 receives payload data over three SubLVDS data
pairs: D0, D1, and D2. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of
10. The internal high speed clock is used to shift in the data payload on D0, D1, and D2, and to deserialize 10
bits of data from each pair. Figure 37 illustrates the timing and the mapping of the data payload into the 30-bit
frame. While in this mode the PLL can lock to a clock that is in the range of 20 MHz through 65 MHz.
CLK CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6
D1 +/- CHANNEL res G7 G6 G5 G4 G3 G2 G1 G0 HS res G7 G6
D2 +/- CHANNEL res B7 B6 B5 B4 B3 B2 B1 B0 DE res B7 B6
Figure 37. Data and Clock Input in 3-ChM (LS0 = low; LS1 = high)
8.4.2 Powerdown Modes
The SN65LVDS302 Receiver has two powerdown modes to facilitate efficient power management.
8.4.2.1 Shutdown Mode
A low input signal on the RXEN pin puts the SN65LVDS302 into Shutdown mode. This turns off most of the
receiver circuitry including the SubLVDS receivers, PLL, and deserializers. The subLVDS differential-input
resistance remains 100 Ω, while any input signal is ignored. All outputs hold a static output pattern:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.
The current draw in Shutdown mode is nearly zero if the SubLVDS inputs are left open or pulled high.
8.4.2.2 Standby Mode
The SN65LVDS302 enters the Standby mode when the SN65LVDS302 is not in Shutdown mode but the
SubLVDS clock-input common-mode voltage is above 0.9 × VDDLVDS. The CLK input incorporates a pull-up circuit
to shift the SubLVDS clock-input common-mode voltage to VDDLVDS in the absence of an input signal. All circuitry
except the SubLVDS clock-input Standby monitor is shut down. The SN65LVDS302 also enters Standby mode
when the input clock frequency on the CLK input is less than 500 kHz. The SubLVDS input resistance remains
100 Ω while any input signal on the data inputs D0, D1, and D2 becomes ignored. All outputs holds a static
output pattern:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.
The current drawn in Standby mode is very low.
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8.4.3 Active Modes
A high input signal on RXEN combined with a CLK input signal switching faster than 3 MHz and VICM smaller
than 1.3 V forces the SN65LVDS302 into Active mode. Current consumption in active mode depends on
operating frequency and the number of data transitions in the data payload. CLK-input frequencies from 3 MHz to
4 MHz activates the device but proper PLL functionality is not secured. The SN65LVDS302 must not be operated
in active mode at CLK frequencies below 4 MHz.
8.4.3.1 Acquire Mode (PLL Approaches Lock)
When the SN65LVDS302 is enabled and a SubLVDS clock input present, the PLL pursues lock to the input
clock. While the PLL pursues lock the output data bus holds a static output pattern:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.
For proper device operation, the pixel clock frequency must fall within the valid fPCLK range specified under
recommended operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than fPCLK(min),
the SN65LVDS302 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the
pixel clock, causing the PLL monitor to release the device into active receive mode. If this happens, the PLL may
or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and
PLL deadlock (loss of VCO oscillation).
8.4.3.2 Receive Mode
After the PLL achieves lock the device enters the normal receive mode. The output data bus presents the deserialized data. The PCLK output pin outputs the recovered pixel clock.
8.4.4 Status Detect and Operating Modes Flow
The SN65LVDS302 switches between the power saving and active modes in the following way:
Power Up
RXEN = 1
CLK Input Inactive
RXEN Low
for > 10 ms
Power Up
RXEN = 0
ShutDown
Mode
Standby
Mode
RXEN High
for > 10 ms
VICM(CLK) > 0.9 VDDLVDS
RXEN Low
for > 10 ms
VICM(CLK) > 0.9 VDDLVDS
or fCLK < 500 kHz
CLK Input Active
Power Up
RXEN = 1
CLK Active
RXEN Low
for > 10 ms
Receive
Mode
PLL Achieved Lock
Acquire
Mode
Figure 38. Operating Modes and State Machine Diagram
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Table 12. Status Detect and Operating Modes Descriptions
MODE
CHARACTERISTICS
CONDITIONS
Shutdown
Mode
Least amount of power consumption (most circuitry turned off);
All outputs held static:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;
RXEN is set low for longer than 10 μs (1) (2)
Standby
Mode
Low power consumption (Standby monitor circuit active;
PLL is shutdown to conserve power); All outputs held static:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;
RXEN is high for longer than 10 μs, and both CLK input
common-mode VICM(CLK) above 0.9 × VDDLVDS, or CLK
input floating (2)
Acquire
Mode
PLL pursues lock; All outputs held static:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;
RXEN is high; CLK input monitor detected clock input
common mode and woke up receiver out of Standby
mode
Receive
Mode
Data transfer (normal operation);
receiver deserializes data and provides data on parallel output
RXEN is high and PLL is locked to incoming clock
(1)
(2)
In Shutdown Mode, all SN65LVDS302 internal switching circuits (for example: PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
Leaving CMOS control inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS
inputs must be tied to a valid logic level VIL or VIH during Shutdown or Standby Mode. Exceptions are the subLVDS inputs CLK and Dx,
which can be left unconnected while not in use.
Table 13. Operating Mode Transitions
MODE TRANSITION
USE CASE
TRANSITION SPECIFICS
1. RXEN high > 10 μs
2. Receiver enters standby mode
Shutdown → Standby Drive RXEN high to enable receiver
a. R[0:7] = G[0:7] = B[0:7] = VS = HS remain high and DE = PCLK
low
b. Receiver activates clock input monitor
1. CLK input monitor detects clock input activity
Standby → Acquire
Transmitter activity detected
2. Outputs remain static
3. PLL circuit is enabled
1. PLL is active and approaches lock
2. PLL achieves lock within twakeup
Acquire → Receive
Link is ready to receive data
3. D1, D2, or D3 become active depending on LS0 and LS1 selection
4. First Data word was recovered
5.
Receive → Standby
Transmitter requested to enter Standby
mode by input common mode voltage
VICM > 0.9 VDDLVDS as when
transmitter output clock stops or enters
high-impedance state.
Parallel output bus turns on switching from static output pattern to
output first valid data word
1. Receiver disables outputs within tsleep
2. RX Input monitor detects VICM > 0.9 VDDLVDS within tsleep
3.
R[0:7] = G[0:7] = B[0:7] = VS = HS transition to high and DE = PCLK
to low on next falling PLL clock edge
4. PLL shuts down. Clock activity input monitor remains active
1. RXEN pulled low for > tpwrdn
Receive and Standby
→ Shutdown
Turn off Receiver
2.
R[0:7] = G[0:7] = B[0:7] = VS = HS remain static high or transition to
static high and DE = PCLK remain or transition to static low
3. Most IC circuitry is shut down for least power consumption
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS
input unconnected or floating. Every input must be connected to a valid logic level VIH or VOL while power is
supplied to VDD. This also minimizes the power consumption of standby and power down mode.
9.1.2 Calculation Example: HVGA Display
Display Resolution:
480 × 320
Frame Refresh Rate:
58.4 Hz
Horizontal Visible Pixel:
480 columns
Horizontal Front Porch:
20 columns
Horizontal Sync:
5 columns
Horizontal Back Porch:
3 columns
Vertical Visible Pixel:
320 lines
Vertical Front Porch:
10 lines
Vertical Sync:
5 lines
Vertical Back Porch:
3 lines
Hsync =5
HBP
The following calculation shows an example for a Half-VGA display with the following parameters:
Visible area = 480 Columns
HFP=20
Vsync =5
VBP =3
Visible area
=320 lines
VFP=10
Visible area
Entire Display
Figure 39. HVGA Display
Calculation of the total number of pixel and blanking overhead:
Visible Area Pixel Count:
480 × 320 = 153600 pixel
Total Frame Pixel Count:
( 480 + 20 + 5 + 3 ) × ( 320 + 10 + 5 + 3 ) = 171704 pixel
Blanking Overhead:
( 171704 – 153600 ) ÷ 153600 = 11.8%
The application requires the following serial-link parameters:
Pixel Clk Frequency:
Serial Data Rate:
32
171704 × 58.4 Hz = 10 MHz
1-channel mode: 10 MHz × 30 bit/channel = 300 Mbps
2-channel mode: 10 MHz × 15 bit/channel = 150 Mbps
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Application Information (continued)
9.1.3 How to Determine Interconnect Skew and Jitter Budget
Designing a reliable data link requires examining the interconnect skew and jitter budget. The sum of all
transmitter, PCB, connector, FPC, and receiver uncertainties must be smaller than the available serial bit time.
The highest pixel clock frequency defines the available serial bit time. The transmitter timing uncertainty is
defined by tPPOS in the transmitter data sheet. For a bit-error-rate target of ≤ 10–12, the measurement duration for
tPPOS is ≥ 1012. The SN65LVDS302 receiver can tolerate a maximum timing uncertainty defined by tRSKM. The
interconnect budget is calculated by Equation 1.
t int erconnect = t RSKM - t PPOS
(1)
Example:
fPCLK(max)
23 MHz (VGA display resolution, 60 Hz)
Transmission mode: 2-ChM; tPPOS(SN65LVDS301)
330 ps
10–12
Target bit error rate
tRSKM(SN65LVDS302)
1 / (2 × 15 × fPCLK) – 480 ps = 969 ps
The interconnect budget for cable skew and ISI must be smaller than the output of Equation 2.
t int erconnect = t RSKM - t PPOS = 639ps
(2)
Ideal TPPosn data transition
Data Period /2
D0, D1, D2
TPPosn(min)
TPPosn(max)
Ideal receiver strobe position
RSKM
RSKM
RX internal sampling clock
Tppos: Transmitter output pulse position (min and max)
RSKM: Receiver Skew Margin
TPPosx(max) -TPPosx(min) = TJ TXPLL(non-trackable) + tTXskew + tTXDJ
RSKM = SKEW PCB + XTALK PCB + ISIPCB
TJ TXPLL(non-trackable): non-trackable TX PLL jitter; this jitter is the integration
> f (BWRX);
of total jitter above the receiver PLL bandwidth ; TJ TXPLL
TJ=RJ[ps-rms]*14 + DJ[ps]
t TXskew
: transmitter output skew (skew between CLK and data)
t TXIDJTransmitter Deterministic JItter of TX output stage (includes TX
Intersymbol Interference ISI)
RSPosn (max)
RSPosn (min)
SKEW
XTALK
RSPosn: Receiver input strobe position (min and max)
RSPosn(max) - RSPosn(min) = SkewRX + S&HRX + TJ (RXPLL(non-trackable)
PCB : PCB induced Skew (trace + connector);
: PCB induced cross-talk;
PCB
ISI PCB: Inter-symbol interference of PCB; is
dependent on interconnect frequency loss; may be
zero for short interconnects.
Skew RX: Receiver input skew (skew between CLK and Dx input)
S&H RX: Receiver input latch Sample & Hold uncertainty
TJ (RXPLL(non-trackable) : Intrinsic RX PLL jitter above RX PLL bandwidth; PLL
TJ >
f(BW RX ); TJ=RJ[ps-rms]*14 + DJ[ps]
Figure 40. Jitter Budget
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Application Information (continued)
9.1.4 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
NOTE
Receiver PLL tracking: To maximize the design margin for the interconnect, good RX
PLL tracking of the TX PLL is important. FlatLink3G requires the RX PLL to have a
bandwidth higher than the bandwidth of the TX PLL. The SN65LVDS302 PLL design is
optimized to track the SN65LVDS0301 PLL particularly well, thus providing a very large
receiver skew margin. A FlatLink3G-compliant link must provide at least ±225 ppm of
receiver skew margin for the interconnect.
It is important to understand the tradeoff between power consumption, EMI, and maximum speed when selecting
the F/S signal. It is beneficial to choose the slowest rise time possible to minimize EMI and power consumption.
Unfortunately a slower rise time also reduces the timing margin left for the LCD driver. Hence it is necessary to
calculate the timing margin to select the correct F/S pin setting.
The output rise time depends on the output driver strength and the output load. An LCD driver typical capacitive
load is assumed with approximately 10 pF. As the capacitive load increases, the rise time also increases. Rise
time of the SN65LVDS302 is measured as the time duration it takes the output voltage to rise from 20% of VDD
and 80% of VDD and fall time is defined as the time for the output voltage to transition from 80% of VDD down to
20%.
Within one mode of operation and one F/S pin setting, the rise time of the output stage is fixed and does not
adjust to the pixel frequency. Due to the short bit time at very fast pixel clock speeds and the real capacitive load
of the display driver, the output amplitude might not reach VDD and GND saturation fully. To ensure sufficient
signal swing and verify the design margin, it becomes necessary to determine that the output amplitude under
any circumstance reaches the display driver’s input stage logic threshold (usually 30% and 70% of VDD).
Figure 41 shows a worst-case rise time simulation assuming a LCD driver load of 16 pF at VGA display
resolution. PCLK is the fastest switching output. With F/S set to GND (Figure 42), the PCLK output voltage
amplitude is significantly reduced. The voltage amplitude of the output data RGB[7:0], VS, HS, and DE shows
less amplitude attenuation because these outputs carry random data pattern and toggle equal or less than half of
the PCLK frequency. It is necessary to determine the timing margin between the LVDS302 output and LCD driver
input.
Application: VGA (2-channel mode)
2
1.8
1.8
1.6
1.6
1.4
1.4
Output Amplitude (V)
Output Amplitude (V)
Application: VGA (2-channel mode)
2
1.2
1
0.8
0.6
1.2
1
0.8
0.6
0.4
0.4
0.2
0.2
0
0
100
150
200
250
300
350
400
450
500
550
600
100
150
200
RX Rise/Fall Time (ns)
CLK 22 MHz
F/S = VDD
300
350
400
450
500
550
600
RX Rise/Fall Time (ns)
data 22 Mbps
CLK 22 MHz
CL = 16 pF
Figure 41. Output Amplitude vs
Toggling Frequency (F/S = 1)
34
250
data 22 Mbps
The data signal has a slower maximum switching frequency, and
therefore drives a larger amplitude than the clock signal.
Figure 42. Output Amplitude vs
Toggling Frequency (F/S = 0)
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Application Information (continued)
9.1.5 How to Determine the LCD Driver Timing Margin
To determine the timing margin, it is necessary to specify the frequency of operation, identify the set-up and hold
time of the LCD driver, and specify the output load of the SN65LVDS302 as a combination of the LCD driver
input parasitics plus any capacitance caused by the connecting PCB trace. Furthermore, the setting of pin F/S
and the SN65LVDS302 output skew impact the margin. The total remaining design margin calculates as
following:
t rise(max ) ´ C LOAD
1
t DM =
- t DUTP(max_ error ) - t OSK
2´ ƒ
10 pF
PCLK
where
•
•
•
•
•
•
tDM is the design margin
fPCLK is the pixel clock frequency
tDUTP(max_error) is the maximum duty cycle error
trise(max) is the maximum rise or fall time; see tR/F under switching characteristics
CL is the parasitic capacitance (sum of LCD driver input parasitics + connecting PCB trace)
tskew is the clock to data output skew SN65LVDS302
(3)
Example:
At a pixel clock frequeny of 5.5 MHz (QVGA), and an assumed LCD driver load of 15 pF, the remaining timing
margin is:
t DM
t DUTP (max ) - 50
5%
1
´ t PCLK =
´
= 9.1ns
100%
100% 5.5 MHz
16 ns (F/S =GND ) ´ 15 pF
1
=
- 9 ns - 500 ps = 57.3 ns
2 ´ 5.5 MHz
10 pF
t DUTP(max_ error ) =
(4)
(5)
As long as the set-up and hold time of the LCD driver are each less than 57 ns, the timing budget is met
sufficiently.
9.1.6 Typical Application Frequencies
The SN65LVDS302 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 14
provides a few typical display resolution examples and shows the number of data lanes necessary to connect the
SN65LVDS302 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is
smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh
rate of 60 Hz. The actual refresh rate may differ depending on the application-processor clock implementation.
Table 14. Typical Application Data Rates and Serial Lane Usage
DISPLAY SCREEN
RESOLUTION
SERIAL DATA RATE PER LANE
VISIBLE PIXEL
COUNT
BLANKING
OVERHEAD
DISPLAY
REFRESH RATE
PIXEL CLOCK
FREQUENCY [MHz]
1-ChM
38,720
20%
90 Hz
4.2 MHz
125 Mbps
240x320 (QVGA)
76,800
20%
60 Hz
5.5 MHz
166 Mbps
640x200
128,000
20%
60 Hz
9.2 MHz
276 Mbps
138 Mbps
352x416 (CIF+)
146,432
20%
60 Hz
10.5 MHz
316 Mbps
158 Mbps
352x440
154,880
20%
60 Hz
11.2 MHz
335 Mbps
167 Mbps
320x480 (HVGA)
153,600
20%
60 Hz
11.1 MHz
332 Mbps
166 Mbps
800x250
200,000
20%
60 Hz
14.4 MHz
432 Mbps
216 Mbps
640x320
204,800
20%
60 Hz
14.7 MHz
442 Mbps
221 Mbps
640x480 (VGA)
307,200
20%
60 Hz
22.1 MHz
332 Mbps
221 Mbps
1024x320
327,680
20%
60 Hz
23.6 MHz
354 Mbps
236 Mbps
854x480 (WVGA)
409,920
20%
60 Hz
29.5 MHz
443 Mbps
295 Mbps
800x600 (SVGA)
480,000
20%
60 Hz
34.6 MHz
346 Mbps
1024x768 (XGA)
786,432
20%
60 Hz
56.6 MHz
566 Mbps
176x220 (QCIF+)
2-ChM
3-ChM
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9.2 Typical Applications
9.2.1 VGA Application
Figure 43 shows a possible implementation of a standard 640x480 VGA display. The LVDS301 interfaces to the
SN65LVDS302, which is the corresponding receiver device to deserialize the data and drive the display driver.
The pixel clock rate of 22 MHz assumes approximately 10% blanking overhead and 60 Hz display refresh rate.
The application assumes 24-bit color resolution. Also shown is how the application processor provides a
powerdown (reset) signal for both serializer and the display driver. The signal count over the Flexible Printed
Circuit board (FPC) could be further decreased by using the standby option on the SN65LVDS302 and pulling
RXEN high with a 30 kΩ resistor to VDD.
GND
GND
CLK+
CLK–
Pixel CLK
D[7:0]
D[15:8]
D[23:16]
HS, VS, DE
PCLK
22MHz
R[7:0]
G[7:0]
B[7:0]
HS, VS, DE
27
22MHz
D0+
D0–
330Mbps
D1+
D1–
330Mbps
CLK+
CLK–
D0+
D0–
PCLK
D1+
D1–
R[7:0]
G[7:0]
B[7:0]
HS, VS, DE
Video Mode Display
Driver
22MHz
27
SN65LVDS 302
LS0
TXEN
LS0
LS1
SPI
SN65LVDS 301
RESET
2x0.01uF
1.8 V
LCD with VGA
resolution
1.8V
SPI
1.8V
ENABLE
2.7V
LS1
Application
Processor
(e.g. OMAP)
2x0.1uF
GND
RXEN
VDDx
GND
2x0.01uF
FPC
2.7V
GND
GND
VDDx
2x0.1uF
1.8V
If FPC wire count is critical, replace this
connection with a pull-up resistor at RXEN
Serial port interface
(3-wire IF)
3
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Typical VGA Display Application
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 15 as the input parameters.
Table 15. Design Parameters
DESIGN PARAMETER
36
EXAMPLE VALUE
Operating free-air temperature range
–40°C to 85°C
Supply voltages, VDD, VDDLVDS, VDDPLLA, VDDPLLD
1.65 V to 1.95 V
Magnitude of differential input voltage, VID
70 mV to 200 mV
Input voltage common mode range, VICM
0.6 V to 1.2 V
Receiver input skew, 2-channel mode
< 630 ps
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9.2.1.2 Detailed Design Procedure
Configuration and Connection:
• Include a power supply capable of providing the power requirements of the whole system.
• Configure the Application Processor to transmit the RGB data at 22 MHz.
• Configure the transmitter and the SN65LVDS302 to work using two channels.
• Connect the SN65LVDS302 to the LCD display following the same color mapping. See Swap Pin
Functionality for more information.
9.2.1.2.1 Power-Up and Power-Down Sequences
The SN65LVDS302 does not require a specific power up sequence for the voltage lines. However, TI
recommends using the power-up and power-down sequences detailed below.
Power-up sequence (SN65LVDS301 RXEN input initially low):
1. Ramp up LCD power and SN65LVDS302 (approximately 0.5 ms to 10 ms) but keep the backlight turned off.
2. Wait for an additional 0 ms to 200 ms to ensure display noise does not occur.
3. Enable video source output; start sending black video data.
4. Toggle SN65LVDS301 TXEN = VIH.
5. Toggle SN65LVDS302 RXEN = VIH.
6. Send at least 1 ms of black video data. This allows the SN65LVDS301 to be phase locked, and the display
to show black data first.
7. Start sending true image data.
8. Enable backlight.
Power-down sequence (SN65LVDS301 RXEN input initially high):
1. Disable LCD backlight and wait for the minimum time specified in the LCD datasheet for the backlight to go
low.
2. Switch the video source output from active video data to black image data (all visible pixels turn black) for at
least 2 frame times.
3. Set SN65LVDS301 TXEN = GND and wait for 250 ns.
4. Set SN65LVDS302 RXEN = GND and wait for 250 ns.
5. Disable the video output of the video source.
6. Remove power from the LCD panel for lowest system power.
250
249
190
190
0
Output Voltage Amplitude - mV
Output Voltage Amplitude - mV
9.2.1.3 Application Curves
2-Channel Mode,
f(PCLK) = 22 MHz
–190
2-Channel Mode,
f(PCLK) = 22 MHz
0
–190
–250
–251
500 ps/div
Response Over 8-inch FR-4 + 1m Coax Cable
Figure 44. VGA 2-Channel Output Waveform
500 ps/div
Response Over 80-inch FR-4 + 1m Coax Cable
Figure 45. VGA 2-Channel Output Waveform
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249
Output Voltage Amplitude - mV
190
3-Channel Mode,
f(PCLK) = 22 MHz
0
–190
–251
1 ns/div
Response Over 80-inch FR-4 + 1m Coax Cable
Figure 46. VGA3-Channel Output Waveform
9.2.2 Dual LCD-Display Application
The example in Figure 47 shows a possible application setup driving two video-mode displays from one
application processor. The data rate of 330 Mbps at a pixel clock rate of 5.5 MHz corresponds to a 320x240
QVGA resolution at 60 Hz refresh rate and 10% blanking overhead.
18+3
CLK+
CLK-
PCLK
CLK+
CLKD0+
330Mbps
D0-
PCLK
R[ 5:
G[ 5:
B[ 5:
HS, VS,
0]
0]
0]
DE
LS0
PCLK
EN
SIN
SOUT
SCLK
Display Driver
PCLK
1.8V
1
21
SN65LVDS 302
TXEN
LS0
LS1
SN 65LVDS 301
SCLK
SI N
SOUT
SEL2
SEL1
Display Driver
5.5MHz
D0+
D0-
R[ 5: 0]
G[ 5: 0]
B[ 5: 0]
HS, VS, DE
GND
2x0.01uF
LCD with QVGA
resolution
1. 8V
GND
2. 7V
1. 8V
EN
SIN
SOUT
SCLK
1.8V
2
LCD wit h QVGA
resolut ion
D[ 5: 0]
D[ 11 : 6]
D[ 17 : 12 ]
HS, VS, DE
5.5MHz
2. 7V
GND
2x0.1uF
GND
RXEN
VDDx
Application
Processor
(e.g. OMAP )
Pixel CLK
GND
2x0.01uF
FPC
VDDx
GND
LS1
2x0.1uF
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Example Dual-QVGA Display Application
9.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 16 as the input parameters.
Table 16. Design Parameters
DESIGN PARAMETER
38
EXAMPLE VALUE
Operating free-air temperature range
–40°C to 85°C
Supply voltages, VDD, VDDLVDS, VDDPLLA, VDDPLLD
1.65 V to 1.95 V
Magnitude of differential input voltage, VID
70 mV to 200 mV
Input voltage common mode range, VICM
0.6 V to 1.2 V
Receiver input skew, 1-channel mode
< 630 ps
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9.2.2.2 Application Curve
249
Output Voltage Amplitude - mV
190
1-Channel Mode,
f(PCLK) = 5.5 MHz
0
–190
–251
1 ns/div
Response Over 80-inch of FR-4 + 1m Coax Cable
Figure 48. QVGA Output Waveform
10 Power Supply Recommendations
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS822 power pins. TI
recommends placing one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors on
each power node. The distance between the SN65LVDS822 and capacitors must be minimized to reduce loop
inductance and provide optimal noise filtering. Placing the capacitor underneath the SN65LVDS822 on the
bottom of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize
the EMI performance.
11 Layout
11.1 Layout Guidelines
Use chamfered corners (45° bends) instead of right-angle (90°) bends. Right-angle bends increase the effective
trace width, which changes the differential trace impedance creating large discontinuities. A 45° bend is seen as
a smaller discontinuity.
When routing traces next to a via or between an array of vias, make sure that the via clearance section does not
interrupt the path of the return current on the ground plane below.
Avoid metal layers and traces underneath or between the pads of the LVDS connectors for better impedance
matching. Otherwise they cause the differential impedance to drop below 75 Ω and fail the board during TDR
testing.
Use solid power and ground planes for 100 Ω impedance control and minimum power noise.
For a multilayer PCB, TI recommends keeping one common GND layer underneath the device and connect all
ground terminals directly to this plane. For 100 Ω differential impedance, use the smallest trace spacing possible,
which is usually specified by the PCB vendor.
Keep the trace length as short as possible to minimize attenuation.
Place bulk capacitors (10 μF) close to power sources, such as voltage regulators or where the power is supplied
to the PCB.
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11.2 Layout Example
45° Bends
100 Ω Differential pairs
Figure 49. Layout Example
Differential pairs with matched lengths
Figure 50. LVDS Input
40
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12 Device and Documentation Support
12.1 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
FlatLink, E2E are trademarks of Texas Instruments.
μBGA is a registered trademark of Tessera, Inc.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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3-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65LVDS302ZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
LVDS302
SN65LVDS302ZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
LVDS302
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Feb-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65LVDS302ZQER
Package Package Pins
Type Drawing
BGA MI
CROSTA
R JUNI
OR
ZQE
80
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65LVDS302ZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
336.6
336.6
31.8
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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