Texas Instruments | SN75LVCP601 Two-Channel 6-Gbps SATA Redriver (Rev. H) | Datasheet | Texas Instruments SN75LVCP601 Two-Channel 6-Gbps SATA Redriver (Rev. H) Datasheet

Texas Instruments SN75LVCP601 Two-Channel 6-Gbps SATA Redriver (Rev. H) Datasheet
Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
SN75LVCP601 Two-Channel 6-Gbps SATA Redriver
1 Features
3 Description
•
•
•
The SN75LVCP601 device is a dual-channel, singlelane SATA redriver and signal conditioner supporting
data rates up to 6 Gbps. The device complies with
SATA physical link 2m and 3i specifications. The
SN75LVCP601 operates from one 3.3-V supply and
has 100-Ω line termination with a self-biasing feature,
making the device suitable for ac coupling. The inputs
incorporate an out-of-band (OOB) detector, which
automatically squelches the output while maintaining
a stable common-mode voltage compliant to the
SATA link. The device design also handles spreadspectrum clocking (SSC) transmission per the SATA
specification.
1
•
•
•
•
•
•
1.5-, 3-, or 6-Gbps Two-Channel Redriver
Integrated Output Squelch
Programmable RX and TX Equalization and
De-Emphasis Width Control
Power-Save Feature Lowers Power by >80%
in Auto Low-Power Mode
Low Power
– <220 mW (Typ)
– <50 mW (in Auto Low-Power Mode)
– <5 mW (in Standby Mode)
Excellent Jitter and Loss Compensation
Capability to Over 24-Inch (61-cm) FR4 Trace
20-Pin 4-mm × 4-mm QFN Package
High Protection Against ESD Transient
– HBM: 10,000 V
– CDM: 1,500 V
– MM: 200 V
Pin-Compatible With LVCP412A and MAX4951
The SN75LVCP601 device handles interconnect
losses at both its input and output. The input stage of
each channel offers selectable equalization settings
that are programmable to match the loss in the
channel. The differential outputs provide selectable
de-emphasis to compensate for the expected
distortion that the SATA signal experiences. The level
of equalization and de-emphasis settings depends on
the length of interconnect and its characteristics. The
setting of signal control pins EQ1, EQ2, DE1, and
DE2 controls both equalization and de-emphasis
levels.
2 Applications
•
•
•
•
•
Notebooks
Desktops
Docking Stations
Servers
Workstations
This device is hot-plug capable (requires the use of
ac-coupling capacitors at differential inputs and
outputs), thus preventing device damage under
device hot-insertion, in such cases as: async signal
plug or removal, unpowered plug or removal,
powered plug or removal, surprise plug or removal
Device Information(1)
PART NUMBER
SN75LVCP601
PACKAGE
WQFN (20)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
R = SN75LVCP601
HDD
ICH
HDD
ICH
R
PC/Workstation
Motherboard
eSATA
connector
eSATA
Cable
Notebook
Dock Connector
PC/WS MB
R
Dock
Notebook Dock
eSATA
connector
iSATA
connector
eSATA Cable
(2m)
HDD
SATA 6G Host
DT MB
Desktop Main Board
R
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Power Dissipation Characteristics ............................ 7
Timing Requirements ................................................ 8
Switching Characteristics .......................................... 8
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 11
7.1 Jitter and VOD Results: Case 1 at 6 Gbps ............. 12
7.2 Jitter and VOD Results: Case 2 at 3 Gbps ............. 13
7.3 Jitter and VOD Results: Case 3 at 1.5 Gbps .......... 15
8
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
18
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2016) to Revision H
Page
•
Changed pin DE1 number From: 8 To: 9 in the Pin Functions table .................................................................................... 4
•
Changed pin DE2 number From: 9 To: 8 in the Pin Functions table .................................................................................... 4
Changes from Revision F (June 2015) to Revision G
•
Page
Changed Pin 8 name To: DE2 and Pin 9 name To: DE1 in Figure 27 ............................................................................... 20
Changes from Revision E (January 2014) to Revision F
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added Storage temperature to the Absolute Maximum Ratings table ................................................................................... 5
•
Moved timing parameters out of Electrical Characteristics and into Timing Requirements .................................................. 8
•
Moved switching parameters out of Electrical Characteristics and into Switching Characteristics ....................................... 8
Changes from Revision D (January 2013) to Revision E
Page
•
Changed DJTX (UI = 333 ps) From: Max = 0.19 To: Max = 0.07 ........................................................................................... 8
•
Changed DJTX (UI = 167 ps) From: Max = 0.34 To: Max = 0.16 ........................................................................................... 8
Changes from Revision C (October 2012) to Revision D
•
2
Page
Corrected formatting of the Differential output-voltage swing dc level section of the Electrical Characteristics table ........... 7
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
Changes from Revision B (February 2012) to Revision C
Page
•
Deleted DiffVppTX row............................................................................................................................................................... 7
•
Inserted DiffVppTX_DE row ......................................................................................................................................................... 7
•
Changed Figure 5 caption .................................................................................................................................................... 10
•
Revised text of the Output Ed-Emphasis section ................................................................................................................. 18
•
Deleted setting recommendations on pulse durations for DEW1 and DEW2 ...................................................................... 18
Changes from Revision A (October 2011) to Revision B
•
Page
Changed pin type from CML to VML for pins 4, 5, 14, 15 in the Pin Functions table ............................................................ 4
Changes from Original (June 2010) to Revision A
•
Page
Changed pin EN number From: 4 To: 7 in the Pin Functions table ....................................................................................... 4
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
3
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
5 Pin Configuration and Functions
RTJ Package
16-Pin WQFN With Thermal Pad
111 RX2P
12
2 RX2N
14 TX1N
1
9
DE 2
GND 18
DE 1
VCC
LVCP601RTJ
VCC
DE 1
EQ 2 19
7
EN
VCC 20
6
DEW 2
TX2P
TX2N
5
DE 2
4
8
RX2P 11
RX2N 12
GND 13
TX1N 14
EQ 1 17
3
9
EN
GND
8
10
TX1P 15
DEW 1 16
7
2
Thermal Pad must
be soldered to PCB
GND plane for
efficient thermal
performance
10
RX1N
EQ 1 17
LVCP601RTJ
DEW 1 16
DEW 2
1
GND 18
6
RX1P
EQ 2 19
15 TX1P
1
5
TX2P
TX2N
4
GND
3
RX1N
2
RX1P
1
VCC 20
13 GND
1
Top View
Bottom View
Pin Functions
PIN
NAME
NO.
PIN TYPE
DESCRIPTION
CONTROL PINS
DE1 (1)
9
(1)
8
DE2
DEW1
Selects de-emphasis settings for CH 1 and CH 2 per Table 1.
Internally tied to VCC / 2.
I, LVCMOS
De-emphasis width control for CH 1 and CH 2.
0 = De-emphasis pulse duration, short
1 = De-emphasis pulse duration, long (default)
I, LVCMOS
Device enable and disable pin, internally pulled to VCC.
0 = Device in standby mode
1 = Device enabled (default)
I, LVCMOS
Selects equalization settings for CH 1 and CH 2 per Table 1.
Internally tied to VCC / 2.
16
DEW2
6
EN
7
EQ1 (1)
17
(1)
19
EQ2
I, LVCMOS
HIGH-SPEED DIFFERENTIAL I/O
RX1N
2
I, CML
RX1P
1
I, CML
RX2N
12
I, CML
RX2P
11
I, CML
TX1N
14
O, VML
TX1P
15
O, VML
TX2N
4
O, VML
TX2P
5
O, VML
GND
3, 13, 18
Power
Supply ground
VCC
10, 20
Power
Positive supply must be 3.3 V ± 10%
Noninverting and inverting CML differential input for CH 1 and CH 2. These pins
connect to an internal voltage bias via a dual-termination resistor circuit.
Noninverting and inverting VML differential output for CH 1 and CH 2. These pins
connect internally to voltage bias via termination resistors.
POWER
(1)
4
Internally biased to VCC / 2 with >200-kΩ pullup or pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be
<1 µA; otherwise, drive to VCC / 2 to assert mid-level state.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Voltage range
MIN
MAX
UNIT
Supply voltage range (2)
–0.5
4
V
Differential I/O
–0.5
4
V
Control I/O
–0.5
VCC + 0.5
V
See Power Dissipation
Characteristics
Continuous power dissipation
Tstg
(1)
(2)
Storage temperature
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±10000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine model
(1)
(2)
(3)
(3)
UNIT
V
±200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested in accordance with JEDEC Standard 22, Test Method A115-A.
6.3 Recommended Operating Conditions
typical values for all parameters are VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design
VCC
Supply voltage
CCOUPLING
Coupling capacitor
MIN
NOM
MAX
3
3.3
3.6
UNIT
V
12
Operating free-air temperature
0
nF
85
°C
6.4 Thermal Information
SN75LVCP601
THERMAL METRIC (1)
RTJ (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
38
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40
°C/W
RθJB
Junction-to-board thermal resistance
10
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
0.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
15.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
5
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
215
288
mW
5
mW
DEVICE PARAMETERS
PD
Power dissipation in active mode
DEWx = EN = VCC, EQx = DEx = NC, K28.5
pattern at 6 Gbps, VID = 700 mVp-p
PSD
Power dissipation in standby
mode
EN = 0 V, DEWx = EQx = DEx = NC, K28.5
pattern at 6 Gbps, VID = 700 mVp-p
ICC
Active-mode supply current
EN = 3.3 V, DEWx = 0 V, EQx = DEx = NC,
K28.5 pattern at 6 Gbps, VID = 700 mVp-p
65
80
mA
ICC_ALP
Acive power-save mode ICC
When device is enabled and auto low-power
conditions are met
6.5
10
mA
ICC_STDBY
Standby mode supply current
EN = 0 V
Maximum data rate
1
mA
1
6
Gbps
78
OUT-OF-BAND (OOB)
VOOB
Input OOB threshold
150
mVpp
DVdiffOOB
OOB differential delta
f = 750 MHz
50
25
mV
DVCMOOB
OOB common-mode delta
50
mV
CONTROL LOGIC
VIH
Input high voltage
VIL
Input low voltage
VINHYS
Input hysteresis
IIH
High-level input current
IIL
Low-level input current
For all control pins
1.4
V
0.5
115
mV
EQx, DEx = VCC
30
EN, DEWx = VCC
1
EQx, DEx = GND
–30
EN, DEWx = GND
–10
V
µA
µA
RECEIVER AC/DC
ZDIFFRX
Differential-input impedance
85
ZSERX
Single-ended input impedance
40
VCMRX
Common-mode voltage
RLDiffRX
RXDiffRLSlope
RLCMRX
VdiffRX
IBRX
6
Common-mode return loss
Differential input voltage PP
Impedance balance
115
f = 150 MHz to 300 MHz
18
28
f = 300 MHz to 600 MHz
14
17
f = 600 MHz to 1.2 GHz
10
12
f = 1.2 GHz to 2.4 GHz
8
9
f = 2.4 GHz to 3 GHz
3
f = 300 MHz to 6 GHz (see Figure 1)
dB
9
5
10
f = 300 MHz to 600 MHz
5
17
f = 600 MHz to 1.2 GHz
2
23
f = 1.2 GHz to 2.4 GHz
1
16
f = 2.4 GHz to 3 GHz
1
12
120
dB/dec
dB
1600
f = 150 MHz to 300 MHz
30
41
f = 300 MHz to 600 MHz
30
38
f = 600 MHz to 1.2 GHz
20
32
f = 1.2 GHz to 2.4 GHz
10
26
f = 2.4 GHz to 3 GHz
10
25
f = 3 GHz to 5 GHz
4
20
f = 5 GHz to 6.5 GHz
4
17
Submit Documentation Feedback
V
–13
f = 150 MHz to 300 MHz
f = 1.5 GHz and 3 GHz
Ω
Ω
1.8
Differential-mode return loss (RL)
Differential-mode RL slope
100
mVppd
dB
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
122
Ω
TRANSMITTER AC/DC
ZdiffTX
Pair differential impedance
85
ZSETX
Single-ended impedance
40
VTXtrans
Sequencing transient voltage
RLDiffTX
TXDiffRLSlope
RLCMTX
IBTX
DE
DiffVppTX_DE
VCMAC_TX
Differential-mode return loss
Differential-mode RL slope
Common-mode return loss
Impedance balance
Output de-emphasis (relative to
transition bit)
Differential output-voltage swing
dc level
TX AC CM voltage
VCMTX
Common-mode voltage
TxR/FImb
TX rise-fall imbalance
TxAmpImb
TX amplitude imbalance
Transient voltages on the serial data bus
during power sequencing (lab load)
Ω
–1.2
1.2
f = 150 MHz to 300 MHz
14
24
f = 300 MHz to 600 MHz
8
19
f = 600 MHz to 1.2 GHz
6
14
f = 1.2 GHz to 2.4 GHz
6
10
f = 2.4 GHz to 3 GHz
3
10
f = 300 MHz to 3 GHz (see Figure 1)
dB
–13
f = 150 MHz to 300 MHz
5
20
f = 300 MHz to 600 MHz
5
19
f = 600 MHz to 1.2 GHz
2
17
f = 1.2 GHz to 2.4 GHz
1
12
f = 2.4 GHz to 3.0 GHz
1
11
f = 150 MHz to 300 MHz
30
41
f = 300 MHz to 600 MHz
30
38
f = 600 MHz to 1.2 GHz
20
33
f = 1.2 GHz to 2.4 GHz
10
24
f = 2.4 GHz to 3 GHz
10
26
f = 3 GHz to 5 GHz
4
22
f = 5 GHz to 6.5 GHz
4
21
f = 3 GHz, DE1 or DE2 = 0
0
f = 3 GHz, DE1 or DE2 = 1
–2
f = 3 GHz, DE1 or DE2 = NC
–4
f = 3 GHz, DE1 or DE2 = 0
550
f = 3 GHz, DE1 or DE2 = 1
830
f = 3 GHz, DE1or DE2 = NC
630
V
dB/dec
dB
dB
dB
mV
At 1.5 GHz
20
50
mVppd
At 3 GHz
12
26
At 6 GHz
13
30
dBmV
(rms)
At 3 Gbps
6%
20%
2%
10%
1.8
V
6.6 Power Dissipation Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PD
Device power dissipation in active mode
PSD
Device power dissipation under standby mode
MIN
MAX
UNIT
215
288
mW
5
mW
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
7
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
6.7 Timing Requirements
MIN
NOM
MAX
UNIT
80
105
130
µs
42
50
ns
DEVICE PARAMETERS
AutoLPENTRY
Auto low-power entry time
Electrical idle at input (see Figure 4)
AutoLPEXIT
Auto low-power exit time
After first signal activity (see Figure 4)
TRANSMITTER AC/DC
tDE
De-emphasis duration
DEW1 or DEW2 = 0
94
DEW1 or DEW2 = 1
215
ps
OUT-OF-BAND (OOB)
tOOB1
OOB mode enter
See Figure 4
3
5
ns
tOOB2
OOB mode exit
See Figure 4
3
5
ns
TYP
MAX
UNIT
323
400
ps
6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
DEVICE PARAMETERS
tPDelay
Propagation delay
Measured using K28.5 pattern (see Figure 2)
tENB
Device enable time
EN 0 → 1
5
µs
tDIS
Device disable time
EN 1 → 0
2
µs
75
ps
30
ps
55
75
ps
6
20
ps
RECEIVER AC/DC
t20-80RX
tskewRX
Rise/fall time
Rise times and fall times measured between 20%
and 80% of the signal. SATA 6-Gbps speed
measured 1 in, (2.5 cm) from device pin.
Differential skew
Difference between the single-ended midpoint of
the RX+ signal rising or falling edge, and the
single-ended midpoint of the RX– signal falling or
rising edge.
62
TRANSMITTER AC/DC
t20-80TX
Rise/fall time
Rise times and fall times measured between 20%
and 80% of the signal. At 6 Gbps under no load
conditions.
tskewTX
Differential skew
Difference between the single-ended mid-point of
the TX+ signal rising or falling edge, and the
single-ended mid-point of the TX– signal falling or
rising edge.
42
TRANSMITTER JITTER
DJTX
Deterministic jitter (1) at CP in
Figure 9
VID = 500 mVpp, UI = 333 ps,
K28.5 control character
0.06
0.07
RJTX
Residual random jitter (1)
VID = 500 mVpp, UI = 333 ps,
K28.7 control character
0.01
2
DJTX
Deterministic jitter (1) at CP in
Figure 9
VID = 500 mVpp, UI = 167 ps,
K28.5 control character
0.08
0.16
RJTX
Residual random jitter (1)
VID = 500 mVpp, UI = 167 ps,
K28.7 control character
0.09
2
(1)
8
UIp-p
ps-rms
UIp-p
ps-rms
TJ = (14.1 × RJSD + DJ), where RJSD is one standard deviation value of RJ Gaussian distribution. Jitter measurement is at the SATA
connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect as shown
in Figure 9.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
IN+
50 mV
Vcm
IN-
tOOB2
tOOB1
OUT+
Vcm
OUT-
Figure 1. TX, RX Differential Return Loss Limits
Figure 2. OOB Enter and Exit Timing
IN
tPDelay
tPDelay
OUT
Figure 3. Propagation Delay Timing Diagram
RX1,2P
VCMRX
RX1,2N
tOOB1
AutoLPEXIT
TX1,2P
VCMTX
TX1,2N
AutoLPENTRY
Power Saving
Mode
Figure 4. Auto Low-Power Mode Enter and Exit Timing
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
9
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
1-bit
1 to N bits
1 to N bits
1-bit
tDE
0 dB
-2 dB
-4 dB
DiffVppTX_DE
DiffVppTX
tDE
Figure 5. TX Differential Output
6.9 Typical Characteristics
0.8
40
12
0.7
35
8
0.5
6
0.4
4
0.3
2
0
2
4
6
8
10
12
14
Input Trace Length (in)
16
Residual DJ (ps)
0.6
Eye Opening (V)
Residual DJ (ps)
10
Residual DJ 3Gbps
Residual DJ 6Gbps 0.2
Eye Opening 3Gbps
Eye Opening 6Gbps
0.1
18
20
22
0.8
Residual DJ 3Gbps
Residual DJ 6Gbps
Eye Opening 3Gbps
Eye Opening 6Gbps
0.7
30
0.6
25
0.5
20
0.4
15
0.3
10
0.2
5
0.1
0
2
4
6
8
10
12
14
Output Trace Length (in)
16
18
20
10
0
22
G002
G001
Figure 6. Residual DJ and Eye Opening
vs Input Trace Length
Eye Opening (V)
14
Figure 7. Residual DJ and Eye Opening
vs Output Trace Length
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
7 Parameter Measurement Information
•
•
Input signal characteristics
– Data rate = 6 Gbps, 3 Gbps, 1.5 Gbps
– Amplitude = 500 mVp-p
– Data pattern = K28.5
SN75LVCP601 device setup
– Temperature = 25°C
– Voltage = 3.3 V
– De-emphasis duration = 117 ps (short)
– Equalization and de-emphasis set to optimize performance at 6 Gbps
With LVCP601
Agilent
ParBERT
16-in., 4-mil (40.6-cm, 0.101-mm)
FR4 Trace +
2-in., 9.5-mil (5.05-cm, 0.241-mm)
FR4 Trace
LVCP601
8-in., 4-mil (20.3-cm, 0.101-mm)
FR4 Trace +
2-in., 9.5-mil (5.05-cm, 0.241-mm)
FR4 Trace
TP4
TP3
TP2
TP1
Agilent
DCA -J
EQ = 14 dB
DE = –2 dB
Without LVCP601
16-in., 4-mil (40.6-cm, 0.101-mm) FR4 Trace +
4-in., 9.5-mil (10.1-cm, 0.241-mm) FR4 Trace +
8-in., 4-mil (20.3-cm, 0.101-mm) FR4 Trace
Agilent
ParBERT
Agilent
DCA -J
TP1
TP4
Figure 8. Performance Curve Measurement Setup
Jitter
Measurement
CP
8" 6 mil Stripline
12" 6mil
Stripline
1
AWG*
2
CP
AWG*
CP = Compliance point
Jitter
Measurement
Figure 9. Jitter Measurement Test Condition
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
11
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
7.1 Jitter and VOD Results: Case 1 at 6 Gbps
TJ
(1e-12)
ps
29.0
DJ
(σ-σ)
ps
3.3
RJ
(rms)
ps
1.88
Eye
Amplitude
mv
412.4
Eye
Width
ps
159.2
Eye
Opening
mv
350.52
TJ
(1e-12)
ps
91.8
DJ
(σ-σ)
ps
65.4
Figure 10. Test Point 1
TJ
(1e-12)
ps
42.0
DJ
(σ-σ)
ps
15.9
RJ
(rms)
ps
1.91
Eye
Amplitude
mv
788.8
12
Eye
Amplitude
mv
240
Eye
Width
ps
28.9
Eye
Opening
mv
81.24
Figure 11. Test Point 2
Eye
Width
ps
141.3
Figure 12. Test Point 3
RJ
(rms)
ps
1.93
Eye
Opening
mv
623.02
TJ
(1e-12)
ps
39.0
DJ
(σ-σ)
ps
12.7
RJ
(rms)
ps
1.92
Eye
Amplitude
mv
557.1
Eye
Width
ps
149.7
Eye
Opening
mv
459.62
Figure 13. Test Point 4 With LVCP601
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
Jitter and VOD Results: Case 1 at 6 Gbps (continued)
TJ
(1e-12)
ps
56.7
DJ
(σ-σ)
ps
29.8
RJ
(rms)
ps
2.00
Eye
Amplitude
mv
165.4
Eye
Width
ps
101
Eye
Opening
mv
13.24
Figure 14. Test Point 5 Without LVCP601
7.2 Jitter and VOD Results: Case 2 at 3 Gbps
TJ
(1e-12)
ps
29.7
DJ
(σ-σ)
ps
3.8
RJ
(rms)
ps
1.89
Eye
Amplitude
mv
430.9
Eye
Width
ps
326
Eye
Opening
mv
392.84
TJ
(1e-12)
ps
72.7
DJ
(σ-σ)
ps
46.8
Figure 15. Test Point 1
RJ
(rms)
ps
1.89
Eye
Amplitude
mv
314.9
Eye
Width
ps
237
Eye
Opening
mv
222.36
Figure 16. Test Point 2
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
13
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
Jitter and VOD Results: Case 2 at 3 Gbps (continued)
TJ
(1e-12)
ps
39.6
DJ
(σ-σ)
ps
12.8
RJ
(rms)
ps
1.96
Eye
Amplitude
mv
714.5
Eye
Width
ps
321
Eye
Opening
mv
611.62
TJ
(1e-12)
ps
47.9
Figure 17. Test Point 3
TJ
(1e-12)
ps
128.6
DJ
(σ-σ)
ps
101.8
DJ
(σ-σ)
ps
20.3
RJ
(rms)
ps
1.99
Eye
Amplitude
mv
615.3
Eye
Width
ps
305.0
Eye
Opening
mv
463.42
Figure 18. Test Point 4 With LVCP601
RJ
(rms)
ps
1.96
Eye
Amplitude
mv
258.8
Eye
Width
ps
118
Eye
Opening
mv
122.26
Figure 19. Test Point 5 Without LVCP601
14
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
7.3 Jitter and VOD Results: Case 3 at 1.5 Gbps
TJ
(1e-12)
ps
34.3
DJ
(σ-σ)
ps
3.4
RJ
(rms)
ps
2.26
Eye
Amplitude
mv
448
Eye
Width
ps
659
Eye
Opening
mv
417.28
TJ
(1e-12)
ps
67.5
DJ
(σ-σ)
ps
38.6
DJ
(σ-σ)
ps
13.2
RJ
(rms)
ps
2.31
Eye
Amplitude
mv
753.1
Eye
Width
ps
649
Figure 22. Test Point 3
Eye
Amplitude
mv
363.4
Eye
Width
ps
589
Eye
Opening
mv
318.48
Figure 21. Test Point 2
Figure 20. Test Point 1
TJ
(1e-12)
ps
44.9
RJ
(rms)
ps
2.11
Eye
Opening
mv
604.02
TJ
(1e-12)
ps
57.3
DJ
(σ-σ)
ps
21.5
RJ
(rms)
ps
2.62
Eye
Amplitude
mv
672.8
Eye
Width
ps
632.0
Eye
Opening
mv
442.42
Figure 23. Test Point 4 With LVCP601
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
15
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
Jitter and VOD Results: Case 3 at 1.5 Gbps (continued)
TJ
(1e-12)
ps
113.3
DJ
(σ-σ)
ps
81.9
RJ
(rms)
ps
2.30
Eye
Amplitude
mv
322.8
Eye
Width
ps
493
Eye
Opening
mv
217.46
Figure 24. Test Point 5 Without LVCP601
16
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
8 Detailed Description
8.1 Overview
The SN75LVCP601 device is a dual-channel, single-lane SATA redriver and signal conditioner supporting data
rates up to 6 Gbps.
This device complies with SATA physical link 2m and 3i specifications. The SN75LVCP601 device is designed to
handle interconnect losses at both its input and output. The input stage of each channel offers selectable
equalization settings that can be programmed to match the loss of the channel. The outputs provide selectable
de-emphasis to compensate for the distortion the SATA signal is expected to experience. The level of
equalization and de-emphasis settings depend on the length of interconnect and it’s characteristics. Equalization
for input trace and output trace are individually controlled by the setting of EQ1 and EQ2. De-emphasis levels for
input and output trace are individually controlled by the setting of DE1, DE2, DEW1 and DEW2 pins.
8.2 Functional Block Diagram
GND[3,13,18]
VBB = 1.7 V TYP
RT
RX1P [1]
TX1P [15]
Driver
Equalizer
RT
RX1N [2]
TX1N [14]
OOB
Detect
VBB
SN75LVCP601
RT
RX2N [12]
Driver
Equalizer
TX2N [4]
RT
RX2P [11]
OOB
Detect
TX2P [5]
DEW1 [16]
CTRL
DEW2 [6]
EQ1[17]
DE1[9]
VCC[10,20]
EQ2[19]
DE2[8]
EN[7]
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Data Flow Block Diagram
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
17
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
8.3 Feature Description
8.3.1 Input Equalization
Each differential input of the SN75LVCP601 device has programmable equalization in its front stage. Table 1
lists the equalization. The input equalizer design recovers a signal even when no eye is present at the receiver,
and effectively supports FR4 trace at the input anywhere from 4 in. (10.2 cm) to 20 in. (50.8 cm) at SATA 6G
speed.
8.3.2 Output De-Emphasis
The SN75LVCP601 device provides the de-emphasis settings shown in Table 1. De-emphasis control is
independent for each channel, controlled by the DE1 and DE2 pin settings as shown in Table 1. The reference
for the de-emphasis settings available in the device is the transition bit amplitude for each given configuration;
this transition bit amplitude is different at 0 dB than the –2-dB and –4-dB settings by design. DEW1 and DEW2
control the DE durations for channels one and two, respectively. Table 1 lists the recommended settings for
these control pins. Output de-emphasis is capable of supporting FR4 trace at the output anywhere from
2 in. (5.1 cm) to 12 in. (30.5 cm) at SATA 3G/6G speed.
Table 1. TX and RX EQ and DE Pulse-Duration Settings
DE1 OR DE2
CH1 OR CH2
DE-EMPHASIS
dB (at 6 Gbps)
EQ1 OR EQ2
CH1 OR CH2 Equalization
dB (at 6 Gbps)
NC (default)
–4
NC (default)
0
0
0
0
7
1
–2
1
14
DEVICE FUNCTION → DE WIDTH FOR CH1/CH2
DEW1 OR DEW2
0
De-emphasis pulse duration, short
1 (default)
De-emphasis pulse duration, long
8.3.3 Out-of-Band (OOB) Support
The squelch detector circuit within the device enables full detection of OOB signaling as specified in the SATA
specification. The device does not detect differential signal amplitude at the receiver input of 50 mVpp or less an
activity, and hence does not passed it to the output. The device detects differential signal amplitude of
150 mVp-p or more as an activity and therefore passes it to the output, providing an indication of the activity.
Squelch circuit ON or OFF time is 5 ns, maximum. While in squelch mode, outputs are held to VCM.
8.4 Device Functional Modes
8.4.1 Low-Power Mode
There are two low-power modes supported by the SN75LVCP601 device, listed as follows:
1. Standby mode (triggered by the EN pin, EN = 0 V)
– The enable (EN) pin controls th low-power mode. Pulling this pin LOW puts the device in standby mode
within 2 µs (max). In this mode, the device drives all its active components to their quiescent level, and
differential outputs Hi-Z (open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode
to normal operation requires a maximum latency of 5 µs.
2. Auto low-power mode (triggered when a given channel is in the electrically idle state for more than 100 µs
and EN = VCC)
– The device enters and exits low-power mode by actively monitoring the input signal (VIDp-p) level on
each of its channels independently. When the input signal on either or both channels is in the electrically
idle state, that is, VIDp-p < 50 mV and stays in this state for >100 µs, the associated channel enters into
the low-power state. In this state, output of the associated channel goes to VCM and the device
selectively shuts off some circuitry to lower power by >80% of its normal operating power. Exit time from
the auto low-power mode is <50 ns.
18
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN75LVCP601 is a dual-channel SATA redriver and signal conditioner supporting data rates of 6 Gbps. The
inputs incorporate an OOB (out-of-band) detector, which automatically squelches the output while maintaining a
stable common-mode voltage compliant to the SATA link.
R = SN75LVCP601
ICH
Notebook
Dock Connector
HDD
R
eSATA
connector
eSATA Cable
(2m)
Dock
Notebook Dock
Figure 26. Typical SN75LVCP601 Placement in the System
9.2 Typical Application
This typical application describes how to configure the EQ, DE, and DEW configuration pins of the
SN75LVCP601 device based on board trace length between the SATA Host and the SN75LVCP601 and the
SN75LVCP601 and SATA Device. Actual configuration settings may differ due to additional factors such as
board layout, trace widths, and connectors used in the signal path.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
19
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
DEW1
1.0 mF
16
17
18
RX1P
TX1P
15
2
RX1N
TX1N
14
3
LVCP 601 RTJ
13
10 nF
4
TX2N
RX2N
12
5
TX2P
RX2P
11
8
7
DE1 9
DE2
EN
DEW2
6
10 nF
10 nF
SATA
Connector
10 nF
10 nF
1
Vcc 10
10 nF
19
20
Vcc
SATA Host
10 nF
1.0 mF
3.3 V
1.0 mF
EQ1
EQ2
Typical Application (continued)
10 nF
Copyright © 2016, Texas Instruments Incorporated
(1)
Place supply capacitors close to device pin.
(2)
With no external control is implemented, one can leave EN open or tie it to the supply .
(3)
Output de-emphasis setting is for –2 dB, EQ for 7 dB, and DE duration for SATA I/II/III operation for both channels.
(4)
Actual EQ/DE duration settings depend on device placement relative to host and SATA connector.
Figure 27. Typical Device Implementation
9.2.1 Design Requirements
Typically, system trace length from the SATA host to the SN75LVCP601 device and trace length from the
SN75LVCP601 device to a SATA device differ and require different equalization and de-emphasis settings for
the host side and device side.
For example:
• A system with a 6-inch trace from the SN75LVCP601 device to a SATA host may set EQ1 (Rx1±) to 7 dB,
and DE2 (Tx2±) to –2 dB and DEW2 (Tx2±) to long pulse duration.
• The same system with a 1-inch trace from the SN75LVCP601 device to a SATA HDD may set EQ2 (Rx2±) to
0 dB, and DE1 (Tx1±) to 0 dB and DEW1 (Tx1±) to short pulse duration.
Refer to Application Curves for recommended EQ, DE and DEW settings based on trace length. It is highly
recommended to add both pullup- and pulldown-resistor options in the layout to fine-tune the settings if needed.
Input Signal Characteristics:
• Data Rate: 6 Gbps
• Pattern: PRBS7
• No pre-emphasis
• Signal amplitude: 500 mVp-p
• 18-inch SMA cable from test equipment to input and output trace
20
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
Typical Application (continued)
Input
Output
SN75LVCP601
Lecroy PERT3
25-GHz Scope
TP2
TP1
TP3
TP4
Figure 28. Measurement Set-up
9.2.2 Detailed Design Procedure
9.2.2.1 Equalization Configuration
Each differential input of the SN75LVCP601 device has programmable equalization in the front stage. The
equalization setting is shown in Table 2. The input equalizer is designed to recover a signal even when no eye is
present at the receiver and effectively supports FR4 trace input from 3 inches to greater than 24 inches at
SATA 6 Gbps speed.
Table 2. Equalization Settings
EQ1, EQ2
CH1, CH2 EQUALIZATION dB (AT 6 Gbps)
NC
0
0
7
1
14
9.2.2.2 De-emphasis Configuration
The SN75LVCP601 device provides the de-emphasis settings shown in Table 3. De-emphasis is controlled
independently for each channel and is set by the DE1, DE2, DEW1 and DEW2 pins of the SN75LVCP601
device. The recommended settings for these pins are listed in Application Curves. Output de-emphasis is
capable of supporting FR4 trace lengths at the output from 3 inches to 12+ inches at SATA 6 Gbps speed.
Table 3. De-emphasis Settings
DE1, DE2
CH1, CH2 DE-EMPHASIS dB (AT 6 Gbps)
0
0
1
–2
NC
–4
Table 4. DE Width Control
DEW1, DEW2
DE-EMPHASIS WIDTH FOR CH1, CH2
0
Short de-emphasis pulse duration
1
Long de-emphasis pulse duration
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
21
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
9.2.3 Application Curves
9.2.3.1 SN75LVCP601 Equalization Settings For Various Input Trace Lengths
Input Trace Length = 3 in.
EQ1, EQ2 Setting = NC (0 dB)
Figure 29. Input Eye (TP2)
Input Trace Length = 3 in.
EQ1, EQ2 Setting = NC (0 dB)
Figure 30. Output Eye (TP4)
Input Trace Length = 6 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 31. Input Eye (TP2)
Input Trace Length = 6 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 32. Output Eye (TP2)
Input Trace Length = 12 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 33. Input Eye (TP2)
Input Trace Length = 12 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 34. Output Eye (TP2)
22
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
Input Trace Length = 24 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 35. Input Eye (TP2)
Input Trace Length = 24 in.
EQ1, EQ2 Setting = 0 (7 dB)
Figure 36. Output Eye (TP2)
Input Trace Length = 36 in.
EQ1, EQ2 Setting = 1 (14 dB)
Figure 37. Input Eye (TP2)
Input Trace Length = 36 in.
EQ1, EQ2 Setting = 1 (14 dB)
Figure 38. Output Eye (TP2)
Input Trace Length = 48 in.
EQ1, EQ2 Setting = 1 (14 dB)
Figure 39. Input Eye (TP2)
Input Trace Length = 36 in.
EQ1, EQ2 Setting = 1 (14 dB)
Figure 40. Output Eye (TP2)
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
23
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
9.2.3.2 SN75LVCP601 De-emphasis Settings For Various Output Trace Lengths
Output Trace Length = 0 in.
DE1, DE2 Setting = 0 (0 dB)
DEW1, DEW2 Setting = 0 (Short pulse duration)
Figure 41. Output Eye (TP4)
Output Trace Length = 3 in.
DE1, DE2 Setting = 0 (0 dB)
DEW1, DEW2 Setting = 0 (Short pulse duration)
Figure 42. Output Eye (TP4)
Output Trace Length = 6 in.
DE1, DE2 Setting = 1 (–2 dB)
DEW1, DEW2 Setting = 1 (Long pulse duration)
Figure 43. Output Eye (TP4)
Output Trace Length = 12 in.
DE1, DE2 Setting = 1 (–2 dB)
DEW1, DEW2 Setting = 1 (Long pulse duration)
Figure 44. Output Eye (TP4)
Output Trace Length = 12 in.
DE1, DE2 Setting = NC (–4 dB
DEW1, DEW2 Setting = 1 (Long pulse duration)
Figure 45. Output Eye (TP4)
24
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
10 Power Supply Recommendations
The design of SN75LVCP601 device is for operation from one 3.3-V supply. Always practice proper powersupply sequencing procedure. Apply VCC first, before application of any input signals to the device. The powerdown sequence is in reverse order.
11 Layout
11.1 Layout Guidelines
24 in. (61 cm)
Redriver
SATA Host
SATA
Connector
8 in.
(20.3 cm)
16 in. (40.6 cm)
Redriver on Motherboard
24 in. (61 cm)
SATA Host
Redriver
Main Board
Dock Board
16 in. (40.6 cm)
SATA
Connector
8 in.
(20.3 cm)
Redriver on Dock Board
Example: Suggested trace-length values are values based on TI spice simulations (done over programmable limits of
input EQ and output de-emphasis) to meet SATA loss and jitter specification.
Actual trace length supported by the LVCP601 may be more or less than suggested values and depends on board
layout, trace widths, and number of connectors used in the SATA signal path.
Figure 46. Trace Length Example for LVCP601
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
25
SN75LVCP601
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
www.ti.com
11.2 Layout Example
HIGH SPEED TRACES
LENGTH MATCHING
Figure 47. SN65LVCP601 EVM
26
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
SN75LVCP601
www.ti.com
SLLSE41H – JUNE 2010 – REVISED MARCH 2016
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP601
27
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN75LVCP601RTJR
ACTIVE
QFN
RTJ
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
0 to 85
LVC601
SN75LVCP601RTJT
ACTIVE
QFN
RTJ
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
0 to 85
LVC601
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN75LVCP601RTJR
QFN
RTJ
20
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
SN75LVCP601RTJT
QFN
RTJ
20
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN75LVCP601RTJR
QFN
RTJ
20
3000
367.0
367.0
35.0
SN75LVCP601RTJT
QFN
RTJ
20
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising