Texas Instruments | TPD2E001 Low-Capacitance 2-Channel ESD-Protection for High-Speed Data Interfaces (Rev. I) | Datasheet | Texas Instruments TPD2E001 Low-Capacitance 2-Channel ESD-Protection for High-Speed Data Interfaces (Rev. I) Datasheet

Texas Instruments TPD2E001 Low-Capacitance 2-Channel ESD-Protection for High-Speed Data Interfaces (Rev. I) Datasheet
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TPD2E001
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TPD2E001 Low-Capacitance 2-Channel ESD-Protection for High-Speed Data Interfaces
1 Features
3 Description
•
The TPD2E001 is a two-channel Transient Voltage
Suppressor (TVS) based Electrostatic Discharge
(ESD) protection diode array. The TPD2E001 is rated
to dissipate ESD strikes at the maximum level
specified in the IEC 61000-4-2 Level 4 international
standard.
1
•
•
•
•
•
•
IEC 61000-4-2 ESD Protection (Level 4)
– ±8-kV Contact Discharge
– ±15-kV Air-Gap Discharge
IO Capacitance: 1.5 pF (Typ)
Low Leakage Current: 1 nA (Maximum)
Low Supply Current: 1 nA
0.9 V to 5.5 V Supply-Voltage Range
Space-Saving DRL, DRY, and QFN Package
Options
Alternate 3, 4, 6-Channel options Available:
TPD3E001, TPD4E001, TPD6E001
The DRS package (3.00 mm x 3.00 mm) is also
available as a non-magnetic package for medical
imaging applications.
See also TPD2E2U06DRLR which is p2p compatible
to TPD2E001DRLR and offers higher IEC ESD
Protection, lower clamping voltage, and eliminates
the input capacitor requirement.
2 Applications
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
USB 2.0
Ethernet
FireWire™
LVDS
SVGA Video Connections
Glucose Meters
Medical Imaging
TPD2E001
PACKAGE
BODY SIZE (NOM)
SOT (5)
1.60 mm x 1.20 mm
WSON (6)
3.00 mm x 3.00 mm
USON (6)
1.45 mm x 1.00 mm
SOP (4)
2.90 mm x 1.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Schematic
VCC
0.1 µF
VBUS
RT
IO1
D+
USB
Controller
RT
D1
D–
IO2
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD2E001
SLLS684I – JULY 2006 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
ESD Ratings: Surge Protection.................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagram ......................................... 6
7.3 Feature Description................................................... 6
7.4 Device Functional Modes.......................................... 6
8
Application and Implementation .......................... 7
8.1 Application Information.............................................. 7
8.2 Typical Application .................................................... 7
9 Power Supply Recommendations........................ 8
10 Layout..................................................................... 8
10.1 Layout Guidelines ................................................... 8
10.2 Layout Example ...................................................... 8
11 Device and Documentation Support ................... 9
11.1
11.2
11.3
11.4
Community Resources............................................
Trademarks .............................................................
Electrostatic Discharge Caution ..............................
Glossary ..................................................................
9
9
9
9
12 Mechanical, Packaging, and Orderable
Information ............................................................. 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (August 2014) to Revision I
Page
•
Updated the ESDS section .................................................................................................................................................... 1
•
Updated the Handling Ratings table to an ESD Ratings table and moved the Tstg to the Absolute Maximum Ratings
table ........................................................................................................................................................................................ 4
•
Added test condition frequency to capacitance ..................................................................................................................... 5
•
Added note to the Application and Implementation ............................................................................................................... 7
•
Added Community Resources ............................................................................................................................................... 9
Changes from Revision G (November 2013) to Revision H
•
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision F (Feburary 2012) to Revision G
Page
•
Updated document formatting. ............................................................................................................................................... 1
•
Updated Description. .............................................................................................................................................................. 1
•
Removed Ordering Information table. .................................................................................................................................... 3
Changes from Revision E (June 2008) to Revision F
Page
•
Added Medical Imaging to Applications.................................................................................................................................. 1
•
Added "The 3x3 mm DRS package is also available as a non-magnetic package for medical imaging application." to
the description. ....................................................................................................................................................................... 1
•
Added 3 x 3 SON – DRS (Non-Magnetic) package to Ordering Information table. ............................................................... 3
2
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5 Pin Configuration and Functions
DRY Package
6-Pin USON
Top View
DRS Package
6-Pin WSON
Top View
VCC
1
6
IO2
N.C.
2
5
N.C.
VCC
1
IO1
3
4
GND
N.C.
2
IO1
3
N.C. – Not internally connected
1
N.C.
2
3
5
N.C.
4
GND
5
IO2
4
GND
DZD Package
4-Pin SOP
Top View
GND
IO1
IO2
N.C. – Not internally connected
DRL Package
5-Pin SOT
Top View
VCC
GND
6
N.C. – Not internally connected
IO1
1
4
2
3
VCC
IO2
Pin Functions
PIN
DESCRIPTION
DRY
NO.
DRL
NO.
DRS
NO.
DZD
NO.
EP
—
—
EP
—
Exposed pad. Connect to GND.
GND
4
4
4
1
Ground
IOx
3, 6
3, 5
3, 6
2, 3
N.C.
2, 5
2
2, 5
—
No connection. Not internally connected.
VCC
1
1
1
4
Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor.
NAME
ESD-protected channel
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Power pin voltage
–0.3
7
V
VIO
IO pin voltage
–0.3
VCC + 0.3
V
TJ
Junction temperature
150
°C
Bump temperature (soldering)
Infrared (15 s)
220
Vapor phase (60 s)
215
Lead temperature (soldering, 10 s)
Tstg
(1)
Storage temperature
–65
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±15000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: Surge Protection
VALUE
Electrostatic
discharge
V(ESD)
IEC 61000-4-2 contact
±8000
IEC 61000-4-2 air-gap discharge
±15000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TA, operating free-air temperature
–40
85
0.9
5.5
0
VCC
VCC pin
Operating voltage
MAX
IO1, IO2 pins
UNIT
°C
V
6.5 Thermal Information
TPD2E001
THERMAL METRIC
(1)
DRY (USON)
DRL (SOT)
DRS (WSON)
DZD (SOP)
5 PINS
5 PINS
6 PINS
4 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
374.2
257.6
91.9
213.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
223.4
97.6
106.9
93.5
°C/W
RθJB
Junction-to-board thermal resistance
227.8
74.2
64.8
56.8
°C/W
ψJT
Junction-to-top characterization parameter
52.9
7.5
10.2
4.2
°C/W
ψJB
Junction-to-board characterization parameter
224.8
73.7
64.9
56.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
87.5
N/A
29.9
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.6 Electrical Characteristics
VCC = 5 V ± 10%, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
Supply voltage
ICC
Supply current
VF
Diode forward voltage
IF = 10 mA
VBR
Breakdown voltage
IBR = 10 mA
VC
TYP (1)
MAX
5.5
V
1
100
nA
0.95
V
0.9
Channel clamp voltage (2)
0.65
UNIT
11
TA = 25°C, ±15-kV HBM,
IF = 10 A
Positive transients
TA = 25°C,
±8-kV contact discharge
(IEC 61000-4-2), IF = 24 A
Positive transients
TA = 25°C,
±15-kV air-gap discharge
(IEC 61000-4-2), IF = 45 A
Positive transients
V
VCC + 25
Negative transients
–25
VCC + 60
Negative transients
Channel leakage current
VI/O = GND to VCC
CIO
Channel input capacitance
VCC = 5 V, bias of VCC / 2; ƒ = 10 MHz
V
–60
VCC + 100
Negative transients
IIO
(1)
(2)
MIN
–100
–1
1
nA
1.5
pF
Typical values are at VCC = 5 V and TA = 25 °C
Channel clamp voltage is not production tested.
6.7 Typical Characteristics
1000
2.20
IO Leakage Current (pA)
IO Capacitance (pF)
2.00
1.80
1.60
1.40
1.20
100
10
1.00
0.00
1.00
2.00
2.50
3.00
4.00
1
–40
5.00
25
Figure 1. IO Capacitance vs IO Voltage (VCC = 5 V)
65
85
Figure 2. IO Leakage Current vs Temperature (VCC = 5 V)
14
12
12
10
10
8
Current (A)
Current (A)
45
Temperature (°C)
IO Voltage (V)
8
6
6
4
4
2
2
0
0
1
3
5
7
9
11
13
15
17
19
Voltage (V)
21
1
C003
Figure 3. TLP IO to GND (DRS Package)
2
3
4
5
6
7
8
Voltage (V)
Figure 4. TLP GND to IO (DRS Package)
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7 Detailed Description
7.1 Overview
The TPD2E001 is a two-channel transient voltage suppressor (TVS) based ESD protection diode array. The
TPD2E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 Level 4
international standard.
7.2 Functional Block Diagram
VCC
IO2
IO1
GND
7.3 Feature Description
TPD2E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a
central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD
clamp is also connected to VCC to provide protection for the VCC line. Each IO line is rated to dissipate ESD
strikes above the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD2E001's
low loading capacitance makes it ideal for protection high-speed signal terminals.
7.4 Device Functional Modes
TPD2E001 is a passive integrated circuit that activates whenever voltages above VBR or below the lower diodes
Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can
be directed to ground and VCC via the internal diode network. Once the voltages on the protected lines fall below
the trigger voltage of the TPD2E001 (usually within 10s of nanoseconds) the device reverts back to a high
impedance state.
6
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TPD2E001 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a path to
ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system.
As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is
the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a
tolerable level to the protected IC.
8.2 Typical Application
0.1 µF
VCC
VBUS
RT
IO1
D+
USB
Controller
RT
D1
D–
IO2
GND
GND
Figure 5. Typical USB Application Diagram
8.2.1 Design Requirements
For this design example, a single TPD2E001 is used to protect all pins of a USB 2.0 connector.
Given the USB application, Table 1 shows the Design Parameters:
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on IO1, and IO2
0 V to 5 V
Signal voltage range on VCC
0 V to 5 V
Operating frequency
240 MHz
8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer needs to know the following:
• Signal voltage range on all the protected lines
• Operating frequency
The VCC pin can be connected in two different ways:
1. If the VCC pin is connected to the system power supply, the TPD2E001 works as a transient suppressor for
any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD
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bypass.
2. If the VCC pin is not connected to the system power supply, the TPD2E001 can tolerate higher signal swing
in the range up to 10 V. Please note that a 0.1-μF capacitor is still recommended at the VCC pin for ESD
bypass.
8.2.2.1 Signal Range on IO1 and IO2 and VCC Pins
The TPD2E001 has 2 IO pins which support 0 to either 10 V or VCC + Vforward (depending on if the VCC pin is
connected to a VCC line or has a 0.1 µF capacitor to ground).
9 Power Supply Recommendations
This device is a passive ESD protection device and there is no need to power it. Care should be taken to make
sure that the maximum voltage specifications for each line are not violated.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
This application is typical of a differential data pair application, such a USB 2.0.
VCC
IO2
IO1
GND
= VIA to GND
Figure 6. Routing With DRL Package
8
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
FireWire is a trademark of Apple Computer, Inc.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPD2E001DRLR
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(2AR, 2AZ)
(2AH, 2AW)
TPD2E001DRLRG4
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(2AR, 2AZ)
(2AH, 2AW)
TPD2E001DRSR
ACTIVE
SON
DRS
6
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZWK
TPD2E001DRST-NM
ACTIVE
SON
DRS
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
ZWKNM
TPD2E001DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2A
TPD2E001DRYRG4
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2A
TPD2E001DZDR
ACTIVE
SOT-23
DZD
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFGO
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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28-Dec-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPD2E001 :
• Automotive: TPD2E001-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPD2E001DRLR
SOT-5X3
DRL
5
4000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.98
1.78
0.69
4.0
8.0
Q3
TPD2E001DRSR
SON
DRS
6
1000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPD2E001DRST-NM
SON
DRS
6
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPD2E001DRYR
SON
DRY
6
5000
180.0
9.5
1.2
1.65
0.7
4.0
8.0
Q1
TPD2E001DRYR
SON
DRY
6
5000
179.0
8.4
1.2
1.65
0.7
4.0
8.0
Q1
TPD2E001DZDR
SOT-23
DZD
4
3000
179.0
8.4
3.15
2.6
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD2E001DRLR
SOT-5X3
DRL
5
4000
183.0
183.0
20.0
TPD2E001DRSR
SON
DRS
6
1000
367.0
367.0
35.0
TPD2E001DRST-NM
SON
DRS
6
250
210.0
185.0
35.0
TPD2E001DRYR
SON
DRY
6
5000
189.0
185.0
36.0
TPD2E001DRYR
SON
DRY
6
5000
203.0
203.0
35.0
TPD2E001DZDR
SOT-23
DZD
4
3000
203.0
203.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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