Texas Instruments | SNx5HVD251 Industrial CAN Bus Transceiver (Rev. G) | Datasheet | Texas Instruments SNx5HVD251 Industrial CAN Bus Transceiver (Rev. G) Datasheet

Texas Instruments SNx5HVD251 Industrial CAN Bus Transceiver (Rev. G) Datasheet
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SN55HVD251, SN65HVD251
SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015
SNx5HVD251 Industrial CAN Bus Transceiver
1 Features
3 Description
•
The HVD251 is intended for use in applications
employing the Controller Area Network (CAN) serial
communication physical layer in accordance with the
ISO 11898 Standard. The HVD251 provides
differential transmit capability to the bus and
differential receive capability to a CAN controller at
speeds up to 1 megabits per second (Mbps).
1
•
•
•
•
•
•
•
•
•
•
(1)
Drop-In Improved Replacement for the
PCA82C250 and PCA82C251
Bus-Fault Protection of ±36 V
Meets or Exceeds ISO 11898
Signaling Rates(1) up to 1 Mbps
High Input Impedance Allows up to 120 Nodes on
a Bus
Bus Pin ESD Protection Exceeds 14 kV HBM
Unpowered Node Does Not Disturb the Bus
Low-Current Standby Mode: 200-µA Typical
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down CAN Bus
Protection for Hot-Plugging
DeviceNet Vendor ID #806
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in bps (bits
per second).
2 Applications
•
•
•
•
CAN Data Buses
Industrial Automation
SAE J1939 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
Block Diagram
VCC (3)
Overtemperature
Sensor
D 1
SLOPE
CONTROL and
MODE LOGIC
8
RS
7
CANH
VCC (3)
VCC/2
Designed for operation in harsh environments, the
device features cross-wire, overvoltage and loss of
ground protection to ±36 V. Also featured are
overtemperature protection as well as –7-V to 12-V
common-mode range, and tolerance to transients of
±200 V. The transceiver interfaces the single-ended
CAN controller with the differential CAN bus found in
industrial, building automation, and automotive
applications.
Rs, pin 8, selects one of three different modes of
operation: high-speed, slope control, or low-power
mode. The high-speed mode of operation is selected
by connecting pin 8 to ground, allowing the
transmitter output transistors to switch as fast as
possible with no limitation on the rise and fall slope.
The rise and fall slope can be adjusted by connecting
a resistor to ground at pin 8; the slope is proportional
to the pin's output current. Slope control with an
external resistor value of 10 kΩ gives about 15-V / µs
slew rate; 100 kΩ gives about 2-V/µs slew rate.
If a high logic level is applied to the Rs pin 8, the
device enters a low-current standby mode where the
driver is switched off and the receiver remains active.
The local protocol controller returns the device to the
normal mode when it transmits to the bus.
VREF (5)
Vcc (3)
Device Information(1)
GND 2
Driver
PART NUMBER
SN55HVD251
VCC 3
6
CANL
SN65HVD251
PACKAGE
BODY SIZE (NOM)
WSON (8)
4.00 mm × 4.00 mm
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
R 4
5
VREF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN55HVD251, SN65HVD251
SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
4
4
5
5
5
5
6
6
7
7
7
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Supply Current ..........................................................
Electrical Characteristics: Driver ...............................
Electrical Characteristics: Receiver ..........................
VREF-Pin Characteristics ........................................
Power Dissipation Characteristics ............................
Switching Characteristics: Driver ............................
Switching Characteristics: Device ...........................
Switching Characteristics: Receiver........................
Dissipation Ratings .................................................
Typical Characteristics ............................................
Parameter Measurement Information ................ 11
8
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
17
19
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 24
9.3 System Example ..................................................... 26
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (June 2015) to Revision G
•
Page
Changed the value of HBM "All pins" From: ±14000 V To: ±6000 V. Changed the value of "CANH, CANL and GND"
From: ±6000 V To: ±14000 V in the ESD Ratings ................................................................................................................. 4
Changes from Revision E (March 2010) to Revision F
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed the location of section "6.12 VREF-Pin Characteristics" to section 6.8 ................................................................. 6
Changes from Revision C (September 2005) to Revision D
Page
•
Added device SN55HVD251 .................................................................................................................................................. 1
•
Added the DRJ Package. ....................................................................................................................................................... 1
•
Changed the data sheet title From: CAN TRANSCEIVER To: INDUSTRIAL CAN TRANSCEIVER..................................... 1
•
Deleted APPLICATIONS bullets: DeviceNet™ Data Buses, Smart Distributed Systems (SDS™), and ISO 11783
Standard Data Bus Interface .................................................................................................................................................. 1
•
Deleted last paragraph from the DESCRIPTION - "The HVD251 may be used..."................................................................ 1
•
Added Electrical fast transient/burst to the Abs Max Ratings table........................................................................................ 4
•
Deleted the condition - over recommended operating conditions (unless otherwise noted). From the
RECOMMENDED OPERATING CONDITIONS table ............................................................................................................ 5
•
Added SN55HVD251 to the Operating free-air temperature, TA in the ROC table ................................................................ 5
•
Added DRJ to the Junction-to-case thermal resistance ......................................................................................................... 5
•
Added DRJ to the Junction-to-board thermal resistance........................................................................................................ 5
2
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SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015
•
Added the SUPPLY CURRENT table..................................................................................................................................... 5
•
Deleted ICC - Supply current from the DRIVER ELECTRICAL CHARACTERISTICS .......................................................... 5
•
Added T ≥ -40°C to VO(D) Test Conditions in the DRIVER ELECTRICAL CHARACTERISTICS .......................................... 5
•
Added RNODE = 330 Ω to Differential output voltage (Dominant) (second line of Test Conditions) in the DRIVER
ELECTRICAL table................................................................................................................................................................. 5
•
Added a third line of Test Conditions to Differential output voltage (Dominant) in the DRIVER ELECTRICAL table............ 5
•
Added T ≤ 85°C to VOD®) Test Conditions in the DRIVER ELECTRICAL CHARACTERISTICS .......................................... 5
•
Deleted ICC - Supply current from the RECEIVER ELECTRICAL CHARACTERISTICS ..................................................... 6
•
Added Receiver noise rejection row to the RECEIVER ELECTRICAL CHARACTERISTIC table......................................... 6
•
Added TYP values to the Differential output signal rise and fall times in the DRIVER SWITCHING
CHARACTERISTIC table ....................................................................................................................................................... 7
•
Changed table title From: ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS To: PACKAGE DISSIPATION
RATINGS................................................................................................................................................................................ 8
•
Added the SON (DRJ) option to the PACKAGE DISSIPATION RATINGS table................................................................... 8
•
Changed Figure 1 title From: tLOOP1-LOOP TIME To: RECESSIVE-TO-DOMINANT LOOP DELAY ........................................ 9
•
Changed Figure 2 title From: tLOOP2-LOOP TIME To: DOMINANT-TO-RECESSIVE LOOP DELAY ........................................ 9
•
Changed Figure 4 From: DRIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE To:
DRIVER OUTPUT VOLTAGE vs OUTPUT CURRENT ......................................................................................................... 9
•
Changed Figure 5 From: DRIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE To:
DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT .............................................................................. 9
•
Changed Figure 8 title From: DIFFERENTIAL OUTPUT FALL TIME To: DIFFERENTIAL OUTPUT TRANSITION TIME... 9
•
Changed Figure 12 - Driver VOD, label RNODE was 330Ω±1% .............................................................................................. 11
•
Changed Table 1 header From: MEASURED To: DIFFERENTIAL INPUT ......................................................................... 13
•
Added Note B to Figure 22................................................................................................................................................... 16
•
Added a row ( X Open) to Table 2 - Driver .......................................................................................................................... 19
Changes from Revision B (September 2003) to Revision C
Page
•
Changed the front page format............................................................................................................................................... 1
•
Changed Junction temperature, TJ - SOIC Package MAX value From 150°C To: 145°C ..................................................... 5
•
Changed the THERMAL CHARACTERISTICS table values ................................................................................................. 7
•
Changed the ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS table values ........................................................ 8
Changes from Revision A (September 2003) to Revision B
Page
•
Changed the front page format............................................................................................................................................... 1
•
Changed DESCRIPTION text From: and tolerance to transients of ±50 V To: and tolerance to transients of ±200 V ......... 1
Changes from Original (November 2002) to Revision A
•
Page
Changed multiple items within the document......................................................................................................................... 1
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
D
GND
1
8
RS
2
7
VCC
3
6
R
4
5
CANH
CANL
Vref
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CANH
7
I/O
High-level CAN bus line
CANL
6
I/O
Low-level CAN bus line
D
1
I
GND
2
GND
R
4
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called
RXD, receiver output
RS
8
I
Mode select pin: strong pulldown to GND = high-speed mode, strong pull up to VCC = lowpower mode, 10-kΩ to 100-kΩ pulldown to GND = slope control mode
VCC
3
Supply
VREF
5
O
CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called
TXD, driver input
Ground connection
Transceiver 5-V supply voltage
Reference output voltage
6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
Supply voltage, VCC
MIN
MAX
UNIT
–0.3
7
V
Voltage at any bus pin(CANH or CANL)
–36
36
V
–200
200
V
Input voltage, VI (D, Rs, or R)
–0.3
VCC + 0.5
V
Receiver output current, IO
–10
10 mA
mA
–3
3
kV
Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b
Electrical fast
transient/burst
IEC 61000-4-4, Classification
B
CANH, CANL
CANH, CANL
Continuous total power dissipation
(1)
(2)
(see Dissipation Ratings)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground pin.
6.2 ESD Ratings
VALUE
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
Electrostatic discharge
All pins
±6000
CANH, CANL and GND
±14000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
(1)
(2)
4
UNIT
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode) VI or VIC
D input
Low-level input voltage, VIL
D input
V
(1)
12
V
Input voltage at Rs for standby, VI(Rs)
V
0.3 VCC
V
–6
6
V
0
VCC
V
0.75 VCC
VCC
V
0
100
kΩ
Input voltage to Rs, VI(Rs)
Rs wave-shaping resistance
Driver
–50
Receiver
mA
–4
Driver
Low-level output current, IOL
50
Receiver
Operating free-air temperature, TA
mA
4
SN65HVD251
–40
125
SN55HVD251
–55
125
Junction temperature, TJ
(1)
UNIT
0.7 VCC
Differential input voltage, VID
High-level output current, IOH
MAX
5.5
–7
High-level input voltage, VIH
NOM
4.5
°C
145
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
6.4 Thermal Information
SN55HVD251
THERMAL METRIC (1)
SN65HVD251
DRJ (SON)
D (SOIC)
P (PDIP)
8 PINS
8 PINS
8 PINS
UNIT
RθJC(top)
Junction-to-case (top) thermal resistance
52
44.6
66.6
°C/W
RθJB
Junction-to-board thermal resistance
73
78.7
48.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Supply Current
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC
(1)
Supply current
TEST CONDITIONS
MIN
TYP (1)
MAX UNIT
Standby
Rs at VCC, D at VCC
275
Dominant
D at 0 V, 60-Ω load, Rs at 0 V
65
Recessive
D at VCC, no load, Rs at 0 V
14
µA
mA
All typical values are at 25°C and with a 5-V supply.
6.6 Electrical Characteristics: Driver
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VO(D)
Bus output voltage
(Dominant)
CANH
VO(R)
Bus output voltage
(Recessive)
CANH
VOD(D)
VOD(R)
(1)
CANL
CANL
Differential output voltage (Dominant)
Differential output voltage (Recessive)
MIN
2.75
Figure 10 and Figure 11 ,
D at 0 V Rs at 0 V, T ≥ –40°C
TYP (1)
MAX UNIT
3.5
0.5
Figure 10 and Figure 11 , D at 0.7 VCC,
Rs at 0 V
4.5
2
2
2.5
3
V
2
2.5
3
Figure 10 , D at 0 V, Rs at 0 V
1.5
2
3
V
Figure 12 , D at 0 V, Rs at 0 V, RNODE = 330 Ω
1.2
2
3.1
V
Figure 12 , D at 0 V, Rs at 0 V, RNODE = 165
Ω, VCC ≥ 4.75 V
1.2
2
3.1
V
mV
Figure 10 and Figure 11 , D at 0.7 VCC
–120
12
D at 0.7 VCC, no load, T ≤ 85°C
–0.5
0.05
V
All typical values are at 25°C and with a 5-V supply.
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Electrical Characteristics: Driver (continued)
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX UNIT
VOC(pp)
Peak-to-peak common-mode output voltage
Figure 18, Rs at 0 V
IIH
High-level input current, D Input
D at 0.7 VCC
–40
600
0
µA
IIL
Low-level input current, D Input
D at 0.3 VCC
–60
0
µA
Figure 20, VCANH at –7 V, CANL Open
IOS(SS)
mV
–200
Figure 20, VCANH at 12 V, CANL Open
Short-circuit steady-state output current
2.5
Figure 20, VCANL at -7 V, CANH Open
–2
Figure 20, VCANL at 12 V, CANH Open
CO
Output capacitance
See receiver input capacitance
IOZ
High-impedance output current
See receiver input current
IIRs(s)
Rs input current for standby
Rs at 0.75 VCC
IIRs(f)
Rs input current for full speed operation
Rs at 0 V
mA
200
–10
µA
–550
0
µA
6.7 Electrical Characteristics: Receiver
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ - VIT-)
VOH
High-level output voltage
Figure 15, IO = –4 mA
VOL
Low-level output voltage
Figure 15, IO = 4 mA
MIN
TYP
MAX UNIT
750
Rs at 0 V, (See Table 1)
500
900
650
mV
100
0.8 VCC
V
0.2 VCC
CANH or CANL at 12 V
II
Bus input current
CANH or CANL at 12 V,
VCC at 0 V
CANH or CANL at -7 V
CANH or CANL at -7 V,
VCC at 0 V
V
600
Other bus
pin at 0 V,
Rs at 0 V, D
at 0.7 VCC
715
µA
–460
–340
CI
Input capacitance, (CANH or CANL)
Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5
V, D at 0.7 VCC
20
pF
CID
Differential input capacitance
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5 V, D
at 0.7 VCC
10
RID
Differential input resistance
D at 0.7 VCC, Rs at 0 V
40
100
kΩ
RIN
Input resistance, (CANH or CANL)
D at 0.7 VCC, Rs at 0 V
20
50
kΩ
Receiver noise rejection
See Figure 22
pF
6.8 VREF-Pin Characteristics
over recommended operating conditions (unless otherwise noted).
PARAMETER
VO
6
Reference output voltage
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TEST CONDITIONS
MIN
–5 µA < IO < 5 µA
–50 µA < IO < 50 µA
TYP
MAX
0.45 VCC
0.55 VCC
0.4 VCC
0.6 VCC
UNIT
V
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SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015
6.9 Power Dissipation Characteristics
PARAMETER
PD
TSD
TEST CONDITIONS
Device power dissipation
MIN
TYP
MAX
UNIT
VCC = 5 V, Tj = 27°C, RL = 60 Ω,
RS at 0 V, Input to D a 500-kHz
50% duty cycle square wave
97.7
mW
VCC = 5.5 V, Tj = 130°C, RL = 60 Ω,
RS at 0 V, Input to D a 500-kHz
50% duty cycle square wave
142
mW
165
°C
Thermal shutdown junction temperature
6.10 Switching Characteristics: Driver
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
40
70
Figure 13, Rs with 10 kΩ to ground
90
125
Figure 13, Rs with 100 kΩ to ground
500
800
85
125
Figure 13, Rs at 0 V
tpLH
Propagation delay time, low-to-high-level output
Figure 13, Rs at 0 V
tpHL
Propagation delay time, high-to-low-level output
Figure 13, Rs with 10 kΩ to ground
200
260
Figure 13, Rs with 100 kΩ to ground
1150
1450
Figure 13, Rs at 0 V
tsk(p)
Pulse skew (|tpHL - tpLH|)
Figure 13, Rs with 10 kΩ to ground
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
ten
Enable time from standby to dominant
Figure 13, Rs with 100 kΩ to ground
Figure 13, Rs at 0 V
Figure 13, Rs with 10 kΩ to ground
Figure 13, Rs with 100 kΩ to ground
45
85
110
180
650
900
35
80
100
35
80
100
100
150
250
100
150
250
600
950
1550
600
950
1550
Figure 17
0.5
UNIT
ns
µs
6.11 Switching Characteristics: Device
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TYP
MAX
60
100
Figure 19, Rs with 10 kΩ to ground
100
150
Figure 19, Rs with 100 kΩ to ground
440
800
Figure 19, Rs at 0 V
115
150
Figure 19, Rs with 10 kΩ to ground
235
290
Figure 19, Rs with 100 kΩ to ground
1070
1450
105
145
Figure 19, Rs at 0 V
tloop1
Total loop delay, driver input to receiver
output, recessive to dominant
tloop2
Total loop delay, driver input to receiver
output, dominant to recessive
tloop2
Total loop delay, driver input to receiver
output, dominant to recessive
Figure 19, Rs at 0 V, VCC from 4.5 V to 5.1 V
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MIN
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UNIT
ns
ns
ns
7
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6.12 Switching Characteristics: Receiver
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tpLH
Propagation delay time, low-to-high-level output
35
50
tpHL
Propagation delay time, high-to-low-level output
35
50
tsk(p)
Pulse skew (|tpHL - tpLH|)
tr
Output signal rise time
tf
Output signal fall time
tp(sb)
Propagation delay time in standby
Figure 15
20
2
2
Figure 21, Rs at VCC
4
UNIT
ns
4
500
6.13 Dissipation Ratings
PACKAGE
SOIC (D)
PDIP (P)
WSON (DRJ)
(1)
(2)
(3)
8
DERATING FACTOR
ABOVE TA = 25°C
(1)
CIRCUIT BOARD
MODEL
TA = 25°C
POWER RATING
TA = 85°C POWER
RATING
TA = 125°C POWER
RATING
Low-K (2)
576 mW
4.8 mW/°C
288 mW
96 mW
High-K (3)
924 mW
7.7 mW/°C
462 mW
154 mW
Low-K (2)
888 mW
7.4 mW/°C
444 mW
148 mW
High-K (3)
1212 mW
10.1 mW/°C
606 mW
202 mW
Low-K (2)
403 mW
4.03 mW/°C
262 mW
100 mW
High-K
(no Vias) (3)
1081 mW
10.8 mW/°C
703 mW
270 mW
High-K
(with Vias)
2793 mW
27.9 mW/°C
1815 mW
698 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
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6.14 Typical Characteristics
150
RS = 0 V
RS = 0 V
74
72
VCC = 4.5 V
VCC = 5 V
70
VCC = 5.5 V
tLOOP2 – Loop Time – ns
tLOOP1 – Loop Time – ns
145
68
66
VCC = 5.5 V
135
130
VCC = 4.5 V
125
64
62
–40 –25 –10 5
VCC = 5 V
140
20 35 50 65 80 95 110 125
120
–40 –25 –10 5
Figure 1. Recessive-to-Dominant Loop Delay vs Free-Air
Temperature
5
30
VCC = 5 V,
TA = 25°C,
RS = 0 V,
RL = 60 W,
CL = 50 pF
4.5
VOD - Driver Output Voltage - V
ICC – RMS Supply Current – mA
31
29
28
27
26
25
0
4
CANH
3.5
VCC = 5 V,
TA = 25°C,
RS = 0 V,
D at 0V
3
2.5
2
1.5
CANL
1
0.5
0
250 500 750 1000 1250 1500 1750 2000
0
10
Signaling Rate – kbps
VCC = 5 V,
TA = 25°C,
RS = 0 V,
D at 0V
3.5
3
2.5
2
1.5
1
0.5
0
10
20
30
40
50
60
30
40
50
60
70
80
70
80
IO - Driver Output Current - mA
Figure 5. Driver Differential Output Voltage vs Output
Current
Figure 4. Driver Output Voltage vs Output Current
VOD(D) – Dominant Differential Output Voltage – V
VOD - Driver Differential Output Voltage - V
4.5
4
20
IO - Driver Output Current - mA
Figure 3. Supply Current (RMS) vs Signaling Rate
0
35 50 65 80 95 110 125
Figure 2. Dominant-to-Recessive Loop Delay vs Free-Air
Temperature
33
32
20
TA – Free-Air Temperature – ºC
TA – Free-Air Temperature – °C
3
VCC = 5.5 V
2.5
2
VCC = 4.5 V
VCC = 5 V
1.5
1
RS = 0 V,
D at 0V,
RL = 60 W
0.5
0
–55
–40
0
25
70
85
125
TA – Free-Air Temperature – °C
Figure 6. Dominant Differential Output Voltage vs free-Air
Temperature
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Typical Characteristics (continued)
1000
TA = 25°C,
RS = 0 V,
D at 0V,
RL = 60 W
50
tf - Differential Output Fall Time - ns
IO – Driver Output Current – mA
60
40
30
20
10
0
TA = 25°C
900
800
VCC = 5.5 V
VCC = 5 V
700
600
VCC = 4.5 V
500
400
300
200
100
0
1
2
3
4
5
6
0
10 20 30 40 50 60 70 80 90 100
VCC – Supply Voltage – V
RS - Slope Resistance - kW
Figure 7. Driver Output Current vs Supply Voltage
Figure 8. Differential Output Transition Time vs Slope
Resistance (Rs)
Input Resistance Matching − %
0
−0.50
VCC = 5.5 V
−1
−1.50
VCC = 5 V
−2
VCC = 4.5 V
−2.50
−3
−50
0
50
100
150
TA − Free-Air Temperature −°C
Figure 9. Input Resistance Matching vs Free-Air Temperature
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7 Parameter Measurement Information
IO(CANH)
VO(CANH)
D
VOD
II
1%
IIRs
Rs
VI
60
+
VO(CANH) + VO(CANL)
2
VOC
IO(CANL)
VI(Rs)
_
VO(CANL)
Figure 10. Driver Voltage, Current, and Test Definition
Dominant
VO(CANH)
3.5 V
Recessive
2.5 V
VO(CANL)
1.5 V
Figure 11. Bus Logic State Voltage Definitions
CANH
D
VOD
VI
RNODE
60 W ± 1%
+
_
RS
CANL
–7 V ≤ VTEST ≤ 12 V
RNODE
Figure 12. Driver VOD
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CANH
D
VI
RL =
60 W ±1%
+
VI(Rs)
_
Rs
(see Note A)
CL =
50 pF ±20%
(see Note B)
VO
CANL
VCC
VCC/2
VI
VCC/2
0V
tPHL
tPLH
0.9V
VO
90%
0.5V
10%
tr
VO(D)
VO(R)
tf
Figure 13. Driver Test Circuit and Voltage Waveforms
CANH
R
VI(CANH)
VI(CANH) + VI(CANL)
VIC =
2
VI(CANL)
IO
VID
VO
CANL
Figure 14. Receiver Voltage and Current Definitions
CANH
R
VI
(see Note A)
CANL
1.5 V
IO
CL = 15 pF
20% (see Note B)
VO
3.5 V
VI
2.4 V
2V
1.5 V
tPLH
VO
tPHL
0.7 VCC
10%
90%
tr
VOH
0.3 VCC
10%
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6ns, tf ≤ 6ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 15. Receiver Test Circuit and Voltage Waveforms
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CANH
R
CANL
100 W
Pulse Generator
15 µs Duration
1% Duty Cycle
tr, tr £ 100 ns
D at 0 V
or VCC
RS at 0 V or VCC
This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 16. Test Circuit, Transient Overvoltage Test
Table 1. Receiver Characteristics Over Common Mode Voltage
DIFFERENTIAL INPUT
OUTPUT
VCANH
INPUT
VCANL
|VID|
R
12 V
11.1 V
900 mV
L
–6.1 V
–7 V
900 mV
L
–1 V
–7 V
6V
L
12 V
6V
6V
L
–6.5 V
–7 V
500 mV
H
12 V
11.5 V
500 mV
H
–7 V
–1 V
6V
H
6V
12 V
6V
H
open
open
X
H
VOL
VOH
DUT
CANH
0V
VI
D
60 W ± 1%
Rs
CANL
R
+
VO
_
15 pF ± 20%
VCC
0.7 VCC
VI
0V
VOH
0.3 VCC
VO
ten
0.3 VCC
VOL
Figure 17. Ten Test Circuit and Voltage Waveforms
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CANH
27 W ± 1%
D
VI
CANL
27 W ± 1%
RS
50 pF ±20%
VOC
VOC(PP)
VOC
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6ns, tf ≤ 6ns, ZO = 50 Ω.
Figure 18. Peak-to-Peak Common Mode Output Voltage
DUT
CANH
VI
D
60 W ± 1%
10 kW or 100 kW ± 5%
_
RS
CANL
VRs +
R
+
VO
_
15 pF ± 20%
VCC
50%
D Input
0V
tLoop2
tLoop1
VOH
0.7 Vcc
R Output
0.3 Vcc
VOL
Figure 19. TLOOP Test Circuit and Voltage Waveforms
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IOS
0 V or VCC
CANH
D
CANL
Rs
Vin –7 V or 12 V
I OS(SS)
I OS(P)
15 s
0V
12 V
Vin
0V
10 s
or
0V
Vin
–7 V
Figure 20. Driver Short-Circuit Test
CANH
R
VI
(see Note A)
CANL
CL = 15 pF
1.5 V
VO
(see Note B)
3.5 V
2.4 V
VI
1.5 V
tp(sb)
VOH
VO
0.3 VCC
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6ns, tf ≤ 6ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 21. Receiver Propagation Delay in Standby Test Circuit and Waveform
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5V
R2±1%
R1±1%
CANH
+
R
VID
–
CANL
Vac
R1±1%
VI
R2±1%
VID
R1
R2
500 mV
50
450
900 mV
50
227
12 V
VI
–7 V
A.
All input pulses are supplied by a generator having the following characteristics: fIN < 1.5 MHz, TA = 25°C, VCC = 5 V.
B.
The receiver output should not change state during application of the common-mode input waveform.
Figure 22. Common-Mode Input Voltage Rejection Test
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8 Detailed Description
8.1 Overview
The SNx5HVD251CAN bus transceiver is compatible with the ISO 11898-2 High Speed CAN (Controller Area
Network) physical layer standard. It is design to interface between the differential bus lines in controller area
network and the CAN protocol controller at data rates up to 1 Mbps.
8.2 Functional Block Diagram
VCC (3)
Undervoltage
SLOPE
CONTROL and
MODE LOGIC
Overtemperature
Sensor
RS
VCC (3)
VREF (5)
VCC/2
Vcc (3)
CANH
Driver
D
CANL
R
8.3 Feature Description
VCC
3
5 V
ref
1
D
RS 8
R
4
7
CANH
6 CANL
Figure 23. Function Diagram (Positive Logic)
8.3.1 Mode Control
RS, Pin 8, selects one of three possible modes of operation: high-speed, slope control, or low-power mode.
8.3.2 High-Speed Mode
The high-speed mode of operation can be selected by setting RS (Pin 8) low. High-speed allows the output to
switch as fast as possible with no internal limitations on the output rise and fall slopes. The CAN bus driver and
receiver are fully operational and the CAN communication is bi-directional. The driver is translating a digital input
on D to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH
and CANL to a digital output on R.
8.3.3 Slope Control Mode
The rise and fall slope of the SNx5HVD251 driver output can be adjusted by connecting a resistor from Rs (Pin
8) to ground (GND), or to a low-level input voltage as shown in Figure 24. The slope of the driver output signal is
proportional to the pin's output current. This slope control is implemented with an external resistor value of 10 kΩ
to achieve a ~15-V/μs slew rate, and up to 100 kΩ to achieve a ~2.0-V/μs slew rate. Figure 8 shows a plot of
differential output transition time vs slope resistance from which the slew rate can be calculated.
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Feature Description (continued)
8.3.4 Low-Power Mode
If a high-level input (>0.75 VCC) is applied to RS (Pin 8), the circuit enters a low-current, listen only standby mode
during which the driver is switched off and the receiver remains active. If using this mode to save system power
while waiting for bus traffic, the local controller can monitor the R output pin for a falling edge which indicates that
a dominant signal was driven onto the CAN bus. The local controller can then drive the RS pin low to return to
slope control mode or high-speed mode.
NOTE
Silent mode may be used to implement babbling idiot protection, to ensure that the driver
does not disrupt the network during a local fault. Silent mode may also be used in
redundant systems to select or de-select the redundant transceiver (driver) when needed.
RS
D 1
10kΩ
to
100k Ω
GND 2
7 CANH
VCC 3
6 CANL
R 4
TMS320LF2407
8
5 VREF
Figure 24. Slope Control
8.3.5 Thermal Shutdown
The SNx5HVD251 has a thermal shutdown feature that turns off the driver outputs when the junction
temperature nears 165°C. This shutdown prevents catastrophic failure from bus shorts, but does not protect the
circuit from possible damage. The user should strive to maintain recommended operating conditions and not
exceed absolute-maximum ratings at all times. If an SNx5HVD251 is subjected to many, or long-duration faults
that can put the device into thermal shutdown, it should be replaced.
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8.4 Device Functional Modes
Table 2. Driver
INPUTS
OUTPUTS
Voltage at Rs, VRs
D
CANH
CANL
BUS STATE
L
VRs < 1.2 V
H
L
Dominant
H
VRs < 1.2 V
Z
Z
Recessive
Open
X
Z
Z
Recessive
X
VRs > 0.75 VCC
Z
Z
Recessive
X
Open
Z
Z
Recessive
Table 3. Receiver
(1)
DIFFERENTIAL INPUTS [VID = V(CANH) - V(CANL)]
OUTPUT R (1)
VID ≥ 0.9 V
L
0.5 V < VID < 0.9 V
?
VID ≤ 0.5 V
H
Open
H
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
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D Input
R Output
Vcc
Vcc
100 kW
1 kW
15 W
Input
Output
9V
9V
CANL Input
CANH Input
Vcc
110 kW
Vcc
110 kW
9 kW
45 kW
9 kW
45 kW
Input
Input
40 V
9 kW
9 kW
40 V
CANH and CANL Outputs
Rs Input
Vcc
Vcc
Output
40 V
+
Input
Figure 25. Equivalent Input and Output Schematic Diagrams
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Typical Bus Voltage (V)
2
3
4
The CAN bus has two states during powered operation of the device; dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the D and R pin. A recessive bus
state is when the bus is biased to VCC/2 via the high-resistance internal resistors RIN and RID of the receiver,
corresponding to a logic high on the D and R pins. See Figure 26 and Figure 27.
CANH
Vdiff(D)
Vdiff(R)
1
CANL
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Time, t
Figure 26. Bus States
CANH
VCC/2
RXD
CANL
Figure 27. Simplified Recessive Common Mode Bias and Receiver
The HVD251 CAN transceiver is typically used in applications with a host microprocessor or FPGA that includes
the link layer portion of the CAN protocol. The different nodes on the network are typically connected through the
use of a 120-Ω characteristic impedance twisted pair cable with termination on both ends of the bus.
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Application Information (continued)
The basics of bus arbitration require that the receiver at the sending node designate the first bit as dominant or
recessive after the initial wave of the first bit of a message travels to the most remote node on a network and
back again. Typically, this sample is made at 75% of the bit width, and within this limitation, the maximum
allowable signal distortion in a CAN network is determined by network electrical parameters.
Factors to be considered in network design include the 5 ns/m propagation delay of typical twisted-pair bus
cable; signal amplitude loss due to the loss mechanisms of the cable; and the number, length, and spacing of
drop-lines (stubs) on a network. Under strict analysis, variations among the different oscillators in a system must
also be accounted for with adjustments in signaling rate and stub and bus length. Table 4 lists the maximum
signaling rates achieved with the HVD251 in high-speed mode with several bus lengths of category-5, shielded
twisted-pair (CAT 5 STP) cable.
Table 4. Maximum Signaling Rates for Various Cable
Lengths
BUS LENGTH (m)
SIGNALING RATE (kbps)
30
1000
100
500
250
250
500
125
1000
62.5
The ISO 11898 standard specifies a maximum bus length of 40 meters and maximum stub length of 0.3 meters
with a maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths,
and many more nodes on a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A
bus with a large number of nodes requires a transceiver with high input impedance such as the HVD251.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (Zo). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the ISO 11898 standard, should have as little effect as possible on standard
operating parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the –2-V to 7-V common-mode range of tolerable
ground noise specified in the standard, helps to ensure data integrity. The HVD251 extends data integrity beyond
that of the standard with an extended –7-V to 12-V range of common-mode operation.
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NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW
75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
ALLOWABLE JITTER
Figure 28. Typical CAN Differential Signal Eye-Pattern
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 28, the differential
signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic
crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all effects of
systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900-mV or 500-mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces & cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC and ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the HVD251 mitigate most sources of signal corruption, and when used with a
quality shielded twisted-pair cable, help meet data integrity.
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9.2 Typical Application
VIN
VCC
3
VIN
VOUT
RS
5-V Voltage
Regulator
(such as TPS76350)
RS (8)
10kΩ
to
100kΩ
5-V MCU
CANH (7)
VREF (5)
RXD
TXD
R (4)
D (1)
CANL (6)
GND (2)
Optional:
Terminating
Node
Figure 29. Typical Application Schematic
9.2.1 Design Requirements
9.2.1.1 Bus Loading, Length, and Number of Nodes
The ISO11898 Standard specifies up to 1-Mbps data rate, maximum bus length of 40 meters, maximum drop line
(stub) length of 0.3 meters and a maximum of 30 nodes. However, with careful network design, the system may
have longer cables, longer stub lengths, and many more nodes to a bus. Many CAN organizations and standards
have scaled the use of CAN for applications outside the original ISO11898 standard. They have made system
level trade-offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these
specifications are ARINC825, CANopen, CAN Kingdom, DeviceNet and NMEA200.
Node n
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
SN65HVD251 CAN
Transceiver
SN65HVD1050 CAN
Transceiver
SN65HVD233 CAN
Transceiver
(with termination)
MCU or DSP
CAN
Controller
SN65HVD257 CAN
Transceiver
RTERM
RTERM
Figure 30. Typical CAN Bus
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Typical Application (continued)
A high number of nodes requires a transceiver with high input impedance and wide common mode range such
as the SNx5HVD251 CAN transceiver. ISO11898-2 specifies the driver differential output with a 60-Ω load (two
120-Ω termination resistors in parallel) and the differential output must be greater than 1.5 V. The SNx5HVD251
devices are specified to meet the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential
output voltage minimum of 1.2 V across a common mode range of –2 V to 7 V via a 330-Ω coupling network.
This network represents the bus loading of 120 SNx5HVD251 transceivers based on their minimum differential
input resistance of 40 kΩ. Therefore, the SNx5HVD251 supports up to 120 transceivers on a single bus segment
with margin to the 1.2-V minimum differential input voltage requirement at each node.
For CAN network design, margin must be given for signal loss across the system and cabling, parasitic loadings,
network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes may be
lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 meters by careful system
design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1
km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898 CAN standard.
9.2.2 Detailed Design Procedure
9.2.2.1 CAN Termination
The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO ). Resistors equal to the characteristic impedance of the line should be used to
terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes
to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the
cable or in a node, but if nodes may be removed from the bus the termination must be carefully placed so that it
is not removed from the bus.
Termination is typically a 120-Ω resistor at each end of the bus. If filtering and stabilization of the common mode
voltage of the bus is desired, then split termination may be used (see Figure 30). Split termination utilizes two 60Ω resistors with a capacitor in the middle of these resistors to ground. Split termination improves the
electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common mode voltages
at the start and end of message transmissions.
Care should be taken when determining the power ratings of the termination resistors. A typical worst case fault
condition is if the system power supply and ground were shorted across the termination resistance which would
result in much higher current through the termination resistance than the CAN transceiver's current limit.
Standard Termination
Split Termination
CANH
CANH
RTERM/2
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM/2
CANL
CANL
Figure 31. CAN Termination
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Typical Application (continued)
9.2.2.2 Loop Propagation Delay
Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the
driver input (D pin) to the differential outputs (CANH and CANL pins), plus the delay from the receiver inputs
(CANH and CANL) to its output pin.
A typical loop delay for the SNx5HVD251 transceiver is displayed in Figure 32. This loop delay will increase as
the slope of the driver output is slowed during slope control mode. This increased loop delay means that there is
a tradeoff between the total bus length able to be used and the driver's output slope used via the slope control
pin of the device. For example, the loop delay for a 10-kΩ resistor from the RS pin to ground is ~100 ns, and the
loop delay for a 100-kΩ resistor is ~500 ns. Therefore, if we use the following rule-of-thumb that the propagation
delay of typical twisted pair bus cable is 5 ns/m, we can calculate an approximate cable length trade-off between
normal high-speed mode and slope control mode with a 100-kΩ resistor. Using typical values, the loop delay for
a recessive to dominant bit with RS tied directly to ground is 60ns, and with a 100-kΩ resistor is 440 ns. At 5ns/m of propagation delay, which you have to count in both directions the difference is 38 meters (440 – 60)/(2 ×
5).
Another option to improving the electromagnetic emissions of the device besides slowing down the edge rates of
the driver in slope control mode is using quality shielded bus cabling.
9.2.3 Application Curve
Figure 32. tLOOP Delay
9.3 System Example
9.3.1 ISO 11898 Compliance of HVD251 5-V CAN Bus Transceiver
9.3.1.1 Introduction
The SNx5HVD251 CAN transceiver is a 5-V CAN transceiver that meets or exceeds the specification of the ISO
11898 standard for applications employing a controller area network.
9.3.1.2 Differential Signal
CAN is a differential bus where complementary signals are sent over two wires and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single ended logic level output signal.
26
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SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015
System Example (continued)
Figure 33. Differential Output Waveform
The CAN driver creates the differential voltage between CANH and CANL in the dominant state. The dominant
differential output of the HVD251 is greater than 1.5 V and less than 3 V across a 60-Ω load as defined by the
ISO 11898 standard. Figure 33 shows CANH, CANL, and the differential dominant state level for the
SNx5HVD251.
A CAN receiver is required to output a recessive state when less than 500 mV of differential voltage exists on the
bus, and a dominant state when more than 900 mV of differential voltage exists on the bus. The CAN receiver
must do this with common-mode input voltages from –2 V to 7 V.
9.3.1.3 Common-Mode Signal
A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. Since the bias voltage
of the recessive state of the device is dependent on VCC, any noise present or variation of VCC will have an effect
on this bias voltage seen by the bus. The HVD251 CAN transceiver has the recessive bias voltage set to 0.5 ×
VCC to comply with the ISO 11898-2 CAN standard.
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100nF ceramic capacitor located as close as possible to the VCC supply pins as possible. The TPS76350 is a linear
voltage regulator suitable for the 5-V supply rail.
11 Layout
11.1 Layout Guidelines
In order for the PCB design to be successful, start with design of the protection and filtering circuitry. Because
ESD and EFT transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz, high frequency
layout techniques must be applied during PCB design. On chip IEC ESD protection is good for laboratory and
portable equipment but is usually not sufficient for EFT and surge transients occurring in industrial environments.
Therefore robust and reliable bus node design requires the use of external transient protection devices at the bus
connectors. Placement at the connector also prevents these harsh transient events from propagating further into
the PCB and system.
Use VCC and ground planes to provide low inductance.
NOTE
High frequency current follows the path of least inductance and not the path of least
resistance.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
An example placement of the Transient Voltage Suppression (TVS) device indicated as D1 (either bi-directional
diode or varistor solution) and bus filter capacitors C5 and C7 are shown in Figure 34.
The bus transient protection and filtering components should be placed as close to the bus connector, J1, as
possible. This prevents transients, ESD and noise from penetrating onto the board and disturbing other devices.
Bus termination: Figure 31 shows split termination. This is where the termination is split into two resistors, R5
and R6, with the center or split tap of the termination connected to ground via capacitor C6. Split termination
provides common mode filtering for the bus. When termination is placed on the board instead of directly on the
bus, care must be taken to ensure the terminating node is not removed from the bus as this will cause signal
integrity issues if the bus is not properly terminated on both ends.
Bypass and bulk capacitors should be placed as close as possible to the supply pins of transceiver, examples
C2, C3 (VCC).
Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize
trace and via inductance.
To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3 and R4.
To filter noise on the digital IO lines, a capacitor may be used close to the input side of the IO as shown by C1
and C4.
Since the internal pull up and pull down biasing of the device is weak for floating pins, an external 1-kΩ to 10-kΩ
pullup or pulldown resistor should be used to bias the state of the pin more strongly against noise during
transient events.
Pin 1: If an open-drain host processor is used to drive the D pin of the device an external pullup resistor between
1 kΩ and 10 kΩ should be used to drive the recessive input state of the device.
Pin 5: is VREF output voltage reference, if used, this pin should be tied to the common mode point of the split
termination. If VREF is not used, the pin can be left floating.
Pin 8: is shown assuming the mode pin, RS, will be used. If the device will only be used in high-speed mode or
slope control mode, R3 is not needed and the pads of C4 could be used for the pulldown resistor to GND.
28
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SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015
11.2 Layout Example
D
R1
8
1
C1
2
C6
VREF
3
6
4
5
R6
J1
R2
R5
C7
R
GND
D1
U1
SN65HVD251
C3
C2
VCC
7
RS
C5
GND
R3
C4
R4
Figure 34. Layout Example Recommendation
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Product Folder Links: SN55HVD251 SN65HVD251
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN55HVD251
Click here
Click here
Click here
Click here
Click here
SN65HVD251
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN55HVD251DRJR
ACTIVE
SON
DRJ
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
SN55
HVD251
SN65HVD251D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VP251
SN65HVD251DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VP251
SN65HVD251DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VP251
SN65HVD251DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VP251
SN65HVD251P
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
65HVD251
SN65HVD251PE4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
65HVD251
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD251 :
• Automotive: SN65HVD251-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN55HVD251DRJR
SON
DRJ
8
1000
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
SN65HVD251DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN55HVD251DRJR
SON
DRJ
8
1000
210.0
185.0
35.0
SN65HVD251DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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