Texas Instruments | TS3USBA225 USB 2.0 High-Speed (480 Mbps) and Audio Switches with Negative Signal Capability and 1.8-V Logic Compatibility and Power-Down Mode (Rev. C) | Datasheet | Texas Instruments TS3USBA225 USB 2.0 High-Speed (480 Mbps) and Audio Switches with Negative Signal Capability and 1.8-V Logic Compatibility and Power-Down Mode (Rev. C) Datasheet

Texas Instruments TS3USBA225 USB 2.0 High-Speed (480 Mbps) and Audio Switches with Negative Signal Capability and 1.8-V Logic Compatibility and Power-Down Mode (Rev. C) Datasheet
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TS3USBA225
SCDS328C – OCTOBER 2011 – REVISED AUGUST 2015
TS3USBA225 USB 2.0 High-Speed (480 Mbps) and Audio Switches with Negative Signal
Capability and 1.8-V Logic Compatibility and Power-Down Mode
1 Features
2 Applications
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
2.7-V to 5.0-V Operating Power Supply (VCC)
MHL/High-Speed USB (480 Mbps) Switch:
– V I/O Accepts Signals up to 4.5 V
(Independent of VCC)
– 6.5 Ω rON Typical
– 3 pF CON Typical
– 1.9 GHz Bandwidth (–3 dB)
Audio Switch:
– 2.5 Ω rON Typical
– Negative Rail Capability down to –1.8 V
– Low THD: < 0.05%
– Internal Shunt Resistors for Click-and-Pop
Reduction
1.8-V Compatible Control Input (SEL1 and SEL2)
Threshold
Minimized Current Consumption (~5 µA) in
Power-Down Mode
Power-Off Protection: All I/O Pins are High-Z
when VCC= 0 V
12-Pin QFN Package (2 mm × 1.7 mm, 0.4 mm
Pitch)
ESD Performance Tested per JESD 22
– 2000 V Human-Body Model
(A114-B, Class II)
– 1000 V Charged-Device Model (C101)
Cell phones and Smartphones
Tablet PCs
Portable Instrumentation
Digital Still Cameras
Portable Navigation Devices (GPS)
USB 2.0, MIPI (CSI/DSI), LVDS Switching
3 Description
The TS3USBA225 is a 2-channel single-pole triplethrow (SP3T) multiplexer that supports USB 2.0 HighSpeed (480 Mbps) signals in all 3 differential
channels. The first two high-speed differential
channels also support Mobile High Definition Link
(MHL) signaling with resolution and video frame rates
up to 720p, 60 fps and 1080i, 30 fps. The remaining
differential channel can also be used as an audio
switch that is designed to allow analog audio signals
to swing negatively. This configuration allows the
system designer to use a common connector for
audio and USB 2.0 or MHL data.
The TS3USBA225 has a VCC range of 2.7 V to 5.0 V
with the capability to pass true-ground audio signals
down to –1.8 V. The device also supports a powerdown mode that can be enabled when both SEL1 and
SEL2 controls are low to minimize current
consumption when no signal is transmitting. The
TS3USBA225 also features internal shunt resistors
on the audio path to reduce clicks and pops that may
be heard when the audio switches are selected.
Simplified Block Diagram
Device Information(1)
PART NUMBER
D0+
D0-
MHL/
USB 2.0
TS3USBA225
PACKAGE
UQFN (12)
BODY SIZE (NOM)
2.00 mm × 1.70 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
D+/R
D-/L D1+
D1-
R
USB
Connector
L
MHL/
UART/
USB 2.0
USB 2.0/
Negative
Audio
SEL1 SEL2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3USBA225
SCDS328C – OCTOBER 2011 – REVISED AUGUST 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dynamic Characteristics ...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2012) to Revision C
Page
•
Added Device Information table, ESD Ratings table, Thermal Information table, Detailed Description section,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Correct typographical errors to align datasheet information. ................................................................................................. 1
•
Changed "Negative Rail Capability -1.8 V to VCC" to “Negative Rail Capability down to -1.8 V” in Features. .................... 1
•
Updated Recommended Operating Conditions table. ........................................................................................................... 5
•
Updated Typical Characteristics graphs. ............................................................................................................................... 9
Changes from Revision A (April 2012) to Revision B
Page
•
Updated Application Block Diagrams. .................................................................................................................................... 1
•
Updated MIN value in the Absolute Maximum Ratings table for VR, VL................................................................................. 4
•
Updated MIN value in the Recommended Operating Conditions table for VR, VL. ................................................................ 5
Changes from Original (October 2011) to Revision A
Page
•
Added MHL specification to datasheet. .................................................................................................................................. 1
•
Updated Application Block Diagrams. .................................................................................................................................... 1
•
Added MHL Eye Pattern graphics. ....................................................................................................................................... 13
2
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5 Pin Configuration and Functions
RUT Package
12-Pin UQFN
Top View
R
12
11
SEL1
2
10
D+/R
VCC
3
9
GND
D1-
4
8
D-/L
D0-
5
7
SEL2
D0+
1
D1+
6
L
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
D0+
1
I/O
MHL/USB/UART Data 1 (Differential +)
D1+
2
I/O
MHL/USB/UART Data 2 (Differential +)
VCC
3
-
D1–
4
I/O
MHL/USB/UART Data 2 (Differential –)
D0–
5
I/O
MHL/USB/UART Data 1 (Differential –)
L
6
I/O
USB-/Left Channel Audio
SEL2
7
I
D–/L
8
I/O
GND
9
-
D+/R
10
I/O
SEL1
11
I
R
12
I/O
Power supply
Control Input Select Line 2. The default state for SEL2 is LOW.
MHL/USB/UART/Audio Common Connector
Ground
MHL/USB/UART/Audio Common Connector
Control Input Select Line 1. The default state for SEL1 is LOW.
USB+/Right Channel Audio
Function Table
SEL1
SEL2
X
L
L
(1)
VCC
L,R
D0+, D0-
D1+, D1-
X
L
OFF
OFF
OFF
Hi-Z Mode
L
H
OFF
OFF
OFF
Power-Down Mode
H
H
ON
OFF
MHL/USB Mode 1
H
L
H
OFF
OFF
USB/Audio Mode
H
H
H
OFF
ON
MHL/USB Mode 2
OFF
(1)
ON
OFF
(1)
MODE
100 Ω shunt resistors are enabled in this state.
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2) (3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage
–0.3
6.0
V
VD0+,
VD0-,
VD1+,
VD1-
High speed differential signal voltage
–0.3
4.6
V
– 1.9
4.6
VR, VL Audio signal voltage
IK
Analog port diode current
VI
Digital input voltage (SEL1, SEL2)
–0.3
IIK
Digital logic input clamp
current (3)
–50
ICC
Continuous current through VCC
IGND
Continuous current through GND
–100
Tstg
Storage temperature
–65
(1)
(2)
(3)
VI/O+ ,VI/O- < 0
V
–50
VI < 0
mA
6.0
V
100
mA
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2000
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
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6.3 Recommended Operating Conditions
VCC
Supply voltage range
VD0+, VD0-,
VD1+, VD1-
High speed differential signal voltage range
VR, VL
Audio signal voltage range when not in power-down mode
Audio signal voltage range when in power-down mode
IK
Analog port diode current
VI
Digital input voltage range (SEL1, SEL2)
TA
Operating free-air temperature
(1)
VI/O+ ,VI/O- < 0
MIN
MAX
2.7
5.0
UNIT
V
0
4.5
V
–1.8
4.3 V or VCC (1)
–1
1
V
–50
mA
0
VCC
V
–40
85
°C
This rating is exclusive and the voltage on the pins must not exceed either 4.3 V or VCC. E.g. if VCC = 3.3 V the voltage on the pin must
not exceed 3.3 V and if VCC is = 5.0 V the voltage on the pin must not exceed 4.3 V.
6.4 Thermal Information
TS3USBA225
THERMAL METRIC
(1)
RUT (UQFN)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
118.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.1
°C/W
RθJB
Junction-to-board thermal resistance
47.9
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
47.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TA = –40°C to 85°C, typical values are at VCC = 3.3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
MHL/USB SWITCH
7.5
Ω
ron
ON-state resistance
VCC = 3.0 V
VI/O+,I/O- = 0.4 V, ION = 15 mA
6.5
Δron
ON-state resistance match
between channels
VCC = 3.0 V
VI/O+,I/O- = 1.7 V, ION = 15 mA
0.1
Ω
ron (flat)
ON-state resistance
flatness
VCC = 3.0 V
VI/O+,I/O- = 0 to 1.7 V, ION = 15 mA
0.5
Ω
IOZ
OFF leakage current
VCC = 3.6 V
Switch OFF , VI/O+,I/O- = 0 to 3.6 V,
VD+/R, D-/L = 0 V
1
µA
3.5
Ω
USB/AUDIO SWITCH
ron
ON-state resistance
VCC = 3.0 V
SEL1 = High, SEL2 = Low,
VL/R = –1.8 V, 0 V, 0.7 V,
ION = –26 mA
2.5
Δron
ON-state resistance match
between channels
VCC = 3.0 V
SEL1 = High, SEL2 = Low,
VL/R = 0.7 V, ION = –26 mA
0.1
Ω
ron (flat)
ON-state resistance
flatness
VCC = 3.0 V
SEL1 = High, SEL2 = Low,
VL/R = –1.8 V, 0 V, 0.7 V, ION = –26 mA
0.1
Ω
rSHUNT
Shunt resistance
VCC = 2.7 V to 5.0 V
Switch OFF, VL/R = 0.7 V,
ISHUNT = 10 mA
100
200
Ω
DIGITAL CONTROL INPUTS (SEL1, SEL2)
VIH
Input logic high
VIL
Input logic low
IIN
Input leakage current
rPD1,
rPD2
Internal pulldown resistance VCC = 2.7 V to 5.0 V
6
VCC = 3.3 V to 5.0 V
1.3
V
VCC = 2.7 V to 3.3 V
0.25
VCC = 3.3 V to 5.0 V
0.4
VCC = 2.7 V to 5.0 V
VIN = 5.0 V
±3
VIN = 0 V
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±0.1
3
V
μA
MΩ
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6.6 Dynamic Characteristics
TA = –40°C to 85°C, typical values are at VCC = 3.3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
MHL/USB SWITCH
tpd
Propagation Delay
VCC = 2.7 V or 3.3 V
tON
Turn-on time
RL = 50 Ω, CL = 35 pF
VCC = 2.7 V
0.25
60
ns
ns
tOFF
Turn-off time
RL = 50 Ω, CL = 35 pF
VCC = 2.7 V
20
ns
tSK(O)
Channel-to-channel skew
VCC = 2.7 V or 3.3 V
15
ps
tSK(P)
Skew of opposite transitions
of same output
VCC = 2.7 V or 3.3 V
15
ps
CI/O+(OFF)
CI/O-(OFF)
OFF capacitance
VCC = 2.7 V or 3.3 V,
VD0+/D0- =0 or 3.3 V
Switch OFF
1
pF
CI/O+(ON)
CI/O-(ON)
ON capacitance
VCC = 2.7 V or 3.3 V,
VD0+/D0- = 0 or 3.3 V
Switch ON
3
pF
CI
Digital input capacitance
VCC = 2.7 V or 3.3 V, VI = 0 or 3.3 V
2.5
pF
BW
Bandwidth
VCC = 2.7 V or 3.3 V, RL = 50 Ω
Switch ON
1.9
GHz
OISO
OFF Isolation
VCC = 2.7 V or 3.3 V, RL = 50 Ω,
f = 240 MHz
Switch OFF
-35
dB
XTALK
Crosstalk
VCC = 2.5 V or 3.3 V, RL = 50 Ω,
f = 240 MHz
Switch ON
-45
dB
USB/AUDIO SWITCH
tON
Turn-on time
RL = 50 Ω, CL = 35 pF
VCC = 2.7 V
40
µs
tOFF
Turn-off time
RL = 50 Ω, CL = 35 pF
VCC = 2.7 V
15
ns
CL(OFF),
CR(OFF)
L , R OFF capacitance
VCC = 2.7 V to 4.5 V, f = 20 kHz
Switch OFF
1.0
pF
CL(ON),
CR(ON)
L, R ON capacitance
VCC = 2.7 V to 4.5 V, f = 20 kHz
Switch ON
3.5
pF
OISO
OFF Isolation
VCC = 3.3 V, RL = 50 Ω, f = 20 kHz
Switch OFF
-85
dB
XTALK
Crosstalk
VCC = 3.3 V, RL = 50 Ω, f = 20 kHz
Switch ON
-95
dB
Total harmonic distortion
VCC = 3.3 V, SEL1 = High, SEL2 = Low,
f = 20 Hz to 20 kHz, RL = 600 Ω,
VIN = 2 Vpp
Switch ON
0.05%
THD
SUPPLY
VCC
Power supply voltage
2.7
Positive supply current
VCC = 2.7 V, 3.6 V, 5.0 V VIN= VCC or GND, VI/O = 0 V,
Switch ON or OFF
Positive supply current
(Power-Down Mode)
VCC = 2.7 V, 3.6 V, 5.0 V, VI/O = 0 V,
SEL1 and SEL2 = Low
PSRR
Power Supply Rejection
Ratio
VCC = 2.7 V, 3.6 V, 5.0 V VIN = VCC +/- 200 mVpp
RL = 50 Ω
IOFF
Power off leakage current
VCC = 0 V, D+/R, D-/L, D0+, D0-, D1+, D1-, L,
VIN = 0 to 4.5 V
ICC
ICC,
PD
5.0
V
25
50
µA
3
5
µA
-60
dB
±0.1
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7.5
2.8
7
2.6
On-State Resistance (Ω)
On-State Resistance (Ω)
6.7 Typical Characteristics
6.5
6
5.5
5
4.5
4
3.5
2.4
2.2
2
1.8
1.6
1.4
1.2
0
0.5
1
1.5
2
Input Voltage (V)
2.5
3
1
3.5
−2
−1
G001
Figure 1. ON Resistance vs VI for MHL/USB Switch
0
Input Voltage (V)
1
2
G002
Figure 2. ON Resistance vs VI for USB/Audio Switch
0
0
−1
−2
−4
−3
Gain (dB)
Gain (dB)
−2
−4
−5
−6
−8
−6
−10
−7
1M
10M
100M
Frequency (Hz)
1G
1M
G003
10M
100M
Frequency (Hz)
1G
10G
G004
Figure 3. Gain vs Frequency for MHL/USB Switch
Figure 4. Gain vs Frequency for USB/Audio Switch
0
0
−20
−20
−40
−40
−60
−80
−60
−80
−100
−100
−120
−120
−140
100k
1M
10M
100M
Frequency (Hz)
1G
10G
−140
100k
G005
Figure 5. Off Isolation vs Frequency for MHL/USB Switch
8
−12
100k
10G
Crosstalk (dB)
Isolation (dB)
−8
100k
1M
10M
100M
Frequency (Hz)
1G
10G
G006
Figure 6. Cross Talk vs Frequency for MHL/USB Switch
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2E-6
1E-5
0
5E-6
-2E-6
0
-4E-6
-5E-6
-6E-6
Leakage (A)
Leakage (A)
Typical Characteristics (continued)
-8E-6
-1E-5
-1.2E-5
-1.4E-5
-1E-5
-1.5E-5
-2E-5
-2.5E-5
-3E-5
-1.6E-5
-3.5E-5
-40qC
25qC
85qC
-1.8E-5
-2E-5
-40qC
25qC
85qC
-4E-5
-4.5E-5
-2.2E-5
-2
-1.5
-1
-0.5
0
0.5
1
VL/R (V)
1.5
2
2.5
-2
3
-1.5
-1
0.001
-40qC
25qC
85qC
0.0012
Leakage (A)
Leakage (A)
0.0006
0.0005
0.0004
0.0003
0.0001
2.5
3
3.5
D002
-40qC
25qC
85qC
0.0008
0.0006
0.0004
0
0
-0.0002
-2
-0.0001
-2
-1
0
1
VL/R (V)
2
3
4
-1.5
-1
-0.5
D003
Figure 9. ION, VCC = 5.0 V
0
0.5
1
VL/R (V)
1.5
2
2.5
3
D004
Figure 10. IOFF, VCC = 2.7 V
0.01
0.004
-40qC
25qC
85qC
0.009
0.008
-40qC
25qC
85qC
0.007
0.0025
Leakage (A)
Leakage (A)
2
0.0002
0.0002
0.002
0.0015
0.001
0.006
0.005
0.004
0.003
0.002
0.001
0.0005
0
0
-0.0005
-2
1.5
0.001
0.0007
0.003
0.5
1
VL/R (V)
0.0014
0.0008
0.0035
0
Figure 8. ION, VCC = 3.3 V
Figure 7. ION, VCC = 2.7 V
0.0011
0.0009
-0.5
D001
-0.001
-1.5
-1
-0.5
0
0.5
1
VL/R (V)
1.5
2
2.5
3
3.5
-0.002
-2
-1
D005
Figure 11. IOFF, VCC = 3.3 V
0
1
2
VL/R (V)
3
4
5
D006
Figure 12. IOFF, VCC = 5.0 V
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7 Detailed Description
7.1 Overview
The TS3USBA225 is a 2-channel single-pole triple-throw (SP3T) multiplexer that supports USB 2.0 High-Speed
(480 Mbps) signals in all 3 differential channels. The first two high-speed differential channels also support
Mobile High Definition Link (MHL) signaling with video resolution and frame rates up to 720p, 60 fps and 1080i,
30 fps. The remaining differential channel can also be used as an audio switch that is designed to allow analog
audio signals to swing negatively. This configuration allows the system designer to use a common connector for
audio and USB 2.0 or MHL data.
The TS3USBA225 has a VCC range of 2.7 V to 5.0 V with the capability to pass true-ground audio signals down
to –1.8 V. The device also supports a power-down mode that can be enabled when both SEL controls are low to
minimize current consumption when no signal is transmitting. The TS3USBA225 also features internal shunt
resistors on the audio path to reduce clicks and pops that may be heard when the audio switches are selected.
7.2 Functional Block Diagram
D0+
D1+
R
D+/R
Rshunt
D0D1L
D-/L
VCC
R shunt
Charge
Pump
SEL1
Control
Logic
Rpd2
Rpd1
SEL2
7.3 Feature Description
7.3.1 Click and Pop Reduction
The shunt resistors in the TS3USBA225 automatically discharge any capacitance at the L and R terminals when
they are not connected to the common D-/L and D+/R paths. This reduces the audible click-and-pop sounds that
occur when switching between audio sources. Audible clicks and pops are caused when a step DC voltage is
switched into the speaker. By automatically discharging the side that is not connected, any residual DC voltage is
removed, thereby reducing the clicks and pops.
10
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Feature Description (continued)
7.3.2 Negative Signal Swing Capability
The TS3USBA225 has an analog audio path L and R that can support negative signals that pass below ground
without distortion. These analog switches operate from –1.8 V to 4.3 V.
7.4 Device Functional Modes
7.4.1 High Impedance (Hi-Z) Mode
The TS3USBA225 has a Hi-Z mode that places the device's signal paths in a high impedance state when there
is no power supplied to the TS3USBA225 VCC pin. This mode will isolate the signal bus in a powered off situation
so that it may not interfere with other devices that maybe sharing the bus.
7.4.1.1 Power-Down Mode
The TS3USBA225 has a power-down mode that reduces the power consumption to 3 μA when the device is not
in use. To put the device in power-down mode and disable the switch, the SEL1 and SEL2 pins must be supplied
with a logic low signal.
7.4.2 Device Functional Modes
Table 1 is the function table for the TS3USBA225.
Table 1. Function Table
(1)
SEL1
SEL2
VCC
L,R
D0+, D0-
D1+, D1-
MODE
X
X
L
OFF
OFF
OFF
Hi-Z Mode
L
L
H
OFF
OFF
OFF
Power-Down Mode
L
H
H
ON
OFF
MHL/USB Mode 1
H
L
H
OFF
OFF
USB/Audio Mode
H
H
H
OFF
ON
MHL/USB Mode 2
OFF
(1)
ON
OFF
(1)
100 Ω shunt resistors are enabled in this state.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TS3USBA225 is typically used to route signals from one USB connector to multiple signal paths in a system
including an analog audio/negative signal path. All signal paths through the device are unbuffered bidirectional
path which can represented by perfect 0 Ω impedance wire in an ideal case. All signal paths can handle USB 2.0
signals but the L and R paths are the only paths that can support a negative signal.
8.2 Typical Application
TS3USBA225
2.7 V to 4.3 V
+
–
Vcc
MHL/
USB 2.0
D0+
10 μF
D0-
0.1 μF
GND
MHL/
UART/
USB 2.0
D1+
D1VBUS
D+
D-
D+
L/R
D-
R/L
SEL1
USB
Connector
SEL2
Vcc
D+
D-
USB 2.0/
Negative
Audio
Accessory
Detection
USB + UART + AUDIO
Figure 13. Application Block Diagram
8.2.1 Design Requirements
Design requirements of the USB 1.0, 1.1, and 2.0 standards should be followed.
TI recommends that the digital control pins SEL1 and SEL2 be pulled up to VCC or down to GND to avoid
undesired switch positions that could result from the floating logic pin.
8.2.2 Detailed Design Procedure
The TS3USB221 can be properly operated without any external components. However, it is recommended that
unused pins should be connected to ground through a 50 Ω resistor to prevent signal reflections back into the
device.
12
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Typical Application (continued)
8.2.3 Application Curves
Figure 14. Eye Pattern: 480-Mbps USB 2.0 Eye Pattern (No
Switch)
Figure 15. Eye Pattern: 480-Mbps USB 2.0 Eye Pattern for
USB Switch
Figure 16. MHL Eye Pattern: 480p 60 fps (No Switch)
Figure 17. MHL Eye Pattern: 480p 60 fps (With Switch)
Figure 18. MHL Eye Pattern: 720p 60 fps, 1080i 30fps (No
Switch)
Figure 19. MHL Eye Pattern: 720p 60 fps, 1080i 30fps (With
Switch)
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9 Power Supply Recommendations
Power to the device is supplied through the VCC pin and should follow the USB 1.0, 1.1, and 2.0 standards. TI
recommends placing a bypass capacitor as close as possible to the supply pin VCC to help smooth out low
frequency noise to provide better load regulation across the frequency spectrum.
10 Layout
10.1 Layout Guidelines
Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
D+/D– traces.
The high-speed D+/D– traces should always be matched lengths and must be no more than 4 inches; otherwise,
the eye diagram performance may be degraded. A high-speed USB connection is made through a shielded,
twisted pair cable with a differential characteristic impedance. In layout, the impedance of D+ and D– traces
should match the cable characteristic differential impedance for optimal performance.
Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Take precaution when designing test points on twisted
pair lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub should be less than 200 mm.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in Figure 20.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 20. Four-Layer Board Stack-Up
The majority of signal traces should run on a single layer, preferably Signal 1. Immediately next to this layer
should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or
power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing
the number of signal vias reduces EMI by reducing inductance at high frequencies. For more information on
layout guidelines, see High Speed Layout Guidelines (SCAA082) and USB 2.0 Board Design and Layout
Guidelines (SPRAAR7).
14
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10.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane
To Codec
To Microcontroller
USB Port 0
1
D0+
2
D1+
3
Vcc
4
D1-
5
D0-
12
SEL1
11
R
D+/R
10
GND
9
L
D-/L
8
6
SEL2
7
USB Port 1
0603 Cap
To USB Host
To Microcontroller
To Codec
Figure 21. Layout Schematic
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www.ti.com
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
TS3USBA225RUTR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
UQFN
RUT
12
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
(LQ7 ~ LQR)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TS3USBA225RUTR
UQFN
RUT
12
3000
180.0
9.5
1.9
2.3
0.75
4.0
8.0
Q1
TS3USBA225RUTR
UQFN
RUT
12
3000
180.0
8.4
1.95
2.3
0.75
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS3USBA225RUTR
UQFN
RUT
12
3000
184.0
184.0
19.0
TS3USBA225RUTR
UQFN
RUT
12
3000
202.0
201.0
28.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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