Texas Instruments | SN65HVDA100-Q1 LIN Physical Interface (Rev. C) | Datasheet | Texas Instruments SN65HVDA100-Q1 LIN Physical Interface (Rev. C) Datasheet

Texas Instruments SN65HVDA100-Q1 LIN Physical Interface (Rev. C) Datasheet
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SN65HVDA100-Q1
SLIS128C – NOVEMBER 2011 – REVISED JULY 2015
SN65HVDA100-Q1 LIN Physical Interface
1 Features
3 Description
•
•
The SN65HVDA100 device is the Local Interconnect
Network (LIN) physical interface, which integrates the
serial transceiver with wakeup and protection
features. The LIN bus is a single-wire bidirectional
bus typically used for low-speed in-vehicle networks
using data rates from 2.4 kbps to 20 kbps. The LIN
protocol output data stream on TXD is converted by
the SN65HVDA100 into the LIN bus signal through a
current-limited wave-shaping driver as outlined by the
LIN Physical Layer Specification. The receiver
converts the data stream from the LIN bus and
outputs the data stream through RXD. The LIN bus
has two states: dominant state (voltage near ground)
and recessive state (voltage near battery). In the
recessive state, the LIN bus is pulled high by the
internal pullup resistor (30 kΩ) and series diode, so
no external pullup components are required for slave
applications. Master applications require an external
pullup resistor (1 kΩ) plus a series diode per the LIN
specification.
1
•
•
•
•
•
•
•
•
•
•
•
•
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•
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•
Qualified for Automotive Applications
Local Interconnect Network (LIN) Physical Layer
Specification Revision 2.1 Compliant and
Conforms to SAEJ2602 Recommended Practice
for LIN
Extended Operation With Supply From 5 V to
27 V DC (LIN Specification 7 V to 18 V)
LIN Transmit Speed up to 20-kbps LIN Specified
Maximum, High-Speed Receive Capable
Sleep Mode: Ultra-Low Current Consumption
Allows Wake-Up Events From: LIN Bus, Wake-Up
Input (External Switch) or Host MCU
Wake-Up Request on RXD Pin
Wake-Up Source Recognition on TXD Pin
Interfaces to MCU With 5-V or 3.3-V I/O Pins
High Electromagnetic Compatibility (EMC)
Control of External Voltage Regulator (INH Pin)
Supports ISO9141 (K-Line) -Like Functions
ESD Protection to ±12 kV (Human Body Model)
on LIN Pin
LIN Pin Handles Voltage From –27 V to 45 V
(Short to Battery or Ground)
Survives Transient Damage in Automotive
Environment (ISO 7637)
Undervoltage Protection on VSUP
TXD Dominant State Time-Out Protection
Prevention of False Wakeups With Bus Stuck
Dominant Fault
Thermal Shutdown
Unpowered Node or Ground Disconnection
Failsafe at System Level, Node Does Not Disturb
Bus (No Load on Bus)
2 Applications
•
•
•
Device Information(1)
PART NUMBER
SN65HVDA100-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SN65HVDA100-Q1 Block Diagram
VSUP
RXD 1
8
INH
7
VSUP
6
LIN
5
GND
VSUP/2
Receiver
EN 2
Filter
Wake up
State
INH Control
NWAKE 3
TXD 4
Filter
30lQ
Fault Detection
and Protection
Dominant State
Timeout
Driver with
Slope Control
Automotive
Industrial Sensing
White Goods Distributed Control
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVDA100-Q1
SLIS128C – NOVEMBER 2011 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
9
1
1
1
2
3
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Switching Characteristics .......................................... 7
Dissipation Ratings ................................................... 8
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
16
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Application ............................................... 18
11 Power Supply Recommendations ..................... 21
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 22
13 Device and Documentation Support ................. 23
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
14 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2014) to Revision C
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision A (January 2013) to Revision B
Page
•
Ordered PIN ASSIGNMENTS table alphabetically by pin name............................................................................................ 3
•
Added new Mode Transitions section, including a new figure ............................................................................................. 18
•
Revised the application schematic diagram ......................................................................................................................... 19
Changes from Original (November 2011) to Revision A
Page
•
Deleted -03V to 45V from the 1.5 row in the abs max table, units column ............................................................................ 4
•
Changed added Delta and corrected Hysteresis in elec chara table, row 4.4 and changed the TYP column from 4.5
to 0.2....................................................................................................................................................................................... 5
•
Deleted rows 9.1 and 9.2 from the elec chara table............................................................................................................... 6
•
Added Minimum to the statement in parens in front of dominant, row 11.9 of elec chara table ............................................ 7
2
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5 Description (continued)
In sleep mode, low quiescent current is needed even though the wake-up circuits remain active and allow for
remote wake up through the LIN bus or local wake up through the NWake or EN pins.
The SN65HVDA100 has been designed for operation in the harsh automotive environment. The device also
prevents back-feed current through LIN to the supply input in case of a ground shift or supply voltage
disconnection. The device also features undervoltage, overtemperature, and loss-of-ground protection. In the
event of a fault condition, the transmitter is immediately switched off and remains off until the fault condition is
removed.
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
RXD
EN
NWake
TXD
1
8
2
7
3
6
4
5
INH
VSUP
LIN
GND
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
EN
2
I
GND
5
GND
Enable input
INH
8
O
Inhibit controls external voltage regulator with inhibit input
LIN
6
I/O
LIN bus single-wire transmitter and receiver
NWake
3
I
High-voltage input for device wake up
RXD
1
O
RXD output (open-drain) interface reporting state of LIN bus voltage
TXD
4
I
TXD input interface to control state of LIN output
VSUP
7
Supply
Ground
Device supply voltage (connected to battery in series with external reverse blocking diode)
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
MIN
MAX
UNIT
VSUP
Supply line supply voltage (LIN 2.1 Param 11)
–0.3
45
V
VLIN
LIN input voltage
–27
45
V
VNWAK
NWake input voltage (through serial resistor ≥ 2 kΩ )
–0.3
45
V
E
IO
Output current
–50
2
mA
VINH
INH voltage
–0.3
Vsup + 0.3
V
VLogic
Logic pin voltage
–0.3
5.5
V
TA
Operational free-air (ambient) temperature
–40
125
°C
TJ
Junction temperature
–40
150
°C
TLEAD
Lead temperature (soldering, 10 seconds)
260
°C
Tstg
Storage temperature
150
°C
(1)
(2)
RXD, TXD, EN
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
7.2 ESD Ratings
VALUE
All pins
V(ESD)
Human body model (HBM), per AEC
Q100-002 (1)
Electrostatic discharge
LIN bus pin (2)
±12000
(3)
±11000
NWake pin
Charged device model (CDM), per AEC Q100-011
(1)
(2)
(3)
UNIT
±4000
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Test method based upon AEC-Q100-002, LIN bus pin stressed with respect to GND.
Test method based upon AEC-Q100-002, NWake pin stressed with respect to GND.
7.3 Recommended Operating Conditions
MIN
MAX
VSUP
Supply line supply voltage (LIN 2.1 Param 10)
5
27
UNIT
V
VLIN
LIN input voltage
0
18
V
VNWake
NWake input voltage
0
27
V
VINH
INH voltage
0
27
V
VLogic
Logic voltage
0
5.25
V
TA
Operational free-air temperature (see Thermal Information)
–40
125
°C
7.4 Thermal Information
SN65HVDA100-Q1
THERMAL METRIC
(1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
112.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.3
°C/W
RθJB
Junction-to-board thermal resistance
52.9
°C/W
ψJT
Junction-to-top characterization parameter
19.3
°C/W
ψJB
Junction-to-board characterization parameter
52.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
VSUP = 5V to 27 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
VSUP SUPPLY
VSUP
Operational supply
voltage (LIN 2.1
Param 10) (2)
Device is operational beyond the LIN defined
nominal supply line voltage range of 5 V <
VSUP < 27 V
5
14
27
Nominal supply
voltage (LIN 2.1
Param 10)
Normal and standby modes
7
14
18
VSUP
Sleep mode
7
12
18
UVSUP
Undervoltage VSUP threshold
UVHYS
Delta hysteresis voltage for VSUP undervoltage threshold
ISUP
Supply current
4.35
4.65
0.2
V
V
V
V
Normal mode, EN = high, Bus dominant
(total bus load where RLIN ≥ 500 Ω and
CLIN ≤ 10 nF (see Figure 9) (3), INH = VSUP,
NWake = VSUP
1.2
7.5
mA
Standby mode, EN = low, Bus dominant
(total bus load where RLIN ≥ 500 Ω and
CLIN ≤ 10 nF (see Figure 9) (3), INH = VSUP,
NWake = VSUP
1
2.1
mA
Normal mode, EN = high, Bus recessive,
LIN = VSUP, INH = VSUP, NWake = VSUP
450
775
μA
Standby mode, EN = low, Bus recessive,
LIN = VSUP, INH = VSUP, NWake = VSUP
450
775
μA
10
20
μA
30
μA
5.5
V
Sleep mode, 7 V < VSUP ≤ 14 V,
LIN = VSUP, NWake = VSUP, EN = 0 V, TXD
and RXD floating
Sleep mode, 14 V < VSUP < 27 V,
LIN = VSUP, NWake = VSUP, EN = 0 V, TXD
and RXD floating
RXD OUTPUT PIN (OPEN DRAIN)
VO
Output voltage (4)
IOL
Low-level output
current, open drain
LIN = 0 V, RXD = 0.4 V
3.5
IIKG
Leakage current, highLIN = VSUP, RXD = 5 V
level
–5
–0.3
mA
0
5
μA
V
TXD INPUT/OUTPUT PIN
VIL
Low-level input voltage
–0.3
0.8
VIH
High-level input voltage
2
5.5
V
VIT
Input threshold hysteresis voltage
30
500
mV
Pulldown resistor
IIL
Low-level input
leakage current
TXD = Low
ITXD_Wake
Local wake up source
re recognition TXD
open drain drive
Standby mode after a local wake up event,
VLIN = VSUP, NWake = 0 V,
TXD = 1 V
125
350
800
kΩ
–5
0
5
μA
1.3
4.6
8
mA
LIN PIN (REFERENCED TO VSUP)
VOH
High-level output
voltage
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 14 V
VOL
Low-level output
voltage
LIN dominant, TXD = low, IO = 40 mA,
VSUP = 14 V
(1)
(2)
(3)
(4)
VSUP – 1
V
0.2 × VSUP
V
Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C.
All voltages are defined with respect to ground; positive currents flow into the SN65HVDA100 device.
In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN slave termination
resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN
slave termination is 20 kΩ, so the maximum supply current attributed to the termination is:ISUP (dom) max termination ≉ (VSUP –
(VLIN_Dominant + 0.7 V) / 20 kΩ.
RXD pin output is open drain. Output voltage is through external pullup resistance to logic supply of the system and impedance of the
RXD pin.
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Electrical Characteristics (continued)
VSUP = 5V to 27 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
Limiting current (LIN
2.1 Param 12)
IL
TEST CONDITIONS
TXD = 0 V, VLIN = 7 V to 27 V
Receiver leakage
current, dominant (LIN LIN = 0 V, 7 V ≤VSUP ≤ 18 V, Driver off
2.1 Param 13)
ILKG
Receiver leakage
current, recessive
(LIN 2.1 Param 14)
TYP (1)
MAX
UNIT
40
90
200
mA
–1
mA
LIN ≥ VSUP, 7 ≤ VSUP ≤18 V, Driver off
20
LIN = VSUP, driver off
–5
5
GND = VSUP , VSUP = 12 V,
0 V < VLIN < 18 V
–1
1
ILKG
Leakage current, loss
of ground (LIN 2.1
Param 15)
ILKG
Leakage current, loss
of supply (LIN 2.1
Param 16)
VIL
Low-level input
voltage (LIN 2.1
Param 17)
LIN dominant (including LIN dominant for
wake up)
VIH
High-level input
voltage (LIN 2.1
Param 18)
LIN recessive
VBUS_CNT
Receiver center
threshold (LIN 2.1
Param 19)
VBUS_CNT = (VIL + VIH) / 2
VHYS
Hysteresis voltage
(LIN 2.1 Param 20)
VHYS = (VIL - VIH)
VSERIAL_
Serial diode in LIN
termination pull up
path (LIN 2.1 Param
21)
By design and characterization
DIODE
MIN
7 V < LIN ≤ 12 V, VSUP = GND
5
12 V < LIN ≤ 18 V, VSUP = GND
10
0.4 × VSUP
0.6 × VSUP
0.475 x VSUP
μA
mA
μA
V
V
0.5 × VSUP
0.05 × VSUP
0.525 x VSUP
V
0.175 × VSUP
V
0.4
0.7
1.0
V
30
60
kΩ
RSLAVE
Pullup resistor to VSUP
Normal and standby modes
(LIN 2.1 Param 26)
20
RSLEEP
Pullup current source
to VSUP
–2
–20
μA
Sleep mode, VSUP = 14 V, LIN = GND
EN INPUT PIN
VIL
Low-level input
voltage
–0.3
0.8
V
VIH
High-level input
voltage
2
5.5
V
Vhys
Hysteresis voltage
By design and characterization
Pulldown resistor
IIL
Low-level input
current
EN = Low
500
mV
125
30
350
800
kΩ
–5
0
5
μA
25
50
Ω
0
5
μA
INH OUTPUT PIN
RDS(on)
ON-state resistance
Between VSUP and INH, INH = 2-mA drive,
Normal or standby mode
IIKG
Leakage current
Low-power mode, 0 < INH < VSUP
6
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Electrical Characteristics (continued)
VSUP = 5V to 27 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (1)
MIN
MAX
UNIT
NWAKE INPUT PIN
VIL
Low-level input
voltage
–0.3
VSUP – 3.3
V
VIH
High-level input
voltage
VSUP – 1
VSUP + 0.3
V
IIKG
Pullup current
NWake = 0 V
Leakage current
VSUP = NWake
–45
–10
–2
μA
–5
0
5
μA
AC CHARACTERISTICS
D1
Duty cycle 1 (5) (LIN
2.1 Param 27)
THREC(max) = 0.744 × VSUP,
THDOM(maximum) = 0.581 × VSUP,
VSUP = 7 V to 18 V, tBIT = 50 μs (20 kbps),
D1 = tBus_rec(min)/ (2 × tBIT) (see Figure 1)
D2
Duty cycle 2 (5) (LIN
2.1 Param 28)
THREC(min) = 0.422 × VSUP,
THDOM(min) = 0.284 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 50 μs (20 kbps),
D2 = tBus_rec(max)/ (2 × tBIT) (see Figure 1)
D3
Duty cycle 3 (LIN
2.1 Param 29)
THREC(max) = 0.778 × VSUP,
THDOM(max) = 0.616 × VSUP,
VSUP = 7 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D3 = tBus_rec(min)/ (2 × tBIT) (see Figure 1)
D4
Duty cycle 4 (5) (LIN
2.1 Param 30)
THREC(min) = 0.389 × VSUP,
THDOM(min) = 0.251 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D4 = tBus_rec(max)/ (2 × tBIT) (see Figure 1)
(5)
(5)
0.396
0.581
0.417
0.59
Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are
defined for 10.4-kbps operation. The SN65HVDA100 also meets these lower data rate requirements, while it is capable of the higher
speed 20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty
cycle definitions, for details see the SAEJ2602 specification.
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS
trx_pdr
Receiver rising propagation delay
time (LIN 2.1 Param 31)
RRXD = 2.4 kΩ, CRXD = 20 pF
(see Figure 2 and Figure 9)
6
μs
trx_pdf
Receiver falling propagation delay
time (LIN 2.1 Param 31)
RRXD = 2.4 kΩ, CRXD = 20 pF
(see Figure 2 and Figure 9)
6
μs
trx_sym
Symmetry of receiver propagation
delay time (LIN 2.1 Param 32)
Rising edge with respect to falling
edge
(trx_sym = trx_pdf - trx_pdr) RRXD = 2.4
kΩ,
CRXD = 20 pF (see Figure 2 and
Figure 9)
–2
2
μs
tNWake
NWake filter time for local wakeup
See Figure 6
25
50
150
μs
tLINBUS
LIN wake-up time (Minimum
dominant time on LIN bus for
wakeup)
See Figure 11, Figure 12, and
Figure 5
25
100
150
μs
tCLEAR
Time to clear false wake-up
prevention logic if LIN Bus had bus
stuck dominant fault (recessive time
on LIN bus to clear bus stuck
dominant fault)
See Figure 12
8
17
50
μs
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Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tDST
Dominant state time-out
tMODE_
TEST CONDITIONS
(1)
TYP
MAX
20
34
80
ms
5
μs
Time to change from standby mode
to normal mode or normal mode to
sleep mode through EN pin
Mode change delay time
CHANGE
(1)
MIN
UNIT
TXD Dominant state timeout limits the minimum data rate to 650 bps. The minimum datarates may be calculated by the following
forumulas. DataRateMaster(min) = tSYNC_DOM(max) / tDST(min) and DataRateSlave(min) = 9 + nmargin / tDST(min) where nmargin is a safety margin.
For slave node cases where nmargin ≤ 4, the master node case will be the limiting calculation.
7.7 Dissipation Ratings
TYP
PD
MAX
UNIT
Thermal shutdown temperature
180
°C
Thermal shutdown hysteresis
15
°C
230
mW
Power Dissipation in normal mode (dominant)
tBit
17
tBit
RECESSIVE
D = 0.5
TXD (Input)
DOMINANT
THRec(max)
LIN Bus
Signal
Thresholds
:
Worst case 1
THDom(max)
Vsup
THRec(min)
Thresholds
:
Worst case 2
THDom(min)
tBus_dom(max)
tBus_rec(max)
D = tBus_rec(min)/(2 x tBit)
RXD
D1 (20 kbps) and
D3 (10 kbps) case
tBus_dom(min)
tBus_rec(min)
D = tBus_rec(max)/(2 x tBit)
RXD
D2 (20 kbps) and
D4 (10 kbps) case
Figure 1. Definition of Bus Timing Parameters
8
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LIN Bus
0.6 VSUP
VSUP
0.4 VSUP
trx_pdf
trx_pdr
RXD
50%
50%
Figure 2. Propagation Delay
Wake Event
tMODE_CHANGE
EN
MODE
RXD
Normal
Transition
Mirrors Bus
Indeterminate
Ignore
tMODE_CHANGE
Sleep
Floating
Standby
Transition
Normal
Wake Request
RXD = low
Indeterminate
Ignore
Mirrors Bus
Figure 3. Mode Transitions
EN
INH
TXD
Vsup
High impedance
Weak internal pulldown
Weak internal pulldown
Vsup
LIN
RXD
MODE
Floating
Sleep
Normal
Figure 4. Wakeup Through EN
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LIN
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0.6 × VSUP
0.6 × VSUP
0.4 × VSUP
Vsup
0.4 × VSUP
t < tLINBUS
tLINBUS
Vsup
INH
TXD
High impedance
Weak internal pulldown
EN
RXD
MODE
Floating
Standby
Sleep
Normal
Figure 5. Wakeup Through LIN
NWake VIL
NWake VIH
NWake VIL
NWake
VSUP
tNWake
t < tNWake
INH
TXD
VSUP
High impedance
Weak internal pulldown
Wake-up source recognition:
Strong pulldown
EN
RXD
Floating
VSUP
LIN
MODE
Sleep
Standby
Normal
Figure 6. Wakeup Through NWake
10
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7.8 Typical Characteristics
30
1000
900
25
800
VOL (mV)
VOH
20
15
10
5
5
10
15
20
600
500
VOHLIN -40°C
400
VOHLIN 25°C
300
25
VSUP
VOLLIN (mV) -40°C
VOLLIN (mV) 25°C
VOLLIN (mV) 125°C
VOHLIN 125°C
0
700
200
30
5
10
15
Figure 7. VOH vs VSUPPLY and Temperature
20
25
VSUP
C002
30
C001
Figure 8. VOL vs VSUPPLY and Temperature
8 Parameter Measurement Information
Figure 9. Test Circuit for AC Characteristics
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9 Detailed Description
9.1 Overview
The SN65HVDA100-Q1 LIN transceiver is a LIN (Local Interconnect Network) physical layer transceiver which
integrates a serial transceiver with wake up and protection features. The LIN bus is a single wire, bi-directional
bus that typically is used in low speed in vehicle networks with data rates that range from 2.4 kbps to 20 kbps.
9.2 Functional Block Diagram
VSUP
INH
RXD
VSUP
VSUP/2
Receiver
EN
Filter
Wake up
State
INH Control
NWAKE
TXD
Filter
Fault Detection
and Protection
Dominant State
Timeout
30lQ
LIN
Driver with
Slope Control
9.3 Feature Description
9.3.1 LIN (Local Interconnect Network) Bus
This I/O pin is the single-wire LIN bus transmitter and receiver. The LIN pin can survive excessive DC and
transient voltages. There are no reverse currents from the LIN to supply (VSUP), even in the event of a ground
shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a lowside transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition, the
transmitter is disabled to protect the device. There is an internal pullup resistor with a serial diode structure to
VSUP, so no external pullup components are required for LIN slave mode applications. An external pullup resistor
and a series diode to VSUP must be added when the device is used for master node applications.
9.3.1.2 LIN Receiver Characteristics
The receiver’s characteristic thresholds are ratio-metric with the device supply pin according to the LIN
specification.
The receiver is capable of receiving higher data rates (>100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the SN65HVDA100 to be used for high-speed downloads at end-of-line production or
other applications. The actual data rates achievable depend on system time constants (bus capacitance and
pullup resistance) and driver characteristics used in the system.
9.3.1.2.1 Termination
There is an internal pullup resistor with a serial diode structure from LIN to VSUP, so no external pullup
components are required for LIN slave mode applications. An external pullup resistor (1 kΩ) and a series diode
to VSUP must be added when the device is used for master node applications per the LIN specification.
12
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Feature Description (continued)
VBattery
(KL30)
Voltage drop across the
diodes in the pullup path
VLIN_BUS
Simplified Transceiver
VSUP
VBattery
VSUP
VSUP
RXD
VLIN_Recessive
VSUP/2
Master
node
pullup
Receiver
LIN
Driver
with slope control
LIN Bus
GND
TXD
VLIN_Dominant
t
VBattery = Vehicle battery supply
VSUP = Electronic module supply (reverse battery diode blocked VBattery)
Figure 10. Definition of Voltage Levels
9.3.2 TXD (Transmit Input / Output)
TXD is the interface to the MCU’s LIN protocol controller or SCI/UART that is used to control the state of the LIN
output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is
recessive (near battery). The TXD input structure is compatible with microcontrollers with 3.3-V and 5-V I/O. TXD
has an internal pulldown resistor. The LIN bus is protected from being stuck dominant through a system failure
driving TXD low through the dominant state time-out timer. The TXD pin is pulled down strongly in standby mode
after a wake-up event on the NWake pin.
9.3.3 RXD (Receive Output)
RXD is the interface to the MCU’s LIN protocol controller or SCI/UART, which reports the state of the LIN bus
voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground) is
represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the
device to be used with 3.3-V and 5-V I/O microcontrollers. If the microcontroller’s RXD pin does not have an
integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required. In standby
mode the RXD pin is driven low to indicate a wake-up request from LIN or NWake.
9.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse battery blocking
diode. If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin, which
does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition
supplied) while the rest of the network remains powered (battery supplied).
9.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied).
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Feature Description (continued)
9.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high, the device is in normal mode, allowing a
transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep mode and
there are no transmission paths available. The device can enter normal mode only after wake up. EN has an
internal pulldown resistor to ensure the device remains in low-power mode even if EN floats.
9.3.7 NWake (High Voltage Wake Up Input)
NWake is a high-voltage input used to wake up from sleep mode. NWake is usually connected to an external
switch in the application. A low on NWake that is asserted longer than the filter time (tNWAKE) results in a local
wakeup. NWake provides an internal pullup source to VSUP.
9.3.8 INH (Inhibit Output)
INH is used to control an external voltage regulator that has an inhibit or enable input. When the device is in
normal operating mode, the inhibit switch is enabled and the external voltage regulator is activated. When device
is in sleep mode, the inhibit switch is disabled, which turns off the system voltage regulator. A wake-up event
transitions the device to standby by mode and re-enables INH which, in turn, restarts the system by turning on
the voltage regulators. INH can also drive an external transistor connected to an MCU interrupt input.
9.3.9 TXD Dominant State Timeout
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on
TXD. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the LIN bus
to return to the recessive state and communication to resume on the bus. The protection is cleared and the tDST
timer is reset by a rising edge on TXD. The TXD pin has an internal pulldown to ensure the device fails to a
known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no
change of state request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus, INH remains on,
and the LIN bus pullup termination remains on.
APPLICATION HINT: The maximum dominant TXD time allowed by the TXD Dominant state time-out limits
the minimum possible data rate of the device. The LIN protocol has different constraints for master and slave
applications thus there are different maximum consecutive dominant bits for each application case and thus
different minimum data rates.
Master node: The maximum continuous dominant is the maximum dominant of the SYNC BREAK
FIELD, tSYNC_DOM(max). The SYN BREAK FIELD notifies the 'start of frame' to all LIN slaves. It consists of
13 to 26 dominant bits (low phase) followed by a delimiter. Thus the minimum TXD dominant time out,
tDST(min) and the maximum SYNC BREAK FIELD for the master determine the minimum data rate for a
master node, which may be calculated by the following equation:
DataRateMaster(min) = tSYNC_DOM(max) / tDST(min)
Slave node: sends the response part of the LIN message frame which has a maximum consecutive
dominant length of 9 bits (start bit + 8 data bits). As a result the minimum baud rate of a slave can be
calculated by the following equation:
DataRateSlave(min) = 9 + nmargin / tDST(min) where nmargin is a saftey margin.
9.3.10 Thermal Shutdown
The LIN transmitter is protected through a current limit, however, if the junction temperature of the device
exceeds the thermal shutdown threshold, the device turns off the LIN transmitter circuit. Once the
overtemperature fault condition has been removed and the junction temperature has cooled beyond the
hysteresis temperature, the transmitter is re-enabled, assuming the device remained in the normal mode. During
this fault, the transceiver remains in normal mode (assuming no change of state request on EN), the transmitter
is disabled, the RXD pin reflects the LIN bus, INH remains on, and the LIN bus pullup termination remains on.
14
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Feature Description (continued)
9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
The device contains logic to detect bus stuck dominant system faults and prevent the device from waking up
falsely during this system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus
is dominant, the wake-up logic is locked out until a valid recessive on the bus "clears" the bus stuck dominant
condition. This logic prevents the potential for a cyclical false wakeup of the system if the bus is stuck dominant,
preventing excessive current use. Figure 11 and Figure 12 show the behavior of this protection feature.
EN
LIN Bus
tLINBUS
<tLINBUS
<tLINBUS
INH
Figure 11. No Bus Fault: Entering Sleep Mode With Bus Recessive Condition and Wakeup
EN
LIN Bus
tLINBUS
tLINBUS
tCLEAR
tLINBUS
<tCLEAR
INH
Figure 12. Bus Fault: Entering Sleep Mode With Bus Stuck Dominant Fault, Clearing, and Wakeup
9.3.12 Undervoltage on VSUP
The device contains a power-on reset circuit to avoid false bus messages during undervoltage conditions when
VSUP is less than UVVSUP.
9.3.13 Unpowered Device Does Not Affect the LIN Bus
The device has extremely low unpowered leakage current from the bus, so an unpowered node does not affect
the network or load it down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition
supplied) while the rest of the network remains powered (battery supplied).
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9.4 Device Functional Modes
9.4.1 Operating States
Unpowered System
Vsup £ Vsup_under
Vsup £ Vsup_under
Vsup > Vsup_under
EN = high
Vsup > Vsup_under
EN = low
Vsup £ Vsup_under
Vsup £ Vsup_under
Standby Mode
Driver : Off
RXD: Low
INH: High (On)
Termination: 30 kW
Sleep Mode
Normal Mode
Driver : On
RXD: LIN bus data
INH: High (On)
Termination: 30 kW
LIN Bus Wake-Up
or
Nwake Pin Wake-Up
EN = high
EN = low
Driver : Off
RXD: Floating
INH: High impedance (Off)
Termination: Weak pullup
EN = high
Figure 13. Operating States Diagram
Table 1. Operating Modes
EN
RXD
LIN BUS
TERMINATION
INH
TRANSMITTER
Sleep
Low
Floating
Weak current pullup
High impedance
Off
Standby
Low
Low
30 kΩ (typical)
High
Off
Wake-up event detected, waiting
on MCU to set EN
Normal
High
LIN bus data
30 kΩ (typical)
High
On
LIN transmission up to 20 kbps
MODE
COMMENTS
9.4.2 Normal Mode
This is the normal operational mode, in which the receiver and driver are active, and LIN transmission up to the
LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and
outputs it on RXD for the LIN controller, where recessive on the LIN bus is a digital high, and dominate on the
LIN bus is digital low. The driver transmits input data on TXD to the LIN bus. Normal mode is entered as EN
transitions high while the SN65HVDA100 is in sleep or standby mode.
16
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9.4.3 Sleep Mode
Sleep mode is the power saving mode for the SN65HVDA100. Even with the extremely low current consumption
in this mode, the SN65HVDA100 can still wake up from LIN bus through a wake-up signal, a low on NWake, or if
EN is set high. The LIN bus and NWake are filtered to prevent false wake-up events. The wake-up events must
be active for their respective time periods (tLINBUS, tNWake).
The sleep mode is entered by setting EN low.
While the device is in sleep mode, the following conditions exist:
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short circuited to ground). However, the weak current pullup is active to prevent false wake-up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• INH is high impedance.
• EN input, NWake input, and the LIN wake-up receiver are active.
9.4.4 Wake-Up Events
There are three ways to wake up from sleep mode:
• Remote wakeup through recessive (high) to dominant (low) state transition on LIN bus. The dominant state
must be held for tLINBUS filter time and then the bus must return to the recessive state (to eliminate false
wakeups from disturbances on the LIN bus or if the bus is shorted to ground).
• Local wakeup through a low on NWake, which is asserted low longer than the filter time tNWake (to eliminate
false wakeups from disturbances on NWake).
• Local wakeup through EN being set high.
9.4.4.1 Wake-Up Request (RXD)
When the device encounters a wake-up event from the LIN bus or NWake pin, RXD goes low, and the device
transitions to standby mode (until EN is reasserted high and the device enters normal mode). Once the device
enters normal mode, the RXD pin is releasing the wake-up request signal, and the RXD pin then reflects the
receiver output from the bus.
9.4.4.2 Wake-Up Source Recognition (TXD)
When the device encounters a wake-up event from the LIN bus or NWake pin, TXD indicates the source while
the device enters and remains in standby mode (until EN is reasserted high and the device enters normal mode).
In addition to the internal pullup resistor on TXD, typically an external pullup resistor (approximately 5 kΩ) is used
in the system's I/O supply voltage. A high on TXD in standby mode indicates a remote wakeup through the LIN
bus, and a low (strong pulldown) on the TXD pin indicates a local wakeup through the NWAKE pin.
9.4.5 Standby Mode
This mode is entered whenever a wake-up event occurs through LIN bus or NWake while the device is in sleep
mode. The LIN bus slave termination circuit and INH are turned on when standby mode is entered. The
application system powers up once INH is turned on, assuming the system is using a voltage regulator
connected through INH. Standby mode is signaled through a low level on RXD.
When EN is set high while the device is in standby mode the device returns to normal mode and the normal
transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
During power up if EN is low the device goes into Standby mode and if EN is high the device goes into Normal
mode. EN has an internal pulldown resistor, so if the pin is floating in the system, the internal pulldown will
ensure it is pulled low.
APPLICATION HINT: If the INH output of the SN65HVDA100 is not used to control the system power
management (voltage regulators) and monitor wake-up sources, but sleep mode is used to reduce system
current the RXD pin can be monitored to ensure SN65HVDA100 remains in sleep mode. If the SN65HVDA100
detects an undervoltage on VSUP the RXD pin transitions low and would signal to the software that the
SN65HVDA100 is in standby mode and should be returned to sleep mode to return to the lowest power state.
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9.4.6 Mode Transitions
When the device is transitioning between modes the device needs the time, tMODE_CHANGE, to allow the change to
fully propagate from the EN pin through the device into the new state.
APPLICATION HINT: When using the SN65HVDA100 in systems which are not controlled through the INH
output, but rather are monitoring the RXD pin for a wake-up request, special care should be taken during the
mode transitions. The output of the RXD pin is indeterminate for the transition period between states as the
receivers are switched. The application software should not look for an edge on the RXD pin indicating a wakeup request until tMODE_CHANGE. This is shown in Figure 3.
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN65HVDA100-Q1 can be used as both a slave device and a master device in a LIN network. The device
comes with the ability to support both remote wake-up requests and local wake-up requests.
10.2 Typical Application
The device comes with an integrated 30-kΩ pullup resistor and series diode for slave applications, and for master
applications an external 1-kΩ pullup with series blocking diode can be used. Figure 14 shows the device being
used in both types of applications.
18
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Typical Application (continued)
VBAT
VSUP
MASTER
NODE
TPSxxxx
VSUP
VDD
NWake
VSUP
INH
VDD
VDD
EN
I/O
2
8
3
Master
Node
Pullup(3)
7
MCU w/o
pullup (2)
VDD I/O
MCU
1k
SN65HVDA100-Q1
LIN
Controller
or
SCI/UART(1)
RXD
TXD
GND
LIN Bus
TMS470
LIN
1
6
4
5
220 pF
VSUP
SLAVE
NODE
TPSxxxx
VSUP
VDD
NWake
INH
VDD
VSUP
EN
I/O
2
8
3
7
MCU w/o
pullup(2)
VDD I/O
MCU
SN65HVDA100-Q1
TMS470
LIN
Controller
or
SCI/UART(1)
GND
RXD
TXD
LIN
1
4
6
5
220 pF
(1)
RXD on MCU or LIN slave has internal pullup, no external pullup resistor is needed.
(2)
RXD on MCU or LIN slave without internal pullup, requires external pullup resistor.
(3)
Master node applications require an external 1-kΩ pullup resistor and serial diode.
Figure 14. SN65HVDA100-Q1 Application Diagram
10.2.1 Design Requirements
For this design, use these requirements:
1. RXD on MCU or LIN Slave has internal pullup, no external pullup resistor is needed.
2. RXD on MCU or LIN Slave without internal pullup, requires external pullup resistor.
3. Master Node applications require an external 1-kΩ pullup resistor and serial diode.
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Typical Application (continued)
10.2.2 Detailed Design Procedure
The RXD output structure is an open-drain output stage. This allows the SN65HVDA100-Q1 to be used with 3.3V and 5-V I/O microcontrollers. If the RXD pin of the microcontroller does not have an integrated pullup, an
external pullup resistor to the microcontroller I/O supply voltage is required.
The VSUP pin of the device should be decoupled with a 100-nF capacitor as close to the supply pin of the device
as possible.
The NWAKE pin is a high voltage wake-up input to the device. If this pin is not being used it should be tied to
VSUP.
10.2.3 Application Curves
Figure 15 and Figure 16 show the propagation delay from the TXD pin to the LIN pin for both the recessive-todominant and dominant-to-recessive states under lightly loaded conditions.
Figure 15. Dominant-to-Recessive Propagation Delay
20
Figure 16. Recessive-to-Dominant Propagation Delay
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11 Power Supply Recommendations
The SN65HVDSA100-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from
7 V to 27 V. A 100-nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.
12 Layout
12.1 Layout Guidelines
Pin 1 is the RXD output of the SN65HVDA100-Q1. The pin is an open-drain output and requires an external
pullup resistor in the range of 1 kΩ to 10 kΩ to function properly. If the microprocessor paired with the transceiver
does not have an integrated pullup, an external resistor should be placed between RXD and the regulated
voltage supply for the microprocessor.
Pin 2 is the EN input pin for the device that is used to place the device in low power sleep mode. If this feature is
not used on the device, the pin should be pulled high to the regulated voltage supply of the microprocessor
through a series 1-kΩ to 10-kΩ series resistor. Additionally, a series resistor may be placed on the pin to limit the
current on the digital lines in the case of a overvoltage fault.
Pin 3 is a high-voltage local wake up input pin. The device is typically externally controlled by a normally open
switch tied between NWAKE and ground. When the momentary switch is pressed the NWAKE pin is pulled to
ground signaling a local wake-up event. A series resistor between VBATT and the switch, and NWAKE and the
switch should be placed to limit current. If the NWAKE local wake-up feature is not used, the pin can be tied to
VSUP through a 1-kΩ to 10-kΩ pullup resistor.
Pin 4 is the transmit input signal to the device. A series resistor can be placed to limit the input current to the
device in the case of a overvoltage on this pin. Also, a capacitor to ground can be placed close to the input pin of
the device to filter noise.
Pin 5 is the ground connection of the device. This pin should be tied to a ground plane through a short trace with
the use of two vias to limit total return inductance.
Pin 6 is the LIN bus connection of the device. For slave applications a 220-pF bus capacitor is implemented. For
master applications an additional series resistor and blocking diode should be placed between the LIN pin and
the VSUP pin.
Pin 7 is the supply pin for the device. A 100-nF decoupling capacitor should be placed as close to the device as
possible.
Pin 8 is a high-voltage output pin that may be used to control the local power supplies. If this feature is not used
the pin may be left floating.
NOTE
All ground and power connections should be made as short as possible and use at least
two vias to minimize the total loop inductance.
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12.2 Layout Example
V…C
R1
8
1
RXD
R7
INH
VSUP
7
R4
U1
SN65HVDA100-Q1
V…C
6
GND
4
5
GND
GND
GND
GND
C1
R6
D3
3
D1
Only needed for
the master node
C3
R5
TXD
C2
D2 R7
2
R3
R2
VSUP EN
Figure 17. Layout Schematic
22
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13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN65HVDA100QDRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
A100Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Mar-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65HVDA100QDRQ1
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Mar-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVDA100QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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