Texas Instruments | Low-Voltage 8-Bit, I2C and SMBus I/O Expander (Rev. D) | Datasheet | Texas Instruments Low-Voltage 8-Bit, I2C and SMBus I/O Expander (Rev. D) Datasheet

Texas Instruments Low-Voltage 8-Bit, I2C and SMBus I/O Expander (Rev. D) Datasheet
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TCA6408A
SCPS192D – APRIL 2009 – REVISED JULY 2015
TCA6408A Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output, Reset,
and Configuration Registers
1 Features
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2 Applications
2
I C to Parallel Port Expander
Operating Power-Supply Voltage Range of 1.65 V
to 5.5 V
Allows Bidirectional Voltage-Level Translation and
GPIO Expansion Between 1.8-V, 2.5-V, 3.3-V,
and 5-V I2C Bus and P-Ports
Low Standby Current Consumption of 1 μA
5-V Tolerant I/O Ports
400-kHz Fast I2C Bus
Hardware Address Pin Allows Two TCA6408A
Devices on the Same I2C/SMBus Bus
Active-Low Reset (RESET) Input
Open-Drain Active-Low Interrupt (INT) Output
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power Up With All Channels Configured as Inputs
No Glitch On Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise Immunity at
the SCL and SDA Inputs
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
•
•
•
•
•
•
Servers
Routers (Telecom Switching Equipment)
Personal Computers
Personal Electronics (Gaming Consoles)
Industrial Automation
Products With GPIO-Limited Processors
3 Description
The TCA6408A is a 16-pin device that provides 8-bits
of general purpose parallel input/output (I/O)
expansion for the two-line bidirectional I2C bus (or
SMBus) protocol. This device can operate with a
power supply voltage ranging from 1.65 V to 5.5 V on
both the I2C bus side (VCCI) and on the P-port side
(VCCP). This allows the TCA6408A to interface with
next-generation microprocessors and microcontrollers
on the SDA/SCL side, where supply levels are
dropping down to conserve power. In contrast to the
dropping power supplies of microprocessors and
microcontrollers, some PCB components such as
LEDs remain at a 5-V power supply.
The device supports both 100-kHz (Standard-mode)
and 400-kHz (Fast-mode) clock frequencies. I/O
expanders such as the TCA6408A provide a simple
solution when additional I/Os are needed for
switches, sensors, push-buttons, LEDs, fans, and so
forth.
Device Information(1)
PART NUMBER
TCA6408A
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
VQFN (16)
3.00 mm × 3.00 mm
UQFN (16)
2.60 mm × 1.80 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI
I2C or SMBus Master
(e.g. Processor)
VCCP
SDA
P0
Peripheral
Devices
SCL
P1
INT
P2
x
RESET
P3
x
P4
x
x
TCA6408A
RESET, EN or
Control Inputs
INT or status
outputs
LEDs
Keypad
P5
P6
P7
ADDR
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA6408A
SCPS192D – APRIL 2009 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
6
7
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Reset Timing Requirements .....................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagrams ..................................... 16
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Map...........................................................
18
19
19
23
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 26
10 Power Supply Recommendations ..................... 29
10.1 Power-On Reset Requirements ........................... 29
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2009) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
VIH - Split SCL, SDA and RESET to different rows in the Recommended Operating Conditions table. Max value of
SCL, SDA changed From: 5.5 V To: VCCI............................................................................................................................... 4
2
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SCPS192D – APRIL 2009 – REVISED JULY 2015
5 Pin Configuration and Functions
9
4
13
14
ADDR
VCCI
VCCP
SDA
11
3
10
4
9
SCL
INT
P7
P6
8
12
7
10
15
9
16
8
11
1
2
5
10
3
Exposed
Center
Pad
RESET
P0
P1
P2
SCL
INT
P7
P6
6
7
2
12
P3
GND
P4
P5
11
13
6
14
12
1
8
5
RESET
P0
P1
P2
7
13
GND
P4
P5
14
4
15
3
VCCP
SDA
SCL
INT
P7
P6
P5
P4
16
15
5
16
2
6
1
RSV Package
16-Pin UQFN
Top View
P3
VCCI
ADDR
RESET
P0
P1
P2
P3
GND
RGT Package
16-Pin VQFN
Top View
ADDR
VCCI
VCCP
SDA
PW Package
16-Pin TSSOP
Top View
If used, the exposed center pad must be connected as a secondary ground or left electrically open.
Pin Functions
PIN
NAME
DESCRIPTION
TSSOP
UQFN, VQFN
ADDR
2
16
Address input. Connect directly to VCCP or ground.
GND
8
6
Ground
INT
13
11
Interrupt output. Connect to VCCI through a pull-up resistor.
P0
4
2
P-port input/output (push-pull design structure).
At power on, P0 is configured as an input.
P1
5
3
P-port input/output (push-pull design structure).
At power on, P1 is configured as an input.
P2
6
4
P-port input/output (push-pull design structure).
At power on, P2 is configured as an input.
P3
7
5
P-port input/output (push-pull design structure).
At power on, P3 is configured as an input.
P4
9
7
P-port input/output (push-pull design structure).
At power on, P4 is configured as an input.
P5
10
8
P-port input/output (push-pull design structure).
At power on, P5 is configured as an input.
P6
11
9
P-port input/output (push-pull design structure).
At power on, P6 is configured as an input.
P7
12
10
P-port input/output (push-pull design structure).
At power on, P7 is configured as an input.
RESET
3
1
Active-low reset input. Connect to VCCI through a pull-up resistor, if no active connection is
used.
SCL
14
12
Serial clock bus. Connect to VCCI through a pull-up resistor.
SDA
15
13
Serial data bus. Connect to VCCI through a pull-up resistor.
VCCI
1
15
Supply voltage of I2C bus. Connect directly to the VCC of the external I2C master. Provides
voltage level translation.
VCCP
16
14
Supply voltage of TCA6408A for P-ports
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SCPS192D – APRIL 2009 – REVISED JULY 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (see
(1)
)
MIN
MAX
UNIT
VCCI
Supply voltage for I2C pins
–0.5
6.5
V
VCCP
Supply voltage for P-ports
–0.5
6.5
V
VI
Input voltage (2)
–0.5
6.5
V
VO
Output voltage (2)
–0.5
6.5
V
IIK
Input clamp current
ADDR, RESET, SCL
VI < 0
±20
mA
IOK
Output clamp current
INT
VO < 0
±20
mA
P-port
VO < 0 or VO > VCCP
±20
SDA
VO < 0 or VO > VCCI
±20
Continuous output low current
P-port
VO = 0 to VCCP
50
Continuous output low current
SDA, INT
VO = 0 to VCCI
25
Continuous output high current
P-port
VO = 0 to VCCP
50
IIOK
Input/output clamp current
IOL
IOH
ICC
Tstg
(1)
(2)
mA
mA
Continuous current through GND
200
Continuous current through VCCP
160
Continuous current through VCCI
10
Storage temperature
–65
mA
150
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
VCCI
Supply voltage for I2C pins
1.65
5.5
VCCP
Supply voltage for P-ports
1.65
5.5
SCL, SDA
0.7 × VCCI
VCCI
VIH
High-level input voltage
RESET
0.7 × VCCI
5.5
ADDR, P7–P0
0.7 × VCCP
5.5
SCL, SDA, RESET
–0.5
0.3 × VCCI
ADDR, P7–P0
–0.5
0.3 × VCCP
VIL
Low-level input voltage
IOH
High-level output current
P7–P0
IOL
Low-level output current
P7–P0
TA
Operating free-air temperature
4
–40
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UNIT
V
V
V
10
mA
25
mA
85
°C
Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TCA6408A
TCA6408A
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SCPS192D – APRIL 2009 – REVISED JULY 2015
6.4 Thermal Information
TCA6408A
THERMAL METRIC (1)
PW (TSSOP)
RGT (VQFN)
RSV (UQFN)
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
122
65.5
127.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.4
92.1
62.3
°C/W
RθJB
Junction-to-board thermal resistance
67.1
40.0
48.4
°C/W
ψJT
Junction-to-top characterization parameter
10.8
6.9
2.5
°C/W
ψJB
Junction-to-board characterization parameter
66.5
21.3
48.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SCPS192D – APRIL 2009 – REVISED JULY 2015
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6.5 Electrical Characteristics
over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCP
VIK
Input diode clamp voltage
II = –18 mA
1.65 V to 5.5 V
VPOR
Power-on reset voltage (2)
VI = VCCP or GND, IO = 0
1.65 V to 5.5 V
IOH = –8 mA
P-port high-level output
voltage
VOH
IOH = –10 mA
IOL = 8 mA
P-port low-level output
voltage
VOL
IOL = 10 mA
MIN TYP (1)
–1.2
1.65 V
1.2
2.3 V
1.8
3V
2.6
4.5 V
4.1
1.65 V
1.1
2.3 V
1.7
3V
2.5
4.5 V
4.0
IOL
VOL = 0.4 V
INT
SCL, SDA, RESET
VI = VCCI or GND
ADDR
VI = VCCP or GND
IIH
P-port
VI = VCCP
IIL
P-port
VI = GND
II
Operating
mode
ICC
(ICCI + ICCP)
Standby
mode
V
0.45
2.3 V
0.25
3V
0.25
4.5 V
0.2
1.65 V
0.6
2.3 V
0.3
3V
0.25
3
mA
15
±0.1
1.65 V to 5.5 V
±0.1
1.65 V to 5.5 V
μA
1
μA
1
μA
VI on SCL, SDA and RESET = VCCI or
GND,
VI on P-Port and ADDR = VCCP or GND,
IO = 0, I/O = inputs,
fSCL = 0
SCL, SDA,
RESET
One input at VCCI – 0.6 V,
Other inputs at VCCI or GND
1.65 V to 5.5 V
25
μA
P-port,
ADDR
One input at VCCP – 0.6 V,
Other inputs at VCCP or GND
1.65 V to 5.5 V
80
μA
1.65 V to 5.5 V
6
7
pF
7
8
7.5
8.5
SCL
VI = VCCI or GND
SDA
VIO = VCCI or GND
P-port
VIO = VCCP or GND
6
0.2
3
SCL, SDA,
P-port,
ADDR,
RESET
Ci
(1)
(2)
V
VI on SDA and RESET= VCCI or GND,
VI on P-port and ADDR = VCCP or GND,
IO = 0, I/O = inputs,
fSCL = 400 kHz
ΔICCP
Cio
V
SDA,
P-port,
ADDR,
RESET
Additional
current in
standby
mode
ΔICCI
1.4
1.65 V
1.65 V to 5.5 V
UNIT
V
1
4.5 V
SDA
MAX
3.6 V to 5.5 V
10
20
2.3 V to 3.6 V
6.5
15
1.65 V to 2.3 V
4
9
3.6 V to 5.5 V
1.5
7
2.3 V to 3.6 V
1
3.2
1.65 V to 2.3 V
0.5
1.7
1.65 V to 5.5 V
μA
pF
All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408A in a reset condition until VCCP has reached
VPOR. At that time, the reset condition is released, and the TCA6408A registers and I2C/SMBus state machine initialize to their default
states. After that, VCCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.
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SCPS192D – APRIL 2009 – REVISED JULY 2015
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 18)
STANDARD MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial data setup time
FAST MODE
I2C BUS
MAX
0
400
kHz
μs
0.6
4.7
μs
1.3
0
50
0
250
2
UNIT
MIN
50
ns
100
0
ns
tsdh
I C serial data hold time
ticr
I2C input rise time
1000
20 + 0.1Cb
300
ticf
I2C input fall time
300
20 + 0.1Cb
300
ns
tocf
I2C output fall time, 10-pF to 400-pF bus
300
20 + 0.1Cb
300
μs
tbuf
I2C bus free time between Stop and Start
4.7
1.3
μs
tsts
I2C Start or repeater Start condition setup time
4.7
0.6
μs
tsth
I2C Start or repeater Start condition hold time
4
0.6
μs
2
0
4
ns
ns
μs
tsps
I C Stop condition setup time
tvd(data)
Valid data time, SCL low to SDA output valid
1
0.6
1
μs
tvd(ack)
Valid data time of ACK condition, ACK signal from SCL low to
SDA (out) low
1
1
μs
6.7 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 21)
STANDARD MODE
I2C BUS
MIN
FAST MODE
I2C BUS
MAX
MIN
UNIT
MAX
tW
Reset pulse duration
4
4
ns
tREC
Reset recovery time
0
0
ns
tRESET
Time to reset
600
600
ns
6.8 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 18)
PARAMETER
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
FROM
(INPUT)
TO
(OUTPUT)
P-Port
INT
4
4
μs
SCL
INT
4
4
μs
400
ns
MIN
MAX
MIN
UNIT
MAX
tiv
Interrupt valid time
tir
Interrupt reset delay time
tpv
Output data valid
SCL
P7–P0
tps
Input data setup time
P-Port
SCL
0
0
ns
tph
Input data hold time
P-Port
SCL
300
300
ns
400
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6.9 Typical Characteristics
TA = 25°C (unless otherwise noted)
22
2000
Supply Current, ICC (µA)
18
Supply Current, ICC (nA)
VCC = 5.5 V
20
VCC = 5 V
16
14
12
10
VCC = 3.3 V
8
VCC = 2.5 V
6
4
VCC = 1.8 V
2
VCC = 1.65 V
0
-40
-15
10
35
1800
VCC = 5.5 V
1600
VCC = 5 V
1400
1200
VCC = 3.3 V
1000
VCC = 2.5 V
800
600
VCC = 1.8 V
400
VCC = 1.65 V
200
60
0
–40
85
–15
10
35
60
85
Temperature, TA (°C)
Temperature, TA (°C)
Figure 1. Supply Current vs Temperature
Figure 2. Standby Supply Current vs Temperature
22
30
VCC = 1.65 V
Sink Current, ISINK (mA)
Supply Current, ICC (µA)
20
18
16
14
12
10
8
6
4
25
TA = –40°C
20
TA = 25°C
15
10
TA = 85°C
5
2
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.1
0.2
0.3
0.5
0.4
0.6
Supply Voltage, VCC (V)
Output Low Voltage, VOL (V)
Figure 3. Supply Current vs Supply Voltage
Figure 4. I/O Sink Current vs Output Low Voltage
50
VCC = 1.8 V
VCC = 2.5 V
TA = –40°C
30
Sink Current, ISINK (mA)
Sink Current, ISINK (mA)
35
25
20
TA = 25°C
15
10
TA = 85°C
5
0
0.0
8
0
0.1
0.2
0.3
0.4
0.5
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.6
TA = –40°C
0.1
0.2
0.3
0.4
0.5
0.6
Output Low Voltage, VOL (V)
Output Low Voltage, VOL (V)
Figure 5. I/O Sink Current vs Output Low Voltage
Figure 6. I/O Sink Current vs Output Low Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
60
70
VCC = 5.0 V
Sink Current, ISINK (mA)
Sink Current, ISINK (mA)
VCC = 3.3 V
TA = –40°C
50
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.1
0.2
0.3
0.5
0.4
60
50
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.6
TA = –40°C
0.1
0.2
0.3
0.4
0.5
0.6
Output Low Voltage, VOL (V)
Output Low Voltage, VOL (V)
Figure 7. I/O Sink Current vs Output Low Voltage
Figure 8. I/O Sink Current vs Output Low Voltage
250
Sink Current, ISINK (mA)
VCC = 5.5 V
60
Output Low Voltage, VOL (mV)
70
TA = –40°C
50
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VCC = 1.8 V, ISINK = 10 mA
200
150
VCC = 5 V, ISINK = 10 mA
100
VCC = 1.8 V, ISINK = 1 mA
50
VCC = 5 V, ISINK = 1 mA
0
-40
-15
10
35
60
85
Output Low Voltage, VOL (V)
Temperature, TA (°C)
Figure 9. I/O Sink Current vs Output Low Voltage
Figure 10. I/O Low Voltage vs Temperature
25
VCC = 1.65 V
Source Current, ISOURCE (mA)
Source Current, ISOURCE (mA)
20
TA = –40°C
15
TA = 25°C
10
TA = 85°C
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VCC = 1.8 V
TA = –40°C
20
15
TA = 25°C
10
TA = 85°C
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VCCP – VOH (V)
VCCP – VOH (V)
Figure 11. I/O Source Current vs Output High Voltage
Figure 12. I/O Source Current vs Output High Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
50
VCC = 2.5 V
TA = –40°C
30
Source Current, ISOURCE (mA)
Source Current, ISOURCE (mA)
35
25
20
TA = 25°C
15
TA = 85°C
10
5
0
0.0
0.1
0.2
0.3
0.4
0.5
VCC = 3.3 V
30
TA = 25°C
20
TA = 85°C
10
0
0.6
0.0
0.1
VCCP – VOH (V)
Source Current, ISOURCE (mA)
Source Current, ISOURCE (mA)
40
TA = 25°C
30
TA = 85°C
10
0
0.0
0.1
0.2
0.3
0.4
0.4
0.5
0.6
70
50
20
0.3
Figure 14. I/O Source Current vs Output High Voltage
TA = –40°C
VCC = 5.0 V
0.2
VCCP – VOH (V)
Figure 13. I/O Source Current vs Output High Voltage
60
TA = –40°C
40
0.5
0.6
VCC = 5.5 V
TA = –40°C
60
50
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.1
VCCP – VOH (V)
0.2
0.3
0.4
0.5
0.6
VCCP – VOH (V)
Figure 15. I/O Source Current vs Output High Voltage
Figure 16. I/O Source Current vs Output High Voltage
350
ISOURCE = –10 mA
VCC – VOH (mV)
300
250
VCC = 1.8 V
200
VCC = 5 V
150
100
50
0
-40
-15
10
35
60
85
Temperature, TA (°C)
Figure 17. I/O High Voltage vs Temperature
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7 Parameter Measurement Information
VCCI
RL = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
(see Figure 9)
Address
Bit 7
(MSB)
Stop
Start
Condition Condition
(P)
(S)
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 ´ VCCI
SCL
0.3 ´ VCCI
ticr
ticf
tbuf
tvd
tsp
tocf
tvd
tsts
tsps
SDA
0.7 ´ VCCI
0.3 ´ VCCI
ticr
ticf
tsth
tsdh
tsds
tvd(ack)
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
2
1
I C address
2
Input register port data
A.
CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 18. I2C Interface Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCCI
RL = 4.7 kW
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
0
1
0
0
0
0
AD
DR
1
A
1
2
3
4
5
6
7
8
A
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
tiv
A
tsps
A
Data
Into
Port
Address
Data 1
0.5 ´ VCCI
INT
SCL
Data 2
0.7 ´ VCCI
R/W
tiv
A
0.3 ´ VCCI
tir
0.5 ´ VCCP
Pn
0.5 ´ VCCI
INT
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 19. Interrupt Load Circuit And Voltage Waveforms
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Parameter Measurement Information (continued)
500 W
Pn
DUT
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
SCL
P0
A
P3
0.7 ´ VCCP
0.3 ´ VCCI
Slave
ACK
SDA
tpv
(see Note B)
Pn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
SCL
0.7 ´ VCCI
P0
A
tps
P3
0.3 ´ VCCI
tph
Pn
0.5 ´ VCCP
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 20. P-Port Load Circuit And Timing Waveforms
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Parameter Measurement Information (continued)
VCCI
RL = 1 kW
500 W
Pn
SDA
DUT
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 ´ VCCI
tRESET
VCCP/2
RESET
tREC
tREC
tW
VCCP/2
Pn
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 21. Reset Load Circuits And Voltage Waveforms
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8 Detailed Description
8.1 Overview
The bidirectional voltage-level translation in the TCA6408A is provided through VCCI. VCCI should be connected to
the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6408A. The voltage
level on the P-port of the TCA6408A is determined by VCCP.
The TCA6408A consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity
Inversion (active high) Register. At power on, the I/Os are configured as inputs. However, the system master can
enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or
output is kept in the corresponding Input or Output Register. The polarity of the Input Port Register can be
inverted with the Polarity Inversion Register. All registers can be read by the system master.
The system master can reset the TCA6408A in the event of a timeout or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
The TCA6408A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port Register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA6408A can remain a simple slave device.
The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low
device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to
share the same I2C bus or SMBus.
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8.2 Functional Block Diagrams
13
INT
Interrupt
Logic
LP Filter
2
ADDR
14
SCL
15
SDA
I2C Bus
Control
Input
Filter
1
VCCI
3
RESET
8 Bits
I/O Port
P7–P0
Write Pulse
Read Pulse
16
VCCP
Shift
Register
Power-On
Reset
8
GND
A.
All pin numbers shown are for the PW package.
B.
All I/Os are set to inputs at reset.
Figure 22. Logic Diagram (Positive Logic)
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Functional Block Diagrams (continued)
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
VCCP
Configuration
Register
D
Q
Q1
FF
Write Configuration
Pulse
CK Q
D
Q
FF
Write Pulse
P0 to P7
CK Q
Output
Port
Register
Q2
Input
Port
Register
GND
Input Port
Register Data
Q
D
FF
Read Pulse
ESD Protection Diode
CK Q
To INT
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity Pulse
CK Q
Polarity
Inversion
Register
A.
On power up or reset, all registers return to default values.
Figure 23. Simplified Schematic of P0 to P7
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8.3 Feature Description
8.3.1 Voltage Translation
Table 1 shows some common supply voltage options for voltage translation between the I2C bus and the P-ports
of the TCA6408A.
Table 1. Voltage Translation
VCCI
(SCL AND SDA OF I2C MASTER)
(V)
VCCP
(P-PORT)
(V)
1.8
1.8
1.8
2.5
1.8
3.3
1.8
5
2.5
1.8
2.5
2.5
2.5
3.3
2.5
5
3.3
1.8
3.3
2.5
3.3
3.3
3.3
5
5
1.8
5
2.5
5
3.3
5
5
8.3.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.3.3 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to VCCP or VCCI, depending on the
application. INT should be connected to the voltage source of the device that requires the interrupt information.
8.3.4 Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6408A registers and
I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),
the I/O levels at the P-port can be changed externally or through the master. This input requires a pull-up resistor
to VCCI, if no active connection is used.
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8.4 Device Functional Modes
8.4.1 Power-On Reset (POR)
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408A in a reset condition
until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6408A registers and
I2C/SMBus state machine initialize to their default states. After that, VCCP must be lowered to below VPORF and
back up to the operating voltage for a power-reset cycle.
8.4.2 Powered-Up
When power has been applied to both VCCP and VCCI and a POR has taken place, the device is in a functioning
mode. The device will always be ready to receive new requests via the I2C bus.
8.5 Programming
8.5.1 I2C Interface
The TCA6408A has a standard bidirectional I2C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I2C bus has a specific device address to
differentiate between other slave devices that are on the same I2C bus. Many slave devices will require
configuration upon startup to set the behavior of the device. This is typically done when the master accesses
internal register maps of the slave, which have unique register addresses. A device can have one or multiple
registers where data is stored, written, or read.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I2C lines. (For further details, refer to I2C Pull-up Resistor Calculation (SLVA689).) Data
transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high
after a STOP condition.
The following is the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver.
– Master-transmitter sends data to slave-receiver.
– Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter.
– Master-receiver sends the requested register to read to slave-transmitter.
– Master-receiver receives data from the slave-transmitter.
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Programming (continued)
– Master-receiver terminates the transfer with a STOP condition.
SCL
SDA
Data Transfer
START
Condition
STOP
Condition
Figure 24. Definition of Start and Stop Conditions
SDA line stable while SCL line is high
SCL
1
0
1
0
1
0
1
0
ACK
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
SDA
Byte: 1010 1010 ( 0xAAh )
Figure 25. Bit Transfer
Table 2. Interface Definition
BYTE
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C slave address
L
H
L
L
L
L
ADDR
R/W
I/O data bus
P7
P6
P5
P4
P3
P2
P1
P0
8.5.2 Bus Transactions
Data must be sent to and received from the slave devices, and this is accomplished by reading from or writing to
registers in the slave device.
Registers are locations in the memory of the slave which contain information, whether it be the configuration
information or some sampled data to send back to the master. The master must write information to these
registers in order to instruct the slave device to perform a task.
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Programming (continued)
While it is common to have registers in I2C slaves, note that not all slave devices will have registers. Some
devices are simple and contain only 1 register, which may be written to directly by sending the register data
immediately after the slave address, instead of addressing a register. An example of a single-register device
would be an 8-bit I2C switch, which is controlled via I2C commands. Since it has 1 bit to enable or disable a
channel, there is only 1 register needed, and the master merely writes the register data after the slave address,
skipping the register number.
8.5.2.1 Writes
To write on the I2C bus, the master will send a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master
will then send the register address of the register to which it wishes to write. The slave will acknowledge again,
letting the master know it is ready. After this, the master will start sending the register data to the slave until the
master has sent all the data necessary (which is sometimes only a single byte), and the master will terminate the
transmission with a STOP condition.
Figure 26 shows an example of writing a single byte to a slave register.
Master controls SDA line
Slave controls SDA line
Write to one register in a device
Register Address N (8 bits)
Device (Slave) Address (7 bits)
S
0
1
0
0
0
0
START
AD
DR
0
R/W=0
A
Data Byte to Register N (8 bits)
B7 B6 B5 B4 B3 B2 B1 B0
ACK
D7 D6 D5 D4 D3 D2 D1 D0
A
ACK
A
ACK
P
STOP
Figure 26. Write to Register
<br/>
Master controls SDA line
Slave controls SDA line
Register Address 0x02 (8 bits)
Device (Slave) Address (7 bits)
S
0
START
1
0
0
0
0
AD
DR
0
R/W=0
A
0
ACK
0
0
0
0
0
1
Data Byte to Register 0x02 (8 bits)
0
A
D7 D6 D5 D4 D3 D2 D1 D0
ACK
A
ACK
P
STOP
Figure 27. Write to the Polarity Inversion Register
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Programming (continued)
8.5.2.2 Reads
Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave,
the master must first instruct the slave which register it wishes to read from. This is done by the master starting
off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. Once the slave acknowledges this
register address, the master will send a START condition again, followed by the slave address with the R/W bit
set to 1 (signifying a read). This time, the slave will acknowledge the read request, and the master will release
the SDA bus but will continue supplying the clock to the slave. During this part of the transaction, the master will
become the master-receiver, and the slave will become the slave-transmitter.
The master will continue to send out the clock pulses, but will release the SDA line so that the slave can transmit
data. At the end of every byte of data, the master will send an ACK to the slave, letting the slave know that it is
ready for more data. Once the master has received the number of bytes it is expecting, it will send a NACK,
signaling to the slave to halt communications and release the bus. The master will follow this up with a STOP
condition.
Figure 28 shows an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Read from one register in a device
Register Address N (8 bits)
Device (Slave) Address (7 bits)
S
0
1
0
0
0
0
START
AD
DR
0
R/W=0
A
Data Byte from Register N (8 bits)
Device (Slave) Address (7 bits)
B7 B6 B5 B4 B3 B2 B1 B0
ACK
A
Sr
ACK
0
1
0
0
0
0
AD
DR
1
A
R/W=1
Repeated START
D7 D6 D5 D4 D3 D2 D1 D0 NA
ACK
NACK
P
STOP
Figure 28. Read from Register
1
SCL
2
3
4
5
6
7
R
9
Data From Port
Slave Address
S 0
SDA
1
0
0
0
AD
0 DR 1
Start
Condition
R/W
Data From Port
Data 1
A
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT is cleared
by Read from Port
INT
tiv
Stop not needed
to clear INT
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port Register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P-port (see Figure 28).
Figure 29. Read from Input Port Register
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8.6 Register Map
8.6.1 Device Address
The address of the TCA6408A is shown in Figure 30.
Slave Address
0
0
1
0
Fixed
0
0 AD
DR R/W
Programmable
Figure 30. TCA6408A Address
Table 3. Address Reference
ADDR
I2C BUS SLAVE ADDRESS
L
32 (decimal), 20 (hexadecimal)
H
33 (decimal), 21 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the Control Register in the TCA6408A. Two bits of this data byte will state both the operation (read or
write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected. This
register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
B7
B6
B5
B4
B3
B2
B1
B0
Figure 31. Control Register Bits
Table 4. Command Byte
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
BYTE
(HEX)
0
0
0
0
0
0
0
0
00
Input Port
Read byte
xxxx xxxx
0
0
0
0
0
0
0
1
01
Output Port
Read/write byte
1111 1111
0
0
0
0
0
0
1
0
02
Polarity Inversion
Read/write byte
0000 0000
0
0
0
0
0
0
1
1
03
Configuration
Read/write byte
1111 1111
REGISTER
PROTOCOL
POWER-UP
DEFAULT
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8.6.3 Register Descriptions
The Input Port Register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration Register. They act only on read operation. Writes to this
register have no effect. The default value (X) is determined by the externally applied logic level. Before a read
operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port
Register will be accessed next.
Table 5. Register 0 (Input Port Register)
BIT
I-7
I-6
I-5
I-4
I-3
I-2
I-1
I-0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port Register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration Register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 6. Register 1 (Output Port Register)
BIT
O-7
O-6
O-5
O-4
O-3
O-2
O-1
O-0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion Register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
Register. If a bit in this register is set (written with 1), the polarity of the corresponding port pin is inverted. If a bit
in this register is cleared (written with a 0), the original polarity of the corresponding port pin is retained.
Table 7. Register 2 (Polarity Inversion Register)
BIT
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N-0
DEFAULT
0
0
0
0
0
0
0
0
The Configuration Register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 8. Register 3 (Configuration Register)
24
BIT
C-7
C-6
C-5
C-4
C-3
C-2
C-1
C-0
DEFAULT
1
1
1
1
1
1
1
1
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA6408A will have this device connected as a slave to an I2C master (processor), and the
I2C bus may contain any number of other slave devices. The TCA6408A will be in a remote location from the
master, placed close to the GPIOs to which the master needs to monitor or control.
A typical application of the TCA6408A will operate with a lower voltage on the master side (VCCI), and a higher
voltage on the P-port side (VCCP). The P-ports can be configured as outputs connected to inputs of devices such
as enable, reset, power select, the gate of a switch, and LEDs. The P-ports can also be configured as inputs to
receive data from interrupts, alarms, status outputs, or push buttons.
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9.2 Typical Application
Figure 32 shows an application in which the TCA6408A can be used.
VCCI VCCP
VCCI
(1.8 V)
VCCI VCCP
14
SCL
15
P0
SDA
13
INT
3
RESET
SCL
Master
Controller SDA
INT
GND
16
1
10 kW
(´ 4)
VCC
RESET
100 kW (´ 3)
ALARM
(see Note D)
Subsystem 1
(e.g., Alarm)
4
A
5
P1
ENABLE
B
TCA6408A
P2
2
ADDR
P3
P4
P5
P6
P7
6
7
9
Keypad
10
11
12
GND
8
A.
Device address configured as 0100000 for this example.
B.
P0 and P2–P4 are configured as inputs.
C.
P1 and P5–P7 are configured as outputs.
D.
Resistors are required for inputs (on P-port) that may float. If a driver to an input will never let the input float, a resistor
is not needed. Outputs (in the P-port) do not need pull-up resistors.
Figure 32. Typical Application Schematic
9.2.1 Design Requirements
Table 9. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
2
I C input voltage (VCCI)
1.8 V
P-port input/output voltage (VCCP)
5V
Output current rating, P-port sinking (IOL)
Output current rating, P-port sourcing (IOH)
I2C bus clock (SCL) speed
26
25 mA
10 mA
400 kHz
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9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL:
Rp(min) =
VCC - VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9538, Ci for SCL or
Cio for SDA, the capacitance of wires, connections, and traces, and the capacitance of additional slaves on the
bus.
9.2.2.1 Minimizing ICC When I/O is Used to Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 32. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs that
must minimize current consumption, such as battery power applications, should consider maintaining the I/O pins
greater than or equal to VCC when the LED is off.
Figure 33 shows a high-value resistor in parallel with the LED. Figure 34 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
VCC
LED
100 kΩ
VCC
Px
Figure 33. High-Value Resistor in Parallel With LED
3.3 V
5V
LED
VCC
Px
Figure 34. Device Supplied by a Low Voltage
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9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC <= 2
0.2
0
0
0
50
100
150
200
250
Cb (pF)
300
350
400
450
0.5
1
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
5.5
D009
VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VCC > 2 V
Standard-mode: fSCL= 100 kHz, tr = 1 µs
Fast-mode: fSCL= 400 kHz, tr= 300 ns
Figure 35. Maximum Pullup Resistance (Rp(max)) vs Bus
Capacitance (Cb)
28
0
D008
Figure 36. Minimum Pullup Resistance (Rp(min)) vs Pullup
Reference Voltage (VCC)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6408A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 37 and Figure 38.
VCC
Ramp-Up
Re-Ramp-Up
Ramp-Down
tTRR_GND
Time
tRT
Time to Re-Ramp
tFT
tRT
Figure 37. VCC is Lowered Below 0.2 V Or 0 V and then Ramped Up to VCC
VCC
Ramp-Down
Ramp-Up
tTRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
tFT
tRT
Figure 38. VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC
Table 10 specifies the performance of the power-on reset feature for TCA6408A for both types of power-on reset.
Table 10. Recommended Supply Sequencing and Ramp Rates at TA = 25°C (1)
PARAMETER
MIN
TYP
MAX
UNIT
tFT
Fall rate
See Figure 37
0.1
2000
ms
tRT
Rise rate
See Figure 37
0.1
2000
ms
tRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 37
1
μs
tRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 38
1
μs
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 39
1.2
V
tGW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 39
10
μs
VPORF
Voltage trip point of POR on falling VCC
VPORR
Voltage trip point of POR on fising VCC
(1)
0.7
V
1.4
V
Not tested. Specified by design.
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tGW)
and height (tGH) are dependent on each other. The bypass capacitance, source impedance, and device
impedance are factors that affect power-on reset performance. Figure 39 and Table 10 provide more information
on how to measure these specifications.
VCC
tGH
Time
tGW
Figure 39. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 40 and Table 10 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 40. VPOR
30
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA6408A, common PCB layout practices should be followed, but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCCP pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors should be placed as close to the TCA6408A as possible. These best practices are shown in Layout
Example.
For the layout example provided in Layout Example, it would be possible to fabricate a PCB with only 2 layers by
using the top layer for signal routing and the bottom layer as a split plane for power (VCCI and VCCP) and ground
(GND). However, a 4-layer board is preferable for boards with higher density signal routing. On a 4-layer PCB, it
is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and
dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and
ground, vias are placed directly next to the surface mount component pad which needs to attach to VCCI, VCCP, or
GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used
when a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated
in Layout Example.
11.2 Layout Example
= Via to GND Plane
0402
Cap
0402
Cap
To CPU/MCU
VCCI
VCCP
ADDR
SDA
RST
SCL
INT
P0
TCA6408A
P1
P7
P2
P6
P3
P5
GND
P4
Figure 41. Example Layout (PW Package)
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TCA6408APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PH408A
TCA6408ARGTR
ACTIVE
VQFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZVU
TCA6408ARSVR
ACTIVE
UQFN
RSV
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
ZVU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCA6408A :
• Automotive: TCA6408A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TCA6408APWR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TCA6408ARGTR
VQFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TCA6408ARSVR
UQFN
RSV
16
3000
177.8
12.4
2.0
2.8
0.7
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TCA6408APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
TCA6408ARGTR
VQFN
RGT
16
3000
367.0
367.0
35.0
TCA6408ARSVR
UQFN
RSV
16
3000
202.0
201.0
28.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016A
VQFN - 1 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
1.45 0.1
(0.2) TYP
5
12X 0.5
8
EXPOSED
THERMAL PAD
4
9
4X
1.5
SYMM
17
1
12
16X
PIN 1 ID
(OPTIONAL)
13
16
0.1
0.05
SYMM
16X
0.30
0.18
C A B
0.5
0.3
4219032/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
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EXAMPLE BOARD LAYOUT
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.45)
SYMM
16
13
16X (0.6)
1
12
16X (0.24)
SYMM
17
(0.475)
TYP
(2.8)
12X (0.5)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.475) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219032/A 02/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.34)
13
16
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
SCALE 5.000
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
B
A
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
5
(0.13) TYP
8
15X
4
0.45
0.35
9
SYMM
2X 1.2
12X 0.4
1
12
16
0.55
0.45
16X
0.25
0.15
0.07
0.05
C A B
13
PIN 1 ID
(45 X 0.1)
4220314/B 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
1
16X (0.2)
SYMM
12X (0.4)
(R0.05) TYP
(2.4)
9
4
15X (0.6)
8
5
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4220314/B 05/2019
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
13
16
16X (0.2)
12
1
SYMM
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/B 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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