Texas Instruments | SNx5HVD08 Wide Supply Range RS-485 Transceiver (Rev. D) | Datasheet | Texas Instruments SNx5HVD08 Wide Supply Range RS-485 Transceiver (Rev. D) Datasheet

Texas Instruments SNx5HVD08 Wide Supply Range RS-485 Transceiver (Rev. D) Datasheet
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SN75HVD08, SN65HVD08
SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
SNx5HVD08 Wide Supply Range RS-485 Transceiver
1 Features
3 Description
•
•
•
The SN65HVD08 combines a 3-state differential line
driver and differential line receiver designed for
balanced data transmission and interoperation with
ANSI TIA/EIA-485-A and ISO-8482E standardcompliant devices.
1
•
•
•
•
Operates With a 3-V to 5.5-V Supply
Consumes Less Than 90-mW Quiescent Power
Open-Circuit, Short-Circuit, and Idle-Bus Failsafe
Receiver
1/8th Unit-Load (up to 256 nodes on the bus)
Bus-Pin ESD Protection Exceeds 16-kV HBM
Driver Output Voltage Slew-Rate Limited for
Optimum Signal Quality at 10 Mbps
Electrically Compatible With ANSI TIA/EIA-485
Standard
2 Applications
•
•
•
•
•
Data Transmission With Remote Stations
Powered From the Host
Isolated Multipoint Data Buses
Industrial Process Control Networks
Point-of-Sale Networks
Electric Utility Metering
The wide supply voltage range and low quiescent
current requirements allow the SN65HVD08s to
operate from a 5-V power bus in the cable with as
much as a 2-V line voltage drop. Busing power in the
cable can alleviate the need for isolated power to be
generated at each connection of a ground-isolated
bus.
The driver differential outputs and receiver differential
inputs connect internally to form a differential
input/output (I/O) bus port that is designed to offer
minimum loading to the bus whenever the driver is
disabled or not powered. The drivers and receivers
have active-high and active-low enables respectively,
which can be externally connected together to
function as a direction control.
Device Information(1)
PART NUMBER
SN75HVD08,
SN65HVD08
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Schematic
Remote
(One of n Shown)
Host
5 V Power
Direct
Connection
to Host
Isolation
Barrier
SN65HVD08
5 V Return
Power Bus and Return Resistance
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75HVD08, SN65HVD08
SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
3
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Driver Switching Characteristics ...............................
Receiver Switching Characteristics...........................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision C (July 2006) to Revision D
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
5 Pin Configuration and Functions
D or P Package
8-Pin SOIC or PDIP
Top View
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
A
6
Bus input /
output
Driver output and receiver input (complementary to B)
B
7
Bus input /
output
Driver output and receiver input (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Driver enable high
GND
5
Reference
potential
R
1
RE
2
Digital input
Receiver enable low
VCC
8
Supply
3-V to 5.5-V supply
Local device ground
Digital output Receive data output
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
(2)
MIN
MAX
UNIT
–0.3
6
V
–9
14
V
Input voltage at D, DE, R or RE
–0.5
VCC + 0.5
V
Voltage input, transient pulse, A and B, through 100 Ω
–25
25
V
Receiver ouput current, IO
–11
11
mA
150
°C
150
°C
Supply voltage, VCC
Voltage at A or B
Maximum Junction Temperature, TJ
Storage Temperature, TSTG
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
A, B, and GND
16000
All pins
4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
Supply voltage, VCC
Input voltage at any bus terminal (separately or common mode), VI
High-level input voltage, VIH
V
12
V
2.25
VCC
0
0.8
–12
12
Driver
V
mA
–8
Driver
60
Receiver
Operating free-air temperature, TA
(1)
–60
Receiver
Low-level output current, IOL
UNIT
–7
Differential input voltage, VID
High-level output current, IOH
MAX
5.5
(1)
Driver, driver enable, and receiver enable inputs
Low-level input voltage, VIL
NOM
3
8
SN75HVD08
0
70
SN65HVD08
–40
85
mA
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
6.4 Thermal Information
SN65HVD08, SN75HVD08
THERMAL METRIC (1)
D (SOIC)
P (PDIP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
175.4
125
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.6
34.9
°C/W
RθJB
Junction-to-board thermal resistance
45.1
23.7
°C/W
ψJT
Junction-to-top characterization parameter
10.1
12.1
°C/W
ψJB
Junction-to-board characterization parameter
44.4
23.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
|VOD|
Driver differential output voltage magnitude
RL= 60 Ω, 375 Ω on each output to 7 V to 12 V, See Figure 7
Δ|VOD|
Change in magnitude of driver differential
output voltage
RL= 54 Ω
VOC(PP)
Peak-to-peak driver common-mode output
voltage
Center of two 27-Ω load
resistors, See Figure 8
VIT+
Positive-going receiver differential input
voltage threshold
VIT-
Negative-going receiver differential input
voltage threshold
Vhys
Receiver differential input voltage threshold
hysteresis(VIT+ - VIT-)
VOH
Receiver high-level output voltage
IOH = -8 mA
VOL
Receiver low-level output voltage
IOL = 8 mA
IIH
Driver input, driver enable, and receiver
enable high-level input current
IIL
Driver input, driver enable, and receiver
enable low-level input current
IOS
Driver short-circuit output current
4
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TYP
MAX
UNIT
1.5
VCC
V
–0.2
0.2
V
0.5
V
–10
–200
mV
35
mV
2.4
7 V < VO < 12 V
mV
V
0.4
V
–100
100
µA
–100
100
µA
–265
265
mA
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SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
Electrical Characteristics (continued)
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
VI = 12 V
II
Bus input current (disabled driver)
Supply current
UNIT
130
VI = -7 V
–100
VI = 12 V, VCC = 0 V
µA
130
VI = -7 V. VCC = 0 V
ICC
MAX
–100
Receiver enabled, driver
disabled, no load
10
Driver enabled, receiver
disabled, no load
16
mA
Both disabled
Both enabled, no load
5
µA
16
mA
6.6 Driver Switching Characteristics
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPHL
Driver high-to-low propagation delay time
18
40
tPLH
Driver low-to-high propagation delay time
18
40
tr
Driver 10%-to-90% differential output rise time
10
55
tf
Driver 90%-to-10% differential output fall time
10
55
tSK(P)
Driver differential output pulse skew, |tPHL - tPLH|
ten
Driver enable time
tdis
Driver disable time
RL = 54 Ω, CL = 50 pF,See Figure 9
UNIT
ns
2.5
Receiver enabled, See Figures 4 and 5
55
ns
Receiver disabled, See Figures 4 and 5
6
µs
Receiver enabled, See Figures 4 and 5
90
ns
6.7 Receiver Switching Characteristics
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
tPHL
Receiver high-to-low propagation delay time
tPLH
Receiver low-to-high propagation delay time
tr
Receiver 10%-to-90% differential output rise time
tf
Receiver 90%-to-10% differential output fall time
tSK(P)
Receiver differential output pulse skew, |tPHL - tPLH|
ten
Receiver enable time
tdis
Receiver disable time
MIN
TYP
MAX
UNIT
70
70
CL = 15 pF, See Figure 12
5
ns
5
4.5
Driver enabled, See Figure 13
15
ns
Driver disabled, See Figure 14
6
µs
Driver enabled, See Figure 13
20
ns
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375 W ± 1%
Y
D
0 or 3 V
-7 V < V(TEST) < 12 V
VOD
60 W
± 1%
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
Figure 1. Driver Enable Time From DE to VOD
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
6
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6.8 Typical Characteristics
4
70
D and DE at VCC
RL = 54 W
TA = –40°C
I O – Driver Output Current – mA
Differential Output Voltage – V
TA = 25°C
DE at VCC
D at VCC
RL = 54 W
60
3.5
TA = 25°C
3
TA = 85°C
2.5
2
1.5
50
40
30
20
10
1
2.5
0
VCC – Supply Voltage – V
1.2 1.8 2.4
3
3.6 4.2
VCC – Supply Voltage – V
Figure 2. Differential Output Voltage vs Supply Voltage
Figure 3. Driver Output Current vs Supply Voltage
3
3.5
4
4.5
5
5.5
6
0.6
4.8
5.4
2.5
TA = 25°C
RE at VCC
DE at VCC
RL = 54 W
CL = 50 pF
VCC = 5 V
TA = 25°C
D, DE or RE input
Logic Input Threshold Voltage – V
I CC – RMS Supply Current – mA
120
0
100
80
60
40
0
2.5
5
7.5
Positive Going
2
1.5
Negative Going
1
0.5
0
2.5
10
Signaling Rate – Mbps
5.5
3.5
4.5
VCC – Supply Voltage – V
6.5
Figure 4. RMS Supply Current vs Signaling Rate
Figure 5. Logic Input Threshold Voltage vs Supply Voltage
500
450
400
Enable Time − ns
350
3.3 V
300
250
5V
200
150
100
50
0
-7
-2
3
8
13
V(TEST) − Common-Mode Voltage − V
Figure 6. Enable Time vs Common-Mode Voltage (See Figure 1)
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7 Parameter Measurement Information
375 Ω ±1%
VCC
DE
D
A
VOD
0 or 3 V
60 Ω ±1%
+
_
B
–7 V < V(test) < 12 V
375 Ω ±1%
Figure 7. Driver VOD With Common-Mode Loading Test Circuit
VCC
DE
Input
D
27 Ω ± 1%
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
A
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
Figure 8. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3V
VCC
DE
D
Input
Generator
VI
50 Ω
VOD
tPLH
CL Includes Fixture
and Instrumentation
Capacitance
RL = 54 Ω
± 1%
B
1.5 V
VI
CL = 50 pF ±20%
A
1.5 V
tPHL
90%
VOD
≈2V
90%
0V
10%
≈ –2 V
0V
10%
tr
tf
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 9. Driver Switching Test Circuit and Voltage Waveforms
A
3V
D
3V
S1
VO
VI
1.5 V
1.5 V
B
DE
Input
Generator
VI
50 Ω
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
RL = 110 Ω
± 1%
0.5 V
0V
tPZH
VOH
VO
2.3 V
tPHZ
≈0V
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 10. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
8
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3V
A
3V
D
VI
≈3V
1.5 V
VI
S1
1.5 V
VO
DE
Input
Generator
RL = 110 Ω
± 1%
50 Ω
0V
B
tPZL
tPLZ
≈3V
CL = 50 pF ±20%
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 11. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
A
Input
Generator
R
VI
50 Ω
1.5 V
0V
B
VO
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
1.5 V
VI
1.5 V
0V
tPLH
VO
tPHL
90% 90%
1.5 V
10%
tr
VOH
1.5 V
10% V
OL
tf
Figure 12. Receiver Switching Test Circuit and Voltage Waveforms
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3V
VCC
A
DE
0 V or 3 V
R
D
VO
B
RE
Input
Generator
VI
A
1 kΩ ± 1%
S1
CL = 15 pF ±20%
B
CL Includes Fixture
and Instrumentation
Capacitance
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
VI
1.5 V
1.5 V
0V
tPZH
tPHZ
VOH –0.5 V
VOH
D at 3 V
S1 to B
1.5 V
VO
≈0V
tPZL
tPLZ
≈ VCC
VO
1.5 V
VOL +0.5 V
D at 0 V
S1 to A
VOL
Figure 13. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
10
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VCC
A
0 V or 1.5 V
B
1.5 V or 0 V
Input
Generator
R
RE
A
1 kΩ ± 1%
S1
CL = 15 pF ±20%
B
CL Includes Fixture
and Instrumentation
Capacitance
50 Ω
VI
VO
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
VI
1.5 V
0V
tPZH
VOH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
VO
GND
tPZL
≈ VCC
1.5 V
VO
A at 0 V
B at 1.5 V
S1 to A
VOL
Figure 14. Receiver Enable Time From Standby (Driver Disabled)
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8 Detailed Description
8.1 Overview
The SNx5HVD08 is a 3-V to 5.5-V, half-duplex, RS-485 transceiver suitable for data transmission up to 10 Mbps.
This device has an active-high driver enable and active-low receiver enable. A standby current of less than 5 µA
can be achieved by disabling both driver and receiver.
Device operation is specified over a wide temperature range from -40°C to +85°C.
8.2 Functional Block Diagram
VCC
R
/RE
A
DE
B
D
GND
Figure 15. Logic Diagram (Positive)
8.3 Feature Description
Internal ESD protection circuits protect the transceiver bus terminals against ±16 kV Human Body Model (HBM)
electrostatic discharges and all other pins up to ±4 kV.
The SNx5HVD08 provides internal biasing of the receiver input thresholds for open-circuit, bus-idle, or shortcircuit failsafe conditions, and a typical receiver hysteresis of 35 mV.
8.4 Device Functional Modes
Table 1. Function Table:
Driver
INPUT
ENABLE
OUTPUTS
D
DE
A
B
H
L
X
Open
H
H
L
H
H
L
Z
H
L
H
Z
L
Table 2. Function Table: Receiver
(1)
12
DIFFERENTIAL INPUTS
ENABLE (1)
OUTPUT (1)
VID = VA - VB
RE
R
VID≤ -0.2 V
-0.2 V < VID < -0.01 V
-0.01 V ≤ VID
X
Open Circuit
Short Circuit
L
L
L
H
L
L
L
?
H
Z
H
H
H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
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D and RE Inputs
DE Input
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9V
9V
A Input
B Input
VCC
VCC
16 V
100 kΩ
16 V
36 kΩ
180 kΩ
180 kΩ
Input
Input
16 V
36 kΩ
36 kΩ
100 kΩ
16 V
A and B Outputs
36 kΩ
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
16 V
Figure 16. Equivalent Input and Output Schematic Diagrams
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
As electrical loads are physically distanced from their power source, the effects of supply and return line
impedance and the resultant voltage drop must be accounted. If the supply regulation at the load cannot be
maintained to the circuit requirements, it forces the use of remote sensing, additional regulation at the load,
bigger or shorter cables, or a combination of these. The SN65HVD08 eases this problem by relaxing the supply
requirements to allow for more variation in the supply voltage over typical RS-485 transceivers.
9.1.1 Supply Source Impedance
In the steady state, the voltage drop from the source to the load is simply the wire resistance times the load
current as modeled in Figure 17.
RS
IL
+
+
RL
VL = VS – 2RSIL
VS
–
RS
–
Figure 17. Steady-State Circuit Model
For example, if you were to provide 5-V ±5% supply power to a remote circuit with a maximum load requirement
of 0.1 A (one SN65HVD08), the voltage at the load would fall below the 4.5-V minimum of most 5-V circuits with
as little as 5.8 m of 28-GA conductors. Table 3 summarizes wire resistance and the length for 4.5 V and 3 V at
the load with 0.1 A of load current. The maximum lengths would scale linearly for higher or lower load currents.
Table 3. Maximum Cable Lengths for Minimum Load Voltages at 0.1 A Load
WIRE SIZE
RESISTANCE
4.5-V LENGTH
AT 0.1 A
3-V LENGTH
AT 0.1 A
28 Gauge
0.213 Ω/m
5.8 m
41.1 m
24 Gauge
0.079 Ω/m
15.8 m
110.7 m
22 Gauge
0.054 Ω/m
23.1 m
162.0 m
20 Gauge
0.034 Ω/m
36.8 m
257.3 m
18 Gauge
0.021 Ω/m
59.5 m
416.7 m
Under dynamic load requirements, the distributed inductance and capacitance of the power lines may not be
ignored and decoupling capacitance at the load is required. The amount depends upon the magnitude and
frequency of the load current change but, if only powering the SN65HVD08, a 0.1 µF ceramic capacitor is usually
sufficient.
9.1.2 Opto-Isolated Data Buses
Long RS-485 circuits can create large ground loops and pick up common-mode noise voltages in excess of the
range tolerated by standard RS-485 circuits. A common remedy is to provide galvanic isolation of the data circuit
from earth or local grounds.
14
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SN75HVD08, SN65HVD08
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SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
Application Information (continued)
Transformers, capacitors, or phototransistors most often provide isolation of the bus and the local node.
Transformers and capacitors require changing signals to transfer the information over the isolation barrier and
phototransistors (opto-isolators) can pass steady-state signals. Each of these methods incurs additional costs
and complexity, the former in clock encoding and decoding of the data stream and the latter in requiring an
isolated power supply.
Quite often, the cost of isolated power is repeated at each node connected to the bus as shown in Figure 18.
The possibly lower-cost solution is to generate this supply once within the system and then distribute it along with
the data line(s) as shown in Figure 19.
DC-to-DC
Converter
Opto
Isolators
DC-to-DC
Converter
Opto
Isolators
Local Power
Source
Rest of
Board
Local Power
Source
Rest of
Board
Figure 18. Isolated Power at Each Node
Local Power
Source
Opto
Isolators
Rest of
Board
SN65HVD08
Local Power
Source
Opto
Isolators
Rest of
Board
Figure 19. Distribution of Isolated Power
The features of the SN65HVD08 are particularly good for the application of Figure 19. Due to added supply
source impedance, the low quiescent current requirements and wide supply voltage tolerance allow for the
poorer load regulation.
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Product Folder Links: SN75HVD08 SN65HVD08
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SN75HVD08, SN65HVD08
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www.ti.com
Application Information (continued)
9.1.3 Opto Alternative
The ISO150 is a two-channel, galvanically isolated data coupler capable of data rates of 80 Mbps. Each channel
can be individually programmed to transmit data in either direction.
Data is transmitted across the isolation barrier by coupling complementary pulses through high-voltage 0.4-pF
capacitors. Receiver circuitry restores the pulses to standard logic levels. Differential signal transmission rejects
isolation-mode voltage transients up to 1.6 kV/ms.
ISO150 avoids the problems commonly associated with opto-couplers. Optically-isolated couplers require high
current pulses and allowance must be made for LED aging. The ISO150's Bi-CMOS circuitry operates at 25 mW
per channel with supply voltage range matching that of the SN65HVD08 of 3 V to 5.5 V.
Figure 20 shows a typical circuit.
+5 V
Data
(I/O)
SN65HVD08
D
D2A
R/T2A
GA
ISO150
VSB
R/T2B
D2B
DE
RE
Channel 1
A
B
Bus
R
Side A
Side B
Channel 2
D1A
R/T1A
VSA
GA
R/T1B
D1B
DE/RE
+5 V
ª1º
+5 V
Figure 20. Isolated RS-485 Interface
16
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SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
B
A
B
DE
D
B
R
R
RE
D
D
R RE DE D
R RE DE D
D
Figure 21. Typical Application Diagram
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 22. Cable Length vs Data Rate Characteristic
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www.ti.com
Typical Application (continued)
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
(1)
Where:
• tr is the 10/90 rise time of the driver
• c is the speed of light (3 × 108 m/s)
• v is the signal velocity of the cable or trace as a factor of c
Per Equation 1, the maximum recommended stub length for the minimum driver output rise time of the
SNx5HVD08 for a signal velocity of 78% is 0.23 meters (0.75 feet).
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the SN65HVD08 and SN75HVD08 are each
1/8 UL transceivers, it is possible to connect up to 256 receivers to the bus.
9.2.1.4 Receiver Failsafe
The differential receivers of the SNx5HVD08 family are “failsafe” to invalid bus states caused by:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the “input indeterminate” range
does not include zero volts differential.
In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the
differential input VID is more positive than +200 mV, and must output a Low when VID is more negative than 200 mV. The receiver parameters which determine the failsafe performance are VIT(+) and VIT(-).
As shown in the Electrical Characteristics table, differential signals more negative than -200 mV will always
cause a Low receiver output, and differential signals more positive than -10 mV will always cause a High receiver
output. Thus, when the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of 10 mV, and the receiver output will be High.
18
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SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
Typical Application (continued)
9.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is necessary.
3.3V
100nF
100nF
10k
VCC
R1
R
RxD
MCU/
UART
HVD08
DE
DIR
TVS
A
RE
B
D
TxD
R2
10k
GND
Figure 23. Transient protection against ESD, EFT, and Surge transients
Figure 23 suggests a protection circuit against 10 kV ESD (IEC 61000-4-2), 4 kV EFT (IEC 61000-4-4), and 1 kV
surge (IEC 61000-4-5) transients. Table 4 shows the associated Bill of Materials.
Table 4. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
3.3 V to 5 V, 10 Mbps RS-485 Transceiver
SNx5HVD08
TI
R1, R2
10 Ω, Pulse-Proof Thick-Film Resistor
CRCW0603010RJNEAHP
Vishay
TVS
Bidirectional 400 W Transient Suppressor
CDSOT23-SM712
Bourns
9.2.3 Application Curve
Figure 24 demonstrates operation of the SN65HVD08 at a signaling rate of 10 Mbps.
Figure 24. SNx5HVD08 Differential Output Waveform
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SN75HVD08, SN65HVD08
SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
www.ti.com
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76333 and TPS76350 are linear
voltage regulators suitable for 3.3 V and 5 V supplies respectively.
11 Layout
11.1 Layout Guidelines
On-chip IEC-ESD protection is sufficient for laboratory and portable equipment but insufficient for EFT and surge
transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the use
of external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high
frequency layout techniques must be applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, or
controller ICs on the board.
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
7. Insert series pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the
specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping
current into the transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
11.2 Layout Example
5
Via to ground
Via to VCC
4
6 R
1
R
MCU
R
7
5 TVS
R
6 R
SNx5HVD08
JMP
C
R
5
Figure 25. SNx5HVD08 Layout example
20
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SLLS550D – NOVEMBER 2002 – REVISED JULY 2015
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN75HVD08
Click here
Click here
Click here
Click here
Click here
SN65HVD08
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: SN75HVD08 SN65HVD08
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21
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65HVD08D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP08
SN65HVD08DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP08
SN65HVD08DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP08
SN65HVD08DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP08
SN65HVD08P
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
65HVD08
SN75HVD08D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VN08
SN75HVD08DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VN08
SN75HVD08DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
VN08
SN75HVD08P
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
75HVD08
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Aug-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD08DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN75HVD08DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD08DR
SOIC
D
8
2500
340.5
338.1
20.6
SN75HVD08DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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