Texas Instruments | TRS3232 3-V to 5.5-V Multichannel RS-232 Line Driver and Receiver With ±15-kV ESD Protection (Rev. A) | Datasheet | Texas Instruments TRS3232 3-V to 5.5-V Multichannel RS-232 Line Driver and Receiver With ±15-kV ESD Protection (Rev. A) Datasheet

Texas Instruments TRS3232 3-V to 5.5-V Multichannel RS-232 Line Driver and Receiver With ±15-kV ESD Protection (Rev. A) Datasheet
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TRS3232
SLLS812A – JULY 2007 – REVISED JUNE 2015
TRS3232 3-V to 5.5-V Multichannel RS-232 Line Driver and Receiver
With ±15-kV ESD Protection
1 Features
3 Description
•
The TRS3232 device consists of two line drivers, two
line receivers, and a dual charge-pump circuit with
±15-kV ESD protection terminal-to-terminal (serialport connection terminals, including GND). The
device meets the requirements of TIA/EIA-232-F and
provides the electrical interface between an
asynchronous communication controller and the
serial-port connector. The charge pump and four
small external capacitors allow operation from one
3-V to 5.5-V supply. The devices operate at datasignaling rates up to 250 kbps and a maximum of
30-V/μs driver-output slew rate.
1
•
•
•
•
•
•
•
•
RS-232 Bus-Terminal ESD Protection Exceeds
±15 kV Using Human-Body Model (HBM)
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU V.28 Standards
Operates With 3-V to 5.5-V VCC Supply
Operates up to 250 kbps
Two Drivers and Two Receivers
Low Supply Current: 300-μA Typical
External Capacitors: 4 × 0.1 μF
Accepts 5-V Logic Input With 3.3-V Supply
Alternative High-Speed Terminal-Compatible
Devices (1 Mbps)
– SN65C3232 (–40°C to 85°C)
– SN75C3232 (0°C to 70°C)
Device Information(1)
PART NUMBER
TRS3232
2 Applications
•
•
•
•
•
Battery-Powered Systems
Notebooks
Laptops
Palmtop PCs
Hand-Held Equipment
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm × 3.91 mm
SSOP (16)
6.20 mm × 5.30 mm
SOIC-Wide (16)
10.30 mm × 7.50 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
3.3 V, 5 V
POWER
2
DIN
2
TX
RS232
2
ROUT
DOUT
RX
2
RIN
RS232
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TRS3232
SLLS812A – JULY 2007 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
5
5
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics—Device ...........................
Electrical Characteristics—Driver .............................
Electrical Characteristics—Receiver .........................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application .................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
Changes from Original (July 2007) to Revision A
Page
•
Changed Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics section,
Detailed Description section, Power Supply Recommendations and Layout sections, Device and Documentation
Support and Mechanical, Packaging, and Orderable Information.......................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 3
2
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5 Pin Configuration and Functions
D, DB, DW, PW Packages
16-Pin SOIC, SSOP, SOIC (Wide), TSSOP
Top View
C1+
V+
C1C2+
C2VDOUT2
RIN2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
GND
DOUT1
RIN1
ROUT1
DIN1
DIN2
ROUT2
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
C1+
1
—
Positive lead of C1 capacitor
C1–
3
—
Negative lead of C1 capacitor
C2+
4
—
Positive lead of C2 capacitor
C2–
5
—
Negative lead of C2 capacitor
DIN1
11
I
Logic data input (from UART)
DIN2
10
I
Logic data input (from UART)
DOUT1
14
O
RS232 line data output (to remote RS232 system)
DOUT2
7
O
RS232 line data output (to remote RS232 system)
GND
15
—
Ground
RIN1
13
I
RS232 line data input (from remote RS232 system)
RIN2
8
I
RS232 line data input (from remote RS232 system)
ROUT1
12
O
Logic data output (to UART)
ROUT2
9
O
Logic data output (to UART)
V+
2
O
Positive charge pump output for storage capacitor only
V–
6
O
Negative charge pump output for storage capacitor only
VCC
16
—
Supply Voltage, Connect to external 3-V to 5.5-V power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage (2)
VCC
(2)
V+
Positive output supply voltage
V–
Negative output supply voltage (2)
V+ – V–
Supply voltage difference (2)
VI
Input voltage
VO
Output voltage
TJ
Operating virtual junction temperature
Tstg
Storage temperature
(1)
(2)
MIN
MAX
UNIT
–0.3
6
V
–0.3
7
V
–7
0.3
V
13
V
Drivers
–0.3
6
Receivers
–25
25
Drivers
–13.2
13.2
Receivers
–0.3
VCC + 0.3
–65
V
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network GND.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
RIN , DOUT, and GND pins (1)
±15000
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
All other pins (1)
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
(see Figure 6) (1)
VCC = 3.3 V
MIN
NOM
MAX
3
3.3
3.6
4.5
5
5.5
VCC
Supply voltage
VIH
Driver high-level input voltage
DIN
VIL
Driver low-level input voltage
DIN
Driver input voltage
DIN
0
5.5
Receiver input voltage
RIN
–25
25
0
70
–40
85
VI
TA
(1)
4
Operating free-air temperature
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
2
TRS3232I
V
V
2.4
0.8
TRS3232C
UNIT
V
V
°C
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
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6.4 Thermal Information
TRS3232
THERMAL METRIC
RθJA
(1)
D
(SOIC)
DB
(SSOP)
DW
(SOIC-wide)
PW
(TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
73
82
57
108
(1)
Junction-to-ambient thermal resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics—Device
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 6)
PARAMETER
ICC
(1)
(2)
TEST CONDITIONS
Supply current
No load,
MIN TYP (2)
MAX
0.3
1
VCC = 3.3 V to 5 V
UNIT
mA
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
6.6 Electrical Characteristics—Driver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 6)
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
5.4
MAX
UNIT
VOH
High-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = GND
5
VOL
Low-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = VCC
–5
IIH
High-level input current
VI = VCC
±0.01
±1
μA
IIL
Low-level input current
VI at GND
±0.01
±1
μA
IOS (3)
Short-circuit output current
±35
±60
mA
rO
Output resistance
(1)
(2)
(3)
VCC = 3.6 V
VO = 0 V
VCC = 5.5 V
VO = 0 V
VCC = 0 V, V+ = 0 V, and V–
VO = ±2 V
=0V
300
V
–5.4
V
Ω
10M
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.
6.7 Electrical Characteristics—Receiver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 6)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –1 mA
VOL
Low-level output voltage
IOL = 1.6 mA
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input hysteresis (VIT+ – VIT–)
rI
Input resistance
(1)
(2)
MIN
TYP (2)
VCC – 0.6
VCC – 0.1
MAX
V
0.4
VCC = 3.3 V
1.5
2.4
VCC = 5 V
1.8
2.4
VCC = 3.3 V
0.6
1.2
VCC = 5 V
0.8
1.5
3
5
V
V
V
0.3
VI = ±3 V to ±25 V
UNIT
V
7
kΩ
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
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6.8 Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 6)
PARAMETER
TEST CONDITIONS
Maximum data rate
RL = 3 kΩ,
CL = 1000 pF
One DOUT switching,
See Figure 3
tsk(p)
Driver Pulse skew (3)
RL = 3 kΩ to 7 kΩ,
SR(tr)
Driver Slew rate, transition region
(see Figure 3)
RL = 3 kΩ to 7 kΩ,
VCC = 5 V
tPLH
Receiver Propagation delay time,
low- to high-level output
tPHL
Receiver Propagation delay time,
high- to low-level output
tsk(p)
Receiver Pulse skew (1)
(1)
(2)
(3)
MIN
TYP (2)
150
250
kbps
300
ns
CL = 150 to 2500 pF
See Figure 4
MAX
CL = 150 to 1000 pF
6
30
CL = 150 to 2500 pF
4
30
UNIT
V/μs
300
ns
300
ns
300
ns
CL = 150 pF
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
6.9 Typical Characteristics
VCC = 3.3 V
1
6
VOH
0
5
VOL (V)
VOH (V)
±1
4
3
2
±3
±4
1
±5
0
±6
0
5
10
15
Output Current (mA)
20
25
VOL
0
5
10
15
Output Current (mA)
C001
Figure 1. DOUT VOH vs Load Current, Both Drivers Loaded
6
±2
20
25
C001
Figure 2. DOUT VOL vs Load Current, Both Drivers Loaded
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7 Parameter Measurement Information
3V
Input
Generator
(see Note B)
1.5 V
RS-232
Output
50 W
RL
1.5 V
0V
tTHL
CL
(see Note A)
Output
tTLH
3V
-3 V
TEST CIRCUIT
SR(tr) =
VOH
3V
-3 V
VOL
VOLTAGE WAVEFORMS
6V
tTHL or tTLH
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbps, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
Figure 3. Driver Slew Rate
3V
Generator
(see Note B)
RS-232
Output
50 W
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPHL
tPLH
VOH
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbps, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
Figure 4. Driver Pulse Skew
3V
Input
Generator
(see Note B)
1.5 V
1.5 V
-3 V
Output
50 W
tPHL
CL
(see Note A)
tPLH
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 5. Receiver Propagation Delay Times
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8 Detailed Description
8.1 Overview
The TRS3232 device consists of two line drivers, two line receivers, and a dual charge-pump circuit with
±15-kV ESD protection terminal to terminal (serial-port connection terminals, including GND). The device meets
the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous
communication controller and the serial-port connector. The charge pump and four small external capacitors
allow operation from one 3-V to 5.5-V supply. The device operates at data signaling rates up to 250 kbps and a
maximum of 30-V/μs driver output slew rate. Outputs are protected against shorts to ground.
8.2 Functional Block Diagram
3.3 V, 5 V
POWER
2
DIN
2
TX
2
ROUT
DOUT
RS232
RX
2
RIN
RS232
8.3 Feature Description
8.3.1 Power
The power block increases, inverts, and regulates voltage at V+ and V– pins using a charge pump that requires
four external capacitors.
8.3.2 RS232 Driver
Two drivers interface the standard logic level to RS232 levels. Both DIN inputs must be valid high or low.
8.3.3 RS232 Receiver
Two receivers interface RS232 levels to standard logic levels. An open input results in a high output on ROUT.
Each RIN input includes an internal standard RS232 load.
8
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8.4 Device Functional Modes
Table 1. Each Driver (1)
(1)
INPUT
DIN
OUTPUT
DOUT
L
H
H
L
H = high level, L = low level
Table 2. Each Receiver (1)
(1)
INPUT
RIN
OUTPUT
ROUT
L
H
H
L
Open
H
H = high level, L = low level,
Open = input disconnected or
connected driver off
8.4.1 VCC Powered by 3 V to 5.5 V
The device is in normal operation.
8.4.2 VCC Unpowered, VCC = 0 V
When the TRS3232 device is unpowered, it can be safely connected to an active remote RS232 device.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TRS3232 device is designed to convert single-ended signals into RS232-compatible signals, and vice-versa.
This device can be used in any application where an RS232 line driver or receiver is required. One benefit of this
device is its ESD protection, which helps protect other components on the board when the RS232 lines are tied
to a physical connector.
9.2 Typical Application
1
16
+ CBYPASS
- = 0.1 mF
+
C1
VCC
C1+
2
(A)
† +
-
C3
V+
GND
15
3
4
14
DOUT1
C113
+
C2
RIN1
C2+
5 kW
5 C212
6
C4
-
V-
ROUT1
11
DIN1
+
DOUT2
RIN2
7
10
8
9
DIN2
ROUT2
5 kW
A.
C3 can be connected to VCC or GND.
B.
Resistor values shown are nominal.
C.
Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they must
be connected as shown.
D.
See Table 3 for capacitor values.
Figure 6. Typical Operating Circuit
10
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Typical Application (continued)
9.2.1 Design Requirements
•
•
Recommended VCC is 3.3 V or 5 V
– 3 V to 5.5 V is also possible
Maximum recommended bit rate is 250 kbps
Table 3. VCC versus Capacitor Values
VCC
C1
C2, C3, C4
3.3 V ± 0.3 V
0.1 µF
0.1 µF
5 V ± 0.5 V
0.047 µF
0.33 µF
3 V to 5.5 V
0.1 µF
0.47 µF
9.2.2 Detailed Design Procedure
For proper operation, add capacitors as shown in Figure 6 and Table 3.
All DIN inputs must be connected to valid low or high logic levels.
Select capacitor values based on VCC level for best performance.
Voltage (V)
9.2.3 Application Curve
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
DIN
DOUT to RIN
ROUT
0
1
2
3
4
5
6
7
Time (µs)
8
9
10
C001
Figure 7. 250 kbps Driver to Receiver Loopback Timing Waveform,
VCC= 3.3 V
10 Power Supply Recommendations
VCC must be between 3 V and 5.5 V. Charge pump capacitors must be chosen using Table 3.
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11 Layout
11.1 Layout Guidelines
Keep the external capacitor traces short. This is more important on C1 and C2 nodes that have the fastest rise
and fall times.
11.2 Layout Example
Ground
C3
C1
1 C1+
VCC 16
2 V+
GND 15
3 C1–
DOUT1 14
4 C2+
RIN1 13
5 C2–
ROUT1 12
VCC
0.1µF
Ground
C2
Ground
6 V–
DIN1 11
7 DOUT2
DIN2 10
C4
8 RIN2
ROUT2 9
Figure 8. Layout Diagram
12
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TRS3232CDBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RS32C
TRS3232CDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS3232C
TRS3232CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS3232C
TRS3232CPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RS32C
TRS3232IDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS3232I
TRS3232IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RS32I
TRS3232IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RS32I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TRS3232CDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TRS3232CDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
TRS3232IDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TRS3232IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TRS3232CDR
TRS3232CDWR
SOIC
D
16
2500
333.2
345.9
28.6
SOIC
DW
16
2000
350.0
350.0
43.0
TRS3232IDR
SOIC
D
16
2500
333.2
345.9
28.6
TRS3232IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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