Texas Instruments | TPIC1021 LIN Physical Interface (Rev. D) | Datasheet | Texas Instruments TPIC1021 LIN Physical Interface (Rev. D) Datasheet

Texas Instruments TPIC1021 LIN Physical Interface (Rev. D) Datasheet
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TPIC1021
SLIS113D – OCTOBER 2004 – REVISED JUNE 2015
TPIC1021 LIN Physical Interface
1 Features
3 Description
•
The TPIC1021 is the LIN (Local Interconnect
Network) physical interface, which integrates the
serial transceiver with wake up and protection
features. The LIN bus is a single wire, bi-directional
bus typically used for low-speed in-vehicle networks
using baud rates between 2.4 kbps and 20 kbps.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LIN Physical Layer Specification Revision 2.0
compliant. Conforms to SAEJ2602 Recommended
Practice for LIN
LIN Bus Speed up to 20 kbps
ESD Protection to 12 kV (Human Body Model) on
LIN Pin
LIN Pin Handles Voltage from –40 V to 40 V
Survives Transient Damage in Automotive
Environment (ISO 7637)
Operation with Supply from 7-V to 27-V DC
Two Operation Modes: Normal and Low-Power
(Sleep) Mode
Low Current Consumption in Low Power Mode
Wake-Up Available from LIN Bus, Wake-Up Input
(External Switch) or Host MCU
Interfaces to MCU with 5-V or 3.3-V I/O Pins
Dominant State Timeout Protection on TXD Pin
Wake-Up Request on RXD Pin
Control of External Voltage Regulator (INH Pin)
Integrated Pull-Up Resistor and Series Diode for
LIN Slave Applications
Low EME (Electromagnetic Emissions), High EMI
(Electromagnetic Immunity)
Bus Terminal Short-Circuit Protected for Short to
Battery or Short to Ground
Thermally Protected
Ground Disconnection Fail-Safe at System Level
Ground Shift Operation at System Level
Unpowered Node Does Not Disturb the Network
The LIN bus has two logical values: the dominant
state (voltage near ground) represents a logic 0 and
the recessive state (voltage near battery) and
represents logic 1.
In the recessive state the LIN bus is pulled high by
the TPIC1021’s internal pull-up resistor (30 kΩ) and
series diode, so no external pullup components are
required for slave applications. Master applications
require an external pullup resistor (1 kΩ) plus a series
diode.
Device Information(1)
PART NUMBER
TPIC1021
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Functional Block Diagram
8
7
1
RXD
Receiver
INH
VSUP
VSUP/2
2
EN
NWake
3
2 Applications
•
•
PACKAGE
Wake−Up
and
Vreg Control
Filter
Dominant
State
Timeout
Industrial Sensing
White Goods Distributed Control
4
TXD
Filter
Fault
Detection and
Protection
6
LIN
5
Driver
GND
with Slope
Control
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC1021
SLIS113D – OCTOBER 2004 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Revision C (July 2005) to Revision D
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Description (continued)
The LIN Protocol output data stream on the TXD pin is converted by the TPIC1021 into the LIN bus signal
through a current limited, wave-shaping low-side driver with control as outlined by the LIN Physical Layer
Specification Revision 2.0. The receiver converts the data stream from the LIN bus and outputs the data stream
via the RXD pin.
In Low Power mode, the TPIC1021 requires very low quiescent current even though the wake-up circuits remain
active allowing for remote wake up via the LIN bus or local wake ups via NWake or EN pins.
The TPIC1021 has been designed for operation in the harsh automotive environment. The device can handle LIN
bus voltage swing from 40 V down to ground and survive –40 V. The device also prevents back feed current
through the LIN pin to the supply input in case of a ground shift or supply voltage disconnection. It also features
under-voltage, over temperature, and loss of ground protection. In the event of a fault condition the output is
immediately switched off and remains off until the fault condition is removed.
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
RXD
1
8
INH
EN
2
7
VSUP
NWake
3
6
LIN
TXD
4
5
GND
Pin Functions
PIN
NO.
1
NAME
TYPE
DESCRIPTION
RXD
O
RXD output (open drain) pin interface reporting state of LIN bus voltage
2
ED
I
Enable input pin
3
NWake
I
High voltage input pin for device wake up
4
TXD
I
TXD input pin interface to control state of LIN output
5
GND
I
Ground connection
6
LIN
I/O
7
VSUP
Supply
8
INH
O
LIN bus pin single wire transmitter and receiver
Device supply pin (connected to battery in series with external reverse blocking diode)
Inhibit pin controls external voltage regulator with inhibit input
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SLIS113D – OCTOBER 2004 – REVISED JUNE 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VSUP
(2)
Continuous
Supply line supply voltage
Transient
MIN
MAX
UNIT
0
27
V
0
40
V
–1
40
V
Logic pin input voltage (RXD, TXD, EN)
–0.3
5.5
V
NWake DC and transient input voltage (through 33-kΩ serial resistor)
LIN DC input voltage
–40
40
V
TA
Operational free-air temperature
–40
125
°C
TJ
Junction temperature
–40
150
°C
Thermal shutdown
200
°C
Thermal shutdown hysteresis
25
°C
165
°C
Tstg
(1)
(2)
Storage temperature range
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
(3)
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1) (2)
Machine model (3)
LIN pin
±12000
NWake pin
±9000
All other pins
±3000
LIN and NWake pins
±400
All other pins
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
The machine model is a 200-pF capacitor through a 10-Ω resistor and a 0.75-µH coil.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TSUP
Supply voltage
TAMB
Ambient temperature
NOM
MAX
UNIT
7
27
V
–40
125
°C
7.4 Thermal Information
TPIC1021
THERMAL METRIC
(1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
145
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.9
°C/W
RθJB
Junction-to-board thermal resistance
55.5
°C/W
ψJT
Junction-to-top characterization parameter
14.3
°C/W
ψJB
Junction-to-board characterization parameter
55
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)
MIN
TYP (1)
MAX
Operational supply voltage (2)
7
14
27
V
Nominal supply line voltage (2)
7
14
18
V
PARAMETER
TEST CONDITIONS
UNIT
SUPPLY
VSUP undervoltage threshold (2)
4.5
Normal Mode, EN = 1, Bus dominant
(total bus load > 500 Ω) (3)
1.2
2.5
mA
1
2.1
mA
Normal Mode, EN = 1, Bus recessive
300
500
µA
Standby Mode, EN = 0, Bus recessive
300
500
µA
Low Power Mode, EN = 0, VSUP < 14 V,
NWake = VSUP , LIN = VSUP
20
50
µA
Low Power Mode, EN = 0, 14 V < VSUP
< 27 V, NWake = VSUP, LIN = VSUP
50
100
µA
Standby Mode, EN = 0, Bus dominant
(total bus load > 500 Ω) (3)
ICC
Supply Current
V
RXD OUTPUT PIN
VO
Output voltage
IOL
Low-level output current, open drain LIN = 0 V, RXD = 0.4 V
-0.3
IIKG
Leakage current, high-level
LIN = VSUP, RXD = 5 V
5.5
3.5
-5
V
mA
0
5
µA
TXD INPUT PIN
VIL
Low-level input voltage (2)
-0.3
0.8
V
VIH
High-level input voltage (2)
2
5.5
V
VIT
Input threshold hysteresis voltage
(2)
30
Pull-down resistor
IIL
Low-level input current
TXD = 0
500
mV
125
350
800
kΩ
-5
0
5
µA
LIN PIN (Referenced to VSUP)
VOH
High-level output voltage (2)
LIN recessive, TXD = High, IO = 0 mA
VSUP-1V
VOL
Low-level output voltage (2)
LIN dominant, TXD = Low, IO = 40 mA
0
Pull-up resistor to VSUP
V
0.2×VSUP
V
20
30
60
kΩ
IL
Limiting current
TXD = Low
50
150
250
mA
IIKG
Leakage current
LIN = VSUP
-5
0
5
µA
VIL
Low-level input voltage (2)
LIN dominant
0×VSUP
0.4×VSUP
V
VIH
High-level input voltage
(2)
LIN recessive
0.6×VSUP
VIT
Input threshold voltage (2)
Vhys
Hysteresis voltage (2)
VIL
Low-level input voltage for wakeup (2)
0.4×VSUP
0.5×VSUP
0.05×VSUP
0
VSUP
V
0.6×VSUP
V
0.175×VSUP
V
0.4×VSUP
V
EN PIN
VIL
Low-level input voltage (2)
VIH
High-level input voltage
(2)
Vhys
Hysteresis voltage (2)
-0.3
Pull-down resistor
IIL
Low-level input current
EN = 0 V
0.8
V
2
5.5
V
30
500
mV
125
350
800
kΩ
-5
0
5
µA
INH PIN
(1)
(2)
(3)
Typical values are give for VSUP = 14 V at 25°C.
All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device.
In the dominant state the supply current increases as the supply voltage increases due to the integrated LIN slave termination
resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN
slave termination is 20 kΩ so the maximum supply current attributed to the termination is: ISUP (dom) max termination ≈ (VSUP –
(VLIN_Dominant+0.7 V) / 20 kΩ.
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Electrical Characteristics (continued)
VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Transient voltage
MIN
TYP (1)
MAX
-0.3
VSUP+0.3
-50
2
UNIT
Vo
DC output voltage
IO
Ouptut current
V
Ron
On state resistance
Between VSUP and INH, INH = 2 mA
drive, Normal or Standby Mode
25
40
100
Ω
IIKG
Leakage current
Low Power mode, 0 < INH < VSUP
-5
0
5
µA
VSUP-3.3
V
mA
NWake PIN
VIL
Low-level input voltage (2)
VIH
(2)
High-level input voltage
IIKG
-0.3
VSUP-1
Pull-up current
NWake = 0 V
Leakage current
VSUP = NWake
VSUP+0.3
V
-40
-10
-4
µA
-5
0
5
µA
THERMAL SHUTDOWN
Shutdown junction thermal
temperature
185
°C
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
D1
Duty cycle 1 (1)
(2)
THREC(max) = 0.744×VSUP, THDOM(max) = 0.581×VSUP, VSUP
= 7.0 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 1
D2
Duty cycle 2 (1)
(2)
THREC(max) = 0.284×VSUP, THDOM(max) = 0.422×VSUP, VSUP
= 7.6 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 1
D3
Duty cycle 3 (1)
(2)
THREC(max) = 0.778×VSUP, THDOM(max) = 0.616×VSUP, VSUP
= 7.0 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 1
D4
Duty cycle 4 (1)
(2)
THREC(max) = 0.251×VSUP, THDOM(max) = 0.389×VSUP, VSUP
= 7.6 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 1
trx_pdr
Receiver rising propagation delay
time
RL = 2.4 kΩ, CL = 20 pF, See Figure 1
6
µs
trx_pdf
Receiver rising propagation delay
time
RL = 2.4 kΩ, CL = 20 pF, See Figure 1
6
µs
trx_sym
Symmetry of receiver propagation
delay time (rising edge)
with respect to falling edge, See Figure 1
–2
2
µs
tNWake
NWake filter time for local wakeup
See Figure 1
25
50
100
µs
tLINBUS
LIN wake-up filter time (dominant
time for wake-up via LIN bus)
See Figure 1
25
50
100
µs
See Figure 1
6
9
14
ms
tDST
(1)
(2)
(3)
6
Dominant state timeout
(3)
0.396
0.581
0.417
0.590
Duty cycle = tBUS_rec(min)/ (2×tBIT)
Duty Cycles: LIN Driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 6.8 nF, 660 Ω; Load3 = 10 nF, 500 Ω.
Duty Cycles 3 and 4 are defined for 10.4 kbps operation. The TPIC1021 also meets these lower speed requirements, while it is capable
of of the higher speed 20.0 kbps operation as specified by Duty Cycles 1 and 2. SAEJ2602 derives propagation delay equations from
the LIN 2.0 duty cycle definitions, for details please refer to the SAEJ2602 specification.
Dominant state timeout will limit the minimum data rate to 2.4 kbps.
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tBit
tBit
tBit
RECESSIVE
TXD (Input)
DOMINANT
tBus_dom(max)
tBus_rec(min)
THRec(max)
THDom(max)
Thresholds of
receiving node 1
VSUP
LIN Bus Signal
(Transceiver supply
of transmitting node)
Thresholds of
receiving node 2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node 1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node 2)
trx_pdf(2)
trx_pdr(2)
Figure 1. Definition of Bus Timing Parameters
7.7 Typical Characteristics
0.7
20
18
0.6
16
0.5
14
VSUPPLY
VLIN
12
10
8
6
0.4
0.3
0.2
4
0.1
VLIN 25°C
VLIN 125°C
2
VLIN 25°C
VLIN 125°C
0
0
0
2
4
6
8
10
12
14
16
18
VSUPPLY
20
0
2
D001
Figure 2. VOH vs VSUPPLY and Temperature
4
6
8
10
VOL
12
14
16
18
20
D002
Figure 3. VOL vs VSUPPLY and Temperature
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8 Detailed Description
8.1 Overview
The TPIC1021 is a LIN (Local Interconnect Network) physical layer transceiver which integrates a serial
transceiver with wake up and protection features. The LIN bus is a single wire, bi-directional bus that typically is
used in low speed in vehicle networks with data rates that range from 2.4 kbps to 20 kbps.
8.2 Functional Block Diagram
8
7
1
RXD
Receiver
INH
VSUP
VSUP/2
2
EN
NWake
3
Wake−Up
and
Vreg Control
Filter
Filter
Dominant
State
Timeout
4
TXD
Fault
Detection and
Protection
6
LIN
5
Driver
GND
with Slope
Control
8.3 Feature Description
8.3.1 LIN Bus Pin
This I/O pin is the single-wire LIN bus transmitter and receiver.
8.3.1.1 Transmitter Characteristics
The driver is a low side transistor with internal current limitation and thermal shutdown. There is an internal 30kΩ pull-up resistor with a serial diode structure to Vsup so no external pull-up components are required for LIN
slave mode applications. An external pull-up resistor of 1 kΩ plus a series diode to Vsup must be added when the
device is used for master node applications.
Voltage on the LIN pin can go from -40 V to +40 V DC without any currents other than through the pull-up
resistance. There are no reverse currents from the LIN bus to supply (Vsup), even in the event of a ground shift or
loss of supply (Vsup).
The LIN thresholds and AC parameters are compatible LIN Protocol Specification Revision 2.0.
During a thermal shut down condition the driver is disabled.
8.3.1.2 Receiver Characteristics
The characteristic thresholds of the receiver are ratio-metric with the device supply pin. Typical thresholds are
50%, with a hysteresis between 5% and 17.5% of supply.
8
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Feature Description (continued)
8.3.2 Transmit Input Pin (TXD)
This pin is the interface to the MCU’s LIN Protocol Controller or SCI/UART used to control the state of the LIN
output. When TXD is low, LIN output is dominant (near ground). When TXD is high, LIN output is recessive (near
battery). TXD input structure is compatible with microcontrollers with 3.3 V and 5.0 V I/O. This pin has an internal
pull-down resistor.
8.3.2.1 TXD Dominant State Timeout
If the TXD pin is inadvertently driven permanently low by a hardware or software application failure, the LIN bus
is protected by TPIC1021’s Dominant State Timeout Timer. This timer is triggered by a falling edge on the TXD
pin. If the low signal remains on the TXD pin for longer than tDST, the transmitter is disabled thus allowing the LIN
bus to return to the recessive state and communication to resume on the bus. The timer is reset by a rising edge
on TXD pin.
8.3.3 Receive Output Pin (RXD)
This pin is the interface to the LIN protocol controller or SCI/UART of the MCU, which reports the state of the LIN
bus voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground)
is represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the
TPIC1021 to be used with 3.3 V and 5 V I/O microcontrollers. If the microcontroller’s RXD pin does not have an
integrated pull-up, an external pull-up resistor to the microcontroller I/O supply voltage is required.
8.3.3.1 RXD Wake-up Request
When the TPIC1021 has been in low power mode and encounters a wake-up event from the LIN bus or NWake
pin the RXD pin will go LOW while the device enters and remains in Standby Mode (until EN is re-asserted high
and the device enters Normal Mode).
8.3.4 Ground (GND)
This is the TPIC1021 device ground connection. The TPIC1021 can operate with a ground shift as long as the
ground shift does not reduce VSUP below the minimum operating voltage. If there is a loss of ground at the ECU
level, the TPIC1021 will not have a significant current consumption on the LIN pin while in the recessive state
(<100 µA sourced via the LIN pin) and for the dominant state the pull-up resistor should be active.
8.3.5 Enable Input Pin (EN)
The enable input pin controls the operation mode of the TPIC1021 (Normal or Low Power Mode). When enable
is high, the TPIC1021 is in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD.
When the enable input is low, the device is put into low power (sleep) mode and there are no transmission paths.
The device can enter normal operating mode only after being woken up. The enable pin has an internal pulldown resistor to ensure the device remains in low power mode even if the enable pin floats.
8.3.6 NWake Input Pin (NWake)
The NWake input pin is a high-voltage input used to wake up the TPIC1021 from low power mode. NWake is
usually connected to an external switch in the application. A falling edge on NWake with a low that is asserted
longer than the filter time (tNWAKE) results in a local wake-up. The NWake pin provides an internal pull-up current
source to VSUP.
8.3.7 Inhibit Output Pin (INH)
The inhibit output pin is used to control an external voltage regulator that has an inhibit input. When the
TPIC1021 is in normal operating mode, the inhibit high-side switch is enabled and the external voltage regulator
is activated. When TPIC1021 is in low power mode, the inhibit switch is turned off, which disables the voltage
regulator. A wake-up event on for the TPIC1021 will return the INH pin to VSUP level. The INH pin output current
is limited to 2 mA. The INH pin can also drive an external transistor connected to an MCU interrupt input.
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8.4 Device Functional Modes
8.4.1 Operating States
Unpowered
System
A: VSUP < VSUP_under
B: VSUP > VSUP_unde, EN = 0
C:VSUP > VSUP_unde, EN = 1
VSUP < VSUP_under
A
A
A
Standby
Mode
C
EN = 1
Normal Mode
TXD: on
RXD: LIN bus data
IHN: HIGH (high
side switched on)
Term: 30 k
B
TXD: off
RXD: LOW
IHN: HIGH (high
side switched on)
Term: 30 k
LIN Bus Wake−UP
or
NWake Pin Wake−Up
Low Power
Mode
TXD: off
RXD: floating
IHN: high
impedance (high
side switched off)
Term: high
EN = 0
EN = 1
Figure 4. Operating States Diagram
Table 1. Operating Modes
MODE
EN
RXD
LIN BUS
TERMINATION
INH
TRANSMITTER
Low Power
0
Floating
High impedance
High impedance
Off
Standby
0
Low
30 kΩ (typical)
High
Off
Normal
1
LIN bus data
30 kΩ (typical)
High
On
COMMENTS
Wake-up event detected,
waiting on MCU to set EN
8.4.1.1 Normal Mode
This is the normal operational mode where the receiver and driver are active. The receiver detects the data
stream on the LIN bus and outputs it on the RXD pin for the LIN controller where recessive on the LIN bus is a
digital high and dominate on the LIN bus is digital low. The driver will transmit input data on the TXD pin to the
LIN bus.
10
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8.4.1.2 Low Power Mode
The power saving mode for the TPIC1021 and the default state after power-up (assuming EN=0). Even with the
extremely low current consumption in this mode, the TPIC1021 can still wake-up from LIN bus activity, a falling
edge on the NWake pin or if EN is set high. The LIN bus and NWake pins are filtered to prevent false wake-up
events. The wake-up events must be active for their respective time periods: tLINBUS, tNWake.
The low power mode is entered by setting the EN pin low.
While the device is in low power mode the following conditions exist:
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short-circuited to ground).
• The normal receiver is disabled.
• The INH pin is high impedance.
• EN input, NWake input and the LIN wake-up receiver are active.
8.4.1.3 Wake-Up Events
There are three ways to wake-up the TPIC1021 from Low Power Mode.
• Remote wake-up via recessive (high) to dominant (low) state transition on LIN Bus where dominant bus state
of 50% threshold is detected. The dominant state must be held for tLINBUS filter time (to eliminate false wake
ups from disturbances on the LIN Bus).
• Local wake-up via falling edge on NWake pin which is held low for filter time tNWake (to eliminate false wake
ups from disturbances on NWake).
• Local wake-up via EN being set high
8.4.1.4 Standby Mode
This mode is entered whenever a wake-up event occurs via the LIN bus or NWake pin while the TPIC1021 is in
low power mode. The LIN bus slave termination circuit and the INH pin are turned on when standby mode is
entered. The application system will power up once the INH pin is driven high assuming it is using a voltage
regulator connected via INH pin. Standby Mode is signaled via a low level on RXD pin.
When EN pin is set high while the TPIC1021 is in Standby Mode the device returns to Normal Mode and the
normal transmission paths from TXD to LIN bus and LIN bus to RXD are turned on.
LIN
tLINBUS
VSUP
INH
High Impedance
EN
System Wake−Up Time (Vreg + MCU)
RXD
MODE
Floating
Low Power
Standby
Normal
Figure 5. Wake-Up Via LIN Bus Timing Diagram
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Falling Edge on NWake
NWake
tNWake
VSUP
INH
High Impedance
EN
System Wake−Up Time (Vreg + MCU)
RXD
MODE
Floating
Low Power
Standby
Normal
Figure 6. Wake-Up Via NWake Timing Diagram
8.4.2 Supply Voltage (VSUP)
This is the TPIC1021 device power supply pin. This pin is connected to the battery through an external reverse
battery blocking diode. The continuous DC operating voltage range for the TPIC1021 is from 7 V to +27 V. The
VSUP is protected for harsh automotive conditions of up to + 40 V.
The device contains a reset circuit to avoid false bus messages during undervoltage conditions when VSUP is less
than VSUP_UNDER.
12
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SLIS113D – OCTOBER 2004 – REVISED JUNE 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPIC1021 can be used as both a slave device and a master device in a LIN network. It comes with the
ability to support both remote wake-up requests and local wake-up requests.
9.2 Typical Application
The device comes with an integrated 30-kΩ pullup resistor and series diode for slave applications, and for master
applications an external 1-kΩ pullup with series blocking diode can be used. Figure 7 shows the device being
used in both types of applications.
VBAT
VSUP
MASTER
NODE
TPIC7xxxx
VSUP
VDD
NWake
VDD
INH
Master Node
Pull−Up3
VSUP
EN
2
8
3
7
MCU w/o
pull−up2
1 kW
VDD I/O
MCU
V
TPIC1021
TMS430
TMS470
GND
VSUP
LIN
Controller
or
SCI/UART1
bat
RXD
TXD
LIN
1
6
4
220 pF
5
LIN Bus
VDD
SLAVE
NODE
TPIC7xxxx
VSUP
VDD
NWake
INH
VSUP
VDD
EN
2
8
3
7
MCU w/o
pull−up2
VDD I/O
MCU
TPIC1021
TMS430
TMS470
LIN
Controller
or
SCI/UART1
GND
(1)
See 1 in the Design Requirements section
(2)
See 2 in the Design Requirements section
(3)
See 3 in the Design Requirements section
RXD
TXD
LIN
1
4
6
5
220 pF
Figure 7. Typical Application Schematic
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SLIS113D – OCTOBER 2004 – REVISED JUNE 2015
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Typical Application (continued)
9.2.1 Design Requirements
For this design, use these requirements:
1. RXD on MCU or LIN Slave has internal pullup, no external pullup resistor is needed.
2. RXD on MCU or LIN Slave without internal pull-up, requires external pullup resistor.
3. Master Node applications require an external 1-kΩ pullup resistor and serial diode.
9.2.2 Detailed Design Procedure
The RXD output structure is an open-drain output stage. This allows the TPIC1021 to be used with 3.3-V and 5-V
I/O microcontrollers. If the RXD pin of the microcontroller does not have an integrated pull-up, an external pullup
resistor to the microcontroller I/O supply voltage is required.
The VSUP pin of the device should be decoupled with a 100-nF capacitor as close to the supply pin of the device
as possible.
The NWAKE pin is a high voltage wake-up input to the device. If this pin is not being used it should be tied to
VSUP.
9.2.3 Application Curves
Figure 8 and Figure 9 show the propagation delay from the TXD pin to the LIN pin for both the recessive to
dominant and dominant to recessive states under lightly loaded conditions.
Figure 8. Dominant to Recessive Propagation Delay
Figure 9. Recessive to Dominant Propagation Delay
10 Power Supply Recommendations
The TPIC1021 was designed to operate directly off car battery, or any other DC supply ranging from 7 V to 27 V.
A 100-nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.
14
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SLIS113D – OCTOBER 2004 – REVISED JUNE 2015
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
Pin 1 is the RXD output of the TPIC1021. It is an open drain output and requires an external pull-up resistor
in the range of 1 to 10 kΩ to function properly. If the micro-processor paired with the transceiver does not
have an integrated pullup and external resistor should be placed between RXD and the regulated voltage
supply for the micro-processor.
Pin 2 is the EN input pin for the device that is used to place the device in low power sleep mode. If this
feature is not used on the device, the pin should be pulled high to the regulated voltage supply of the microprocessor through a series 1-kΩ to 10-kΩ series resistor. Additionally, a series resistor may be placed on the
pin to limit the current on the digital lines in the case of a overvoltage fault.
Pin 3 is a high-voltage local wake up input pin. The device is typically externally controlled by a normally open
switch tied between NWAKE and ground. When the momentary switch is pressed the NWAKE pin is pulled to
ground signaling a local wake-up event. A series resistor between VBATT and the switch, and NWAKE and
the switch should be placed to limit current. If the NWAKE local wake-up feature is not used, the pin can be
tied to VSUP through a 1-kΩ to 10-kΩ pullup resistor.
Pin 4 is the transmit input signal to the device. A series resistor can be placed to limit the input current to the
device in the case of a overvoltage on this pin. Also a capacitor to ground can be placed close to the input pin
of the device to filter noise.
Pin 5 is the ground connection of the device. This pin should be tied to a ground plane through a short trace
with the use of two vias to limit total return inductance.
Pin 6 is the LIN bus connection of the device. For slave applications a 220pF bus capacitor is implemented.
For master applications an additional series resistor and blocking diode should be placed between the LIN pin
and the VSUP pin.
Pin 7 is the supply pin for the device. A 100-nF decoupling capacitor should be placed as close to the device
as possible.
Pin 8 is a high-voltage output pin that may be used to control the local power supplies. If this feature is not
used the pin may be left floating.
NOTE
All ground and power connections should be made as short as possible and use at least
two vias to minimize the total loop inductance.
11.2 Layout Example
VµC
RXD
C
GND
U1
U1
VSUP
D1
Only needed for
Master Nodes
J1
C9
R3
GND
D3
R2
C1
TXD
INH
R5
VµC
R2
D2
R3
R4
R4
EN
R1
VSUP
GND
GND
GND
GND
Figure 10. Layout Example
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TPIC1021
SLIS113D – OCTOBER 2004 – REVISED JUNE 2015
www.ti.com
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TPIC1021D
NRND
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC1021DG4
NRND
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC1021DR
NRND
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC1021DRG4
NRND
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
T1021
T1021
-40 to 125
T1021
T1021
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPIC1021DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TPIC1021DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPIC1021DR
SOIC
D
8
2500
367.0
367.0
35.0
TPIC1021DRG4
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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