Texas Instruments | DS125BR401 Low-Power, 12.5-Gbps, 4-Lane Repeater With Input Equalization and Output De-Emphasis (Rev. D) | Datasheet | Texas Instruments DS125BR401 Low-Power, 12.5-Gbps, 4-Lane Repeater With Input Equalization and Output De-Emphasis (Rev. D) Datasheet

Texas Instruments DS125BR401 Low-Power, 12.5-Gbps, 4-Lane Repeater With Input Equalization and Output De-Emphasis (Rev. D) Datasheet
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DS125BR401
SNLS419D – JULY 2012 – REVISED MAY 2015
DS125BR401 Low-Power, 12.5-Gbps, 4-Lane Repeater With Input Equalization
and Output De-Emphasis
1 Features
3 Description
•
The DS125BR401 device is an extremely low-power
high-performance multiprotocol repeater and redriver
designed to support four lanes of PCIe Gen-3/2/1,
10G-KR, and other high-speed interface serial
protocols up to 12.5 Gbps. The continuous time linear
equalizer (CTLE) of the receiver provides a boost of
up to 30 dB at 6.25 GHz (12.5 Gbps) in each of its
eight channels and can open an input eye that is
completely closed due to intersymbol interference
(ISI) induced by interconnect medium such as
backplane traces of 30 inches or more or copper
cables of 8 meters or more, hence enabling host
controllers to ensure an error-free end-to-end link.
The transmitter provides a de-emphasis boost of up
to –12 dB and output voltage amplitude control from
700 mV to 1300 mV to allow maximum flexibility in
the physical placement within the interconnect
channel.
1
•
•
•
•
•
•
•
•
•
Comprehensive Family, Proven System
Interoperability
– DS125BR111: 1-Lane Repeater
– DS125BR401: 4-Lane Repeater
– DS125BR800: 8-Channel Repeater
– DS125MB203: 2-Port 2:1/1:2 Mux/Switch
– DS125DF410: 4-Channel Unidirectional
Retimer With CDR
Low 65-mW/Channel (Typical) Power
Consumption, With Option to Power Down
Unused Channels
Nonlimiting Output for PCIe and 10G-KR Link
Training Support
Advanced Signal Conditioning Features
– Receive Equalization up to 30 dB at 6.25 GHz
– Transmit De-Emphasis up to –12 dB
– Transmit Output Voltage Control: 700 mV to
1300 mV
Programmable Through Pin Selection, EEPROM,
or SMBus Interface
Single Supply Voltage: 2.5 V or 3.3 V (Selectable)
−40°C to 85°C Operating Temperature Range
5-kV HBM ESD Rating
Flow-Thru Pinout in 10-mm × 5.5-mm 54-Pin
Leadless WQFN Package
Supported Protocols
– sRIO, Infiniband, Interlaken, CPRI, OBSAI
– Other Proprietary Interface up to 12.5 Gbps
Device Information(1)
PART NUMBER
DS125BR401
PACKAGE
WQFN (54)
•
•
SAS/SATA (up to 6 Gbps), Fibre Channel (up to
10 GFC)
PCIe Gen-3/2/1, 10G-KR, 10GbE, XAUI, RXAUI
10.00 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Typical Application
4
TX
ASIC
or
PCIe EP
Connector
4
RX
DS125BR401
4
2 Applications
BODY SIZE (NOM)
RX
System Board
Root Complex
Connector
4
TX
ard
Bo ce
Tra
DS125BR401
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS125BR401
SNLS419D – JULY 2012 – REVISED MAY 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application ................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
5
8.1
8.2
8.3
8.4
8.5
8.6
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Electrical Characteristics — Serial Management Bus
Interface .................................................................... 9
8.7 Typical Characteristics ............................................ 11
9
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 13
9.5 Programming........................................................... 13
9.6 Register Maps ......................................................... 25
10 Application and Implementation........................ 39
10.1 Application Information.......................................... 39
10.2 Typical Application ............................................... 39
11 Power Supply Recommendations ..................... 43
11.1 3.3-V or 2.5-V Supply Mode Operation................. 43
11.2 Power Supply Bypassing ...................................... 43
12 Layout................................................................... 44
12.1 Layout Guidelines ................................................. 44
12.2 Layout Example .................................................... 44
13 Device and Documentation Support ................. 45
13.1
13.2
13.3
13.4
13.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
45
45
45
45
45
14 Mechanical, Packaging, and Orderable
Information ........................................................... 45
5 Revision History
Changes from Revision C (April 2013) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SNLS419D – JULY 2012 – REVISED MAY 2015
6 Description (continued)
When operating in 10G-KR, and PCIe Gen-3 mode, the DS125BR401 allows the host controller and the end
point to optimize the full link and negotiate transmit equalizer coefficients. This transparency to the link training
protocol can extend the maximum channel loss with minimum latency. With a low power consumption of 65
mW/channel (typical) and the option to turn off unused channels, the DS125BR401 enables energy efficient
system design. A single supply of 3.3 V or 2.5 V is required to power the device.
The programmable settings can be applied easily through pins, software (SMBus or I2C), or loaded through an
external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded
on power up, which eliminates the need for an external microprocessor or software driver.
7 Pin Configuration and Functions
DEMA0/SDA
ENSMB
EQB1/AD2
EQB0/AD3
47
46
DEMA1/SCL
50
48
VDD
49
PWDN
51
DEMB0/AD1
53
52
DEMB1/AD0
54
NJY Package
54-Pin WQFN
Top View
SMBUS AND CONTROL
OUTB_0+
1
45
INB_0+
OUTB_0-
2
44
INB_0-
OUTB_1+
3
43
INB_1+
OUTB_1-
4
42
INB_1-
OUTB_2+
5
41
VDD
OUTB_2-
6
40
INB_2+
OUTB_3+
7
39
INB_2-
OUTB_3-
8
38
INB_3+
VDD
9
37
INB_3-
DAP = GND
INA_0+
10
36
VDD
INA_0-
11
35
OUTA_0+
INA_1+
12
34
OUTA_0-
INA_1-
13
33
OUTA_1+
VDD
14
32
OUTA_1-
INA_2+
15
31
OUTA_2+
23
24
25
26
27
VIN
VDD_SEL
SD_TH/READ_EN
ALL_DONE
EQA1
LPBK
OUTA_3-
22
28
RXDET
18
21
INA_3-
20
OUTA_2OUTA_3+
EQA0
30
29
MODE
16
17
19
INA_2INA_3+
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SNLS419D – JULY 2012 – REVISED MAY 2015
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Pin Functions (1)
PIN
NAME
I/O, TYPE
NUMBER
DESCRIPTION
DIFFERENTIAL HIGH-SPEED I/Os
INB_0+, INB_0-, INB_1+,
INB_1-, INB_2+, INB_2-,
INB_3+, INB_3-
45, 44, 43, 42
40, 39, 38, 37
I
Inverting and noninverting CML differential inputs to the equalizer. Onchip 50-Ω termination resistor connects INB_n+ to VDD and INB_n- to
VDD when enabled.
AC coupling required on high-speed I/O
OUTB_0+,
OUTB_1+,
OUTB_2+,
OUTB_3+,
1, 2, 3, 4
5, 6, 7, 8
O
Inverting and noninverting 50-Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
INA_0+, INA_0-, INA_1+,
INA_1-, INA_2+, INA_2-,
INA_3+, INA_3-
10, 11, 12, 13
15, 16, 17, 18
I
Inverting and noninverting CML differential inputs to the equalizer. Onchip 50-Ω termination resistor connects INA_n+ to VDD and INA_n- to
VDD when enabled.
AC coupling required on high-speed I/O
OUTA_0+,
OUTA_1+,
OUTA_2+,
OUTA_3+,
35, 34, 33, 32
31, 30, 29, 28
O
Inverting and noninverting 50-Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
I, 4-LEVEL,
LVCMOS
System Management Bus (SMBus) Enable pin
Tie 1 kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1 kΩ to GND = Pin Mode
OUTB_0-,
OUTB_1-,
OUTB_2-,
OUTB_3-
OUTA_0-,
OUTA_1-,
OUTA_2-,
OUTA_3-
CONTROL PINS — SHARED (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
I, 2-LEVEL,
LVCMOS,
O, OPEN Drain
ENSMB Master or Slave mode
SMBUS clock input pin is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
SDA
49
I, 2-LEVEL,
LVCMOS,
O, OPEN Drain
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open-drain
(pulldown only) output.
AD0-AD3
54, 53, 47, 46
I, 4-LEVEL,
LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs.
There are 16 addresses supported by these pins. Pins must be tied LOW
or HIGH when used to define the device SMBus address.
READ_EN
26
I, 2-LEVEL,
LVCMOS
When using an External EEPROM, a transition from high to low starts
the load from the external EEPROM
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization of the A/B sides
as shown in . The pins are active only when ENSMB is deasserted (low).
Each of the 4 A/B channels have the same level unless controlled by the
SMBus control registers. When ENSMB goes high the SMBus registers
provide independent control of each lane. The EQB[1:0] pins are
converted to SMBUS AD2, AD3 inputs. See Table 2.
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the A/B
sides as shown in . The pins are only active when ENSMB is deasserted
(low). Each of the 4 A/B channels have the same level unless controlled
by the SMBus control registers. When ENSMB goes high the SMBus
registers provide independent control of each lane. The DEMA[1:0] pins
are converted to SMBUS SCL/SDA and DEMB[1:0] pins are converted to
AD0, AD1 inputs. See Table 3.
ENSMB = 0 (PIN MODE)
(1)
4
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
For 2.5-V mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.
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Pin Functions(1) (continued)
PIN
NAME
I/O, TYPE
NUMBER
DESCRIPTION
MODE
21
I, 4-LEVEL,
LVCMOS
MODE control pin selects operating modes.
Tie 1 kΩ to GND = PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to
6 Gbps)
FLOAT = AUTO Rate Select (for PCIe)
Tie 20 kΩ to GND = PCIe Gen-3 without De-emphasis
Tie 1 kΩ to VDD = 10G-KR
See Table 6
SD_TH
26
I, 4-LEVEL,
LVCMOS
Controls the internal Signal Detect Threshold.
For datarates above 8 Gbps the Signal Detect function should be
disabled to avoid potential for intermittent data loss. See Table 5.
CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS)
RXDET
22
I, 4-LEVEL,
LVCMOS
The RXDET pin controls the receiver detect function. Depending on the
input level, a 50 Ω or >50 kΩ termination to the power rail is enabled.
See Table 4.
LPBK
23
I, 4-LEVEL,
LVCMOS
Controls the loopback function
Tie 1 kΩ to GND = Root Complex Loopback (INA_n to OUTB_n)
Float = Normal Operation
Tie 1 kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
VDD_SEL
25
I, LVCMOS
Controls the internal regulator
Float = 2.5-V mode
Tie GND = 3.3-V mode
PWDN
52
I, LVCMOS
Tie High = Low power - power down
Tie GND = Normal Operation
See Table 4.
ALL_DONE
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
VIN
24
Power
In 3.3-V mode, feed 3.3 V to VIN
In 2.5-V mode, leave floating.
VDD
9, 14,36, 41, 51
Power
Power supply pins CML/analog
2.5-V mode, connect to 2.5 V
3.3-V mode, connect 0.1-µF capacitor to each VDD pin
GND
DAP
Power
Ground pad (DAP - die attach pad). See Power Supply
Recommendations for proper power supply decoupling.
POWER
8 Specifications
8.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
Supply Voltage (VDD - 2.5 V)
–0.5
2.75
V
Supply Voltage (VIN - 3.3 V)
–0.5
4
V
LVCMOS Input/Output Voltage
–0.5
4
V
CML Input Voltage
–0.5
(VDD + 0.5)
V
CML Input Current
–30
30
mA
Junction Temperature
125
°C
Lead Temperature Range Soldering (4 sec.) (2)
260
°C
125
°C
Storage Temperature, Tstg
(1)
(2)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications: See application note SNOA549.
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8.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±5000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
Machine model (MM), JESD22-A115-A
±150
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be
operated beyond such conditions. Absolute maximum numbers are specified for a junction temperature range of –40°C to
125°C. Models are validated to maximum operating voltages only.
MIN
NOM
MAX
UNIT
Supply Voltage (2.5-V mode)
2.375
2.5
2.625
V
Supply Voltage (3.3-V mode)
3.0
3.3
3.6
V
Ambient Temperature
–40
25
85
°C
3.6
V
100
mVp-p
SMBus (SDA, SCL)
Supply Noise up to 50 MHz
(1)
(1)
Allowed supply noise (mVp-p sine wave) under typical conditions.
8.4 Thermal Information
DS125BR401
THERMAL METRIC (1)
NJY [WQFN]
UNIT
54 PINS
RθJA
Junction-to-ambient thermal resistance
26.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.8
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8.5 Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
POWER
PD
Power Dissipation
VDD = 2.5-V supply, EQ Enabled,
VOD = 1 Vp-p, RXDET = 1, PWDN = 0
500
700
VIN = 3.3-V supply, EQ Enabled,
VOD = 1 Vp-p, RXDET = 1, PWDN = 0
660
900
mW
LVCMOS / LVTTL DC SPECIFICATIONS
VIH25
High Level Input Voltage
2.5-V Mode
2.0
VDD
V
VIH33
High Level Input Voltage
3.3-V Mode
2.0
VIN
V
VIL
Low Level Input Voltage
0
0.8
V
VOH
High Level Output Voltage
(ALL_DONE pin)
Ioh = –4 mA
VOL
Low Level Output Voltage
(ALL_DONE pin)
Iol = 4 mA
IIH
Input High Current (PWDN pin)
Input High Current with internal
resistors
(4-level input pin)
6
VIN = 3.6 V,
LVCMOS = 3.6 V
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2.0
V
0.4
–15
15
20
150
V
µA
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Electrical Characteristics (continued)
PARAMETER
IIL
TEST CONDITIONS
Input Low Current (PWDN pin)
VIN = 3.6 V,
LVCMOS = 0 V
Input Low Current with internal
resistors
(4-level input pin)
MIN
TYP MAX
–15
15
–160
–40
UNIT
µA
CML RECEIVER INPUTS (IN_N+, IN_N-)
RLRX-DIFF
0.05 - 7.5 GHz
RX Differential return loss
–15
7.5 - 15 GHz
dB
–5
RLRX-CM
RX Common mode return loss
0.05 - 5 GHz
ZRX-DC
RX DC common mode impedance
Tested at VDD = 2.5 V
40
–10
50
60
dB
Ω
ZRX-DIFF-DC
RX DC differential mode impedance
Tested at VDD = 2.5 V
80
100
120
Ω
VRX-DIFF-DC
Differential RX peak-to-peak voltage
(VID)
Tested at pins
1.2
V
VRX-SIGNAL-DET- Signal detect assert level for active
data signal
DIFF-PP
SD_TH = F (float), 0101 pattern at 8 Gbps
180
mVp-p
VRX-IDLE-DET-
SD_TH = F (float), 0101 pattern at 8 Gbps
110
mVp-p
DIFF-PP
Signal detect deassert level for
electrical idle
HIGH SPEED OUTPUTS
VTX-DIFF-PP
Output Voltage Differential Swing
Differential measurement with Out_n+ and
OUT_n-, terminated by 50 Ω to GND,
AC-Coupled, VID = 1 Vp-p,
DEM0 = 1, DEM1 = 0 (1)
TX de-emphasis ratio
VOD = 1 Vp-p, DEM0 = 0, DEM1 = R,
PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up
to 6 Gbps)
–3.5
dB
TX de-emphasis ratio
VOD = 1 Vp-p, DEM0 = R, DEM1 = R,
PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up
to 6 Gbps)
–6
dB
VTX-DERATIO_3.5
VTX-DE-RATIO_6
0.8
1
1.2
Vp-p
TTX-DJ
Deterministic Jitter
VID = 800 mV, PRBS15 pattern, 8.0 Gbps, VOD
= 1 V, EQ = 0x00, DE = 0 dB, (no input or output
trace loss)
0.05
UIpp
TTX-RJ
Random Jitter
VID = 800 mV, 0101 pattern, 8.0 Gbps, VOD = 1
V, EQ = 0x00, DE = 0 dB, (no input or output
trace loss)
0.3
ps RMS
TTX-RISE-FALL
Transmitter rise/fall time
20% to 80% of differential output voltage
TRF-MISMATCH
Transmitter rise/fall mismatch
20% to 80% of differential output voltage
0.01
0.05 - 7.5 GHz
–15
RLTX-DIFF
TX Differential return loss
RLTX-CM
TX Common mode return loss
ZTX-DIFF-DC
DC differential TX impedance
35
–10
dB
100
Ω
ITX-SHORT
Transmitter short circuit current limit
Total current the transmitter can supply when
shorted to VDD or GND
DELTA
TTX-IDLE-DATA
(1)
dB
0.05 - 5 GHz
TX AC common mode voltage
VTX-CM-DC-LINE-
UI
–5
VOD = 1 Vp-p,
DEM0 = 1, DEM1 = 0
ACTIVE-IDLEDELTA
ps
0.1
7.5 - 15 GHz
VTX-CM-AC-PP
VTX-CM-DC-
45
100
20
mVp-p
mA
Absolute delta of DC common mode
voltage during L0 and electrical idle
100
mV
Absolute delta of DC common mode
voltage between TX+ and TX-
25
mV
Max time to transition to valid
differential signal after idle
VID = 1 Vp-p, 8 Gbps
3.5
ns
In PCIe Gen-3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The
output VOD level set by DEMA/B[1:0] in this MODE is dependent on the VID level and the frequency content. The DS125BR401
repeater is designed to be nonlimiting in this MODE, so the TX-FIR (de-emphasis) is passed to the RX to support the handshake
negotiation link training.
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Electrical Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
TTX-DATA-IDLE
Max time to transition to idle after
differential signal
VID = 1 Vp-p, 8 Gbps
6.2
ns
TPDEQ
Differential propagation delay
EQ = 00 (2)
200
ps
TLSK
Lane-to-lane skew
T = 25°C, VDD = 2.5 V
25
ps
TPPSK
Part-to-part propagation delay skew
T = 25°C, VDD = 2.5 V
40
ps
Residual deterministic jitter at 12 Gbps
30” 5mils FR4, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB
0.18
UIpp
Residual deterministic jitter at 8 Gbps
30” 5mils FR4, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB
0.11
UIpp
Residual deterministic jitter at 5 Gbps
30” 5mils FR4, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB
0.07
UIpp
Residual deterministic jitter at 12 Gbps
5-meter 30-AWG cable, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB
0.25
UIpp
Residual deterministic jitter at 12 Gbps
8-meter 30-AWG cable, VID = 0.6 Vp-p,
PRBS15, EQ = 0x0F, DEM = 0 dB
0.33
UIpp
0.1
UIpp
EQUALIZATION
DJE1
DJE2
DJE3
DJE4
DJE5
DE-EMPHASIS — PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps)
DJD1
Residual deterministic jitter at 12 Gbps
(2)
8
Input Channel: 20" 5mils FR4,
Output Channel: 10” 5mils FR4,
VID = 0.6 Vp-p, PRBS15, EQ = 0x03,
VOD = 1 Vp-p, DEM = −3.5 dB
Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the longest propagation
delays.
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8.6 Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pullup Resistor or
Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SCL
See (1) (2)
RTERM
External Termination Resistance pull to
VDD = 2.5 V ± 5% OR 3.3 V ± 10%
Pullup VDD = 3.3 V (1) (2) (3)
2000
Pullup VDD = 2.5 V (1) (2) (3)
1000
2.1
High Power Specification
See (1)
0.8
V
3.6
V
4
mA
2.375
3.6
V
–200
200
µA
–15
µA
10
pF
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
TBUF
Bus Free Time Between Stop and Start
Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
400
280
400
520
kHz
1.3
µs
0.6
µs
At IPULLUP, Max
TSU:STA
Repeated Start Condition Setup Time
0.6
µs
TSU:STO
Stop Condition Setup Time
0.6
µs
THD:DAT
Data Hold Time
0
ns
TSU:DAT
Data Setup Time
100
ns
TLOW
Clock Low Period
1.3
µs
(4)
THIGH
Clock High Period
See
50
µs
tF
Clock/Data Fall Time
See (4)
300
ns
tR
Clock/Data Rise Time
See (4)
300
ns
tPOR
Time in which a device must be
operational after power-on reset
See (4) (5)
500
ms
(1)
(2)
(3)
(4)
(5)
0.6
Recommended value.
Recommended maximum capacitance load per bus segment is 400 pF.
Maximum termination voltage should be identical to the device supply voltage.
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
Ensured by Design. Parameter not tested in production.
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80%
80%
VOD = [Out+ - Out-]
0V
20%
20%
tRISE
tFALL
Figure 1. CML Output and Rise and FALL Transition Time
IN
0V
tPLHD
OUT
tPHLD
0V
Figure 2. Propagation Delay Timing Diagram
+
IN
0V
DATA
tIDLE-DATA
tDATA-IDLE
+
OUT
0V
DATA
IDLE
IDLE
Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
SP
ST
Figure 4. SMBus Timing Parameters
10
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8.7 Typical Characteristics
1021
640.0
VDD = 2.625V
620.0
T = 25°C
VDD = 2.5V
600.0
1019
VDD = 2.375V
560.0
VOD (mVp-p)
PD (mW)
580.0
540.0
520.0
500.0
1016
1013
480.0
1010
T = 25oC
460.0
440.0
1007
2.375
420.0
0.8
0.9
1
1.1
1.2
1.3
VOD (Vp-p)
2.5
2.625
VDD (V)
Figure 5. Power Dissipation (PD)
vs Output Differential Voltage (VOD)
Figure 6. Output Differential Voltage (VOD = 1 Vp-p)
vs Supply Voltage (VDD)
1020
VDD = 2.5 V
VOD (mVp-p)
1018
1016
1014
1012
- 40
-15
10
35
60
85
TEMPERATURE (°C)
Figure 7. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature
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9 Detailed Description
9.1 Overview
The DS125BR401 device compensates for lossy printed-circuit-board (PCB) backplanes and balanced cables.
The DS125BR401 compensates for lossy FR-4 PCB backplanes and balanced cables. The DS125BR401
operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master
Mode (ENSMB = float) to load register informations from external EEPROM; refer to SMBUS Master Mode for
additional information.
9.2 Functional Block Diagram
VDD
Auto/Manual
RXDET
INx_n+
RATE
DET
VOD/DeEMPHASIS
CONTROL
DEMA/B
SMBus
EQ
OUTBUF
INx_n-
OUTx_n+
OUTx_n-
TX Idle Enable
IDLE
DET
EQA/B
SMBus
SMBus
Figure 8. Block Diagram - Detail View Of Channel (1 Of 8)
9.3 Feature Description
The 4-level input pins use a resistor divider to help
settings when ENSMB=0. There is an internal 30-kΩ
These resistors, together with the external resistor
Using the 1-kΩ pullup, 1-kΩ pulldown, no connect,
each of the four input states.
set the 4 valid levels and provide a wider range of control
pullup and a 60-kΩ pulldown connected to the package pin.
connection combine to achieve the desired voltage level.
and 20-kΩ pulldown provide the optimal voltage levels for
Table 1. 4–Level Control Pin Settings
LEVEL
SETTING
3.3-V MODE
2.5-V MODE
0
Tie 1 kΩ to GND
0.10 V
0.08 V
R
Tie 20 kΩ to GND
1/3 × VIN
1/3 × VDD
Float
Float (leave pin open)
2/3 × VIN
2/3 × VDD
1
Tie 1 kΩ to VIN or VDD
VIN – 0.05 V
VDD – 0.04 V
9.3.1 Typical 4-Level Input Thresholds
• Level 1 - 2 = 0.2 × VIN or VDD
• Level 2 - 3 = 0.5 × VIN or VDD
• Level 3 - 4 = 0.8 × VIN or VDD
To minimize the start-up current associated with the integrated 2.5-V regulator, TI recommends using the 1-kΩ
pullup and pulldown resistors. If several 4-level inputs require the same setting, it is possible to combine two or
more 1-kΩ resistors into a single lower value resistor. As an example; combining two inputs with a single 500-Ω
resistor is a good way to save board space.
12
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9.4 Device Functional Modes
9.4.1 Pin Control Mode
When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected through pin for each side
independently. When de-emphasis is asserted VOD is automatically adjusted per Table 3. For PCIe applications,
the RXDET pins provides automatic and manual control for input termination (50 Ω or >50 kΩ). MODE setting is
also pin controllable with pin selections (PCIe Gen-1, PCIe Gen-2, auto detect, and PCIe Gen-3). The receiver
electrical idle detect threshold is also adjustable through the SD_TH pin.
9.4.2 SMBUS Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx
and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (MODE,
RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit
is set, in which case they are ignored until ENSMB is driven low (pin mode). On power up and when ENSMB is
driven low all registers are reset to their default state. If PWDN is asserted while ENSMB is high, the registers
retain their current state.
Equalization settings accessible through the pin controls were chosen to meet the needs of most high speed
applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed
through the SMBus registers. Each input has a total of 256 possible equalization settings. System Management
Bus (SMBus) and Configuration Registers show the 16 setting when the device is in pin mode. When using
SMBus mode, the equalization, VOD and de-emphasis levels are set by registers.
9.5 Programming
9.5.1 PCIe Signal Integrity
When using the DS125BR401 in PCIe Gen-3 systems, there are specific signal integrity settings to ensure signal
integrity margin. The settings were optimized by extensive testing. Contact your field representative for more
information regarding the testing completed to achieve these settings.
For tuning the in the downstream direction (from CPU to EP).
• EQ: use the guidelines outlined in Table 2.
• De-Emphasis: use the guidelines outlined in Table 3.
• VOD: use the guidelines outlined in Table 3.
For tuning in the upstream direction (from EP to CPU).
• EQ: use the guidelines outlined in Table 2.
• De-Emphasis:
– For trace lengths < 15 in set to –3.5 dB
– For trace lengths > 15 in set to –6 dB
• VOD: set to 900 mV
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Programming (continued)
Table 2. Equalizer Settings
LEVEL
EQA1
EQB1
EQA0
EQB
EQ – 8 bits [7:0]
dB at
1.5 GHz
dB at
2.5 GHz
dB at
4 GHz
dB at
6 GHz
SUGGESTED USE (1)
1
0
0
0000 0000 = 0x00
2.5
3.5
3.8
3.1
FR4 < 5-inch trace
2
0
R
0000 0001 = 0x01
3.8
5.4
6.7
6.7
FR4 5- to 10-inch trace
3
0
Float
0000 0010 = 0x02
5
7
8.4
8.4
FR4 10-inch trace
4
0
1
0000 0011 = 0x03
5.9
8
9.3
9.1
FR4 15- to 20-inch trace
5
R
0
0000 0111 = 0x07
7.4
10.3
12.8
13.7
FR4 20- to 30-inch trace
6
R
R
0001 0101 = 0x15
6.9
10.2
13.9
16.2
FR4 25- to 30-inch trace
7
R
Float
0000 1011 = 0x0B
9
12.4
15.3
15.9
FR4 25- to 30-inch trace
8
R
1
0000 1111 = 0x0F
10.2
13.8
16.7
17
8-m, 30-AWG cable
> 8-m cable
(1)
14
9
Float
0
0101 0101 = 0x55
8.5
12.6
17.5
20.7
10
Float
R
0001 1111 = 0x1F
11.7
16.2
20.3
21.8
11
Float
Float
0010 1111 = 0x2F
13.2
18.3
22.8
23.6
12
Float
1
0011 1111 = 0x3F
14.4
19.8
24.2
24.7
13
1
0
1010 1010 = 0xAA
14.4
20.5
26.4
28
14
1
R
0111 1111 = 0x7F
16
22.2
27.8
29.2
15
1
Float
1011 1111 = 0xBF
17.6
24.4
30.2
30.9
16
1
1
1111 1111 = 0xFF
18.7
25.8
31.6
31.9
Cable and FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace
separation. Optimal EQ setting should be determined through simulation and prototype verification.
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Table 3. Output Voltage and De-Emphasis Settings
LEVEL
DEMA1
DEMB1
DEMA0
DEMB0
VOD Vp-p
DEM dB (1)
INNER AMPLITUDE
Vp-p
SUGGESTED USE (2)
1
0
0
0.8
0
0.8
FR4 <5-inch trace
2
0
R
0.9
0
0.9
FR4 <5-inch trace
3
0
Float
0.9
–3.5
0.6
FR4 10-inch trace
4
0
1
1
0
1
FR4 <5-inch trace
5
R
0
1
–3.5
0.7
FR4 10-inch trace
6
R
R
1
–6
0.5
FR4 15-inch trace
7
R
Float
1.1
0
1.1
FR4 <5-inch trace
8
R
1
1.1
–3.5
0.7
FR4 10-inch trace
9
Float
0
1.1
–6
0.6
FR4 15-inch trace
10
Float
R
1.2
0
1.2
FR4 <5-inch trace
11
Float
Float
1.2
–3.5
0.8
FR4 10-inch trace
12
Float
1
1.2
–6
0.6
FR4 15-inch trace
13
1
0
1.3
0
1.3
FR4 <5-inch trace
14
1
R
1.3
–3.5
0.9
FR4 10-inch trace
15
1
Float
1.3
–6
0.7
FR4 15-inch trace
16
1
1
1.3
–9
0.5
FR4 20-inch trace
(1)
(2)
The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are also available in PCIe Gen-3 mode when MODE = 1 (tied to VDD).
FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace separation.
Optimal DEM settings should be determined through simulation and prototype verification.
Table 4. RX-Detect Settings
PWDN
(PIN 52)
RXDET
(PIN 22)
SMBus REG
bit[3:2]
INPUT
TERMINATION
RECOMMENDED
USE
0
0
00
Hi-Z
X
0
Tie 20 kΩ
to GND
01
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe only
COMMENTS
Manual RX-Detect, input is high impedance
mode
Auto RX-Detect, outputs test every 12 msec for
600 msec then stops; termination is Hi-Z until
RX detection; once detected input termination
is 50 Ω
Reset function by pulsing PWDN high for 5
usec then low again
0
Float
(Default)
10
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe only
Auto RX-Detect, outputs test every 12 msec
until detection occurs; termination is Hi-Z until
RX detection; once detected input termination
is 50 Ω
0
1
11
50 Ω
All Others
Manual RX-Detect, input is 50 Ω
1
X
High Impedance
X
Power-down mode, input is Hi-Z, output drivers
are disabled
Used to reset RX-Detect State Machine when
held high for 5 usec
9.5.1.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
Unlike PCIe systems, SAS/SATA (up to 6 Gbps) systems use a low speed Out-Of-Band or OOB communications
sequence to detect and communicate between Controllers/Expanders and target drives. This communication
eliminates the need to detect for endpoints like PCIe. For SAS/SATA systems, TI recommends tying the RXDET
pin high. This will ensure any OOB sequences sent from the Controller/Expander will reach the target drive
without any additional latency due to the termination detection sequence defined by PCIe.
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Table 5. Signal Detect Threshold Level (1)
(1)
SD_TH (PIN 26)
SMBus REG bit [3:2] and [1:0]
ASSERT LEVEL (TYP)
DEASSERT LEVEL (TYP)
0
10
210 mVp-p
150 mVp-p
R
01
160 mVp-p
100 mVp-p
F (default)
00
180 mVp-p
110 mVp-p
1
11
190 mVp-p
130 mVp-p
VDD = 2.5V, 25°C and 0101 pattern at 8 Gbps
9.5.1.1.1 Signal Detect Control for Datarates Above 8 Gbps
Signal detect bandwidth limitations combined with high levels of signal attenuation can result in intermittent data
loss above 8 Gbps. This data loss can be eliminated by disabling automatic detection and forcing the Signal
Detect function to be always "on". This programming requires SMBus control over the DS125BR401 to be
present. The Signal Detect function is controlled for each channel independently. The register programming
sequence is shown below:
1. Write register 0x06 = 0x18 //* Enable SMBus register programming
2. Write registers 0x0D[1]= 1'b, 0x14[1] = 1'b, 0x1B[1] = 1'b, 0x22[1] = 1'b //* CH0 - CH3
3. Write registers 0x2A[1]= 1'b, 0x31[1] = 1'b, 0x38[1] = 1'b, 0x3F[1] = 1'b //* CH4 - CH7
Table 6. MODE Operation with Pin Control
MODE
(PIN 21)
Driver Characteristics
0
Limiting
R
Nonlimiting without DE
F (default)
Automatic
1
Nonlimiting with DE
PCIe
SAS
SATA
10G-KR
X
10GbE
CPRI
OBSAI
SRIO
(R)XAUI
Interlaken
Infiniband
X
X
X
X
X
X
Note: Automatic operation allows input to sense the incoming data rate and use a Nonlimiting output driver for
operation at or above 8 Gbps.
Note: SAS/SATA up to 6 Gbps.
9.5.1.2 MODE Operation With SMBus Registers
When in SMBus mode (Slave or Master), the MODE pin retains control of the output driver characteristics. In
order to override this control function, Register 0x08[2] must be written with a "1". Writing this bit enables MODE
control of each channel individually using the channel registers defined in Table 7.
16
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9.5.2 SMBUS Master Mode
The DS125BR401 device supports reading directly from an external EEPROM device by implementing SMBus
Master mode. When using the SMBus master mode, the DS125BR401 will read directly from specific location in
the external EEPROM. When designing a system for using the external EEPROM, the user must follow these
specific guidelines. For additional information, refer to SNLA228.
• Set ENSMB = Float — enable the SMBUS master mode.
• The external EEPROM device address byte must be 0xA0 and capable of 1-MHz operation at 2.5-V and 3.3V supply.
• Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.
When tying multiple DS125BR401 devices to the SDA and SCL bus, use these guidelines to configure the
devices.
• Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM.
Example below is for four devices.
– U1: AD[3:0] = 0000 = 0xB0,
– U2: AD[3:0] = 0001 = 0xB2,
– U3: AD[3:0] = 0010 = 0xB4,
– U4: AD[3:0] = 0011 = 0xB6
• Use a pullup resistor on SDA and SCL; value = 2 kΩ
• Daisy-chain READ_EN (pin 26) and ALL_DONE (pin 27) from one device to the next device in the sequence
so that they do not compete for the EEPROM at the same time.
1. Tie READ_EN of the first device in the chain (U1) to GND
2. Tie ALL_DONE of U1 to READ_EN of U2
3. Tie ALL_DONE of U2 to READ_EN of U3
4. Tie ALL_DONE of U3 to READ_EN of U4
5. Optional: Tie ALL_DONE output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS125BR401 device. The first 3
bytes of the EEPROM always contain a header common and necessary to control initialization of all devices
connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed
pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a
MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the
MAP bit is not present the configuration data start address is derived from the DS125BR401 address and the
configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the
EEPROM. There are 37 bytes of data size for each DS125BR401 device. For additional information on EEPROM
programming, refer to SNLA228.
spacer
:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
NOTE
The maximum EEPROM size supported is 8-kbits (1024 × 8 bits).
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Table 7. EEPROM Register Map - Single Device With Default Value
EEPROM Address Byte
Description
Default Value
0x00
0x00
Description
Default Value
0x01
0x00
Description
Default Value
0x02
0x00
Description
0x03
SMBus Register
Default Value
0x00
Description
0x04
SMBus Register
Default Value
00
Description
0x05
SMBus Register
Default Value
04
Description
0x06
SMBus Register
Default Value
07
Description
0x07
SMBus Register
Default Value
00
Description
0x08
SMBus Register
Default Value
2F
Description
0x09
SMBus Register
Default Value
AD
Description
0x0A
SMBus Register
Default Value
18
40
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
CRC EN
Address Map
Present
EEPROM > 256
Bytes
Reserved
DEVICE COUNT[3] DEVICE COUNT[2] DEVICE COUNT[1] DEVICE COUNT[0]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Max EEPROM Burst
size[7]
Max EEPROM
Burst size[6]
Max EEPROM
Burst size[5]
Max EEPROM
Burst size[4]
Max EEPROM
Burst size[3]
Max EEPROM
Burst size[2]
Max EEPROM
Burst size[1]
Max EEPROM Burst
size[0]
0
0
0
0
0
0
0
0
PWDN_ch7
PWDN_ch6
PWDN_ch5
PWDN_ch4
PWDN_ch3
PWDN_ch2
PWDN_ch1
PWDN_ch0
0x01 [7]
0x01 [6]
0x01 [5]
0x01 [4]
0x01 [3]
0x01 [2]
0x01 [1]
0x01 [0]
0
0
0
0
0
0
0
0
lpbk_1
lpbk_0
PWDN_INPUTS
PWDN_OSC
Ovrd_PWDN
Reserved
Reserved
Reserved
0x02 [5]
0x02 [4]
0x02 [3]
0x02 [2]
0x02 [0]
0x04 [7]
0x04 [6]
0x04 [5]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
rxdet_btb_en
Ovrd_idle_th
Ovrd_RES
0x04 [4]
0x04 [3]
0x04 [2]
0x04 [1]
0x04 [0]
0x06 [4]
0x08 [6]
0x08 [5]
0
0
0
0
0
1
0
0
Ovrd_IDLE
Ovrd_RX_DET
Ovrd_MODE
Ovrd_RES
Ovrd_RES
rx_delay_sel_2
rx_delay_sel_1
rx_delay_sel_0
0x08 [4]
0x08 [3]
0x08 [2]
0x08 [1]
0x08 [0]
0x0B [6]
0x0B [5]
0x0B [4]
0
0
0
0
0
1
1
1
RD_delay_sel_3
RD_delay_sel_2
RD_delay_sel_1
RD_delay_sel_0
ch0_Idle_auto
ch0_Idle_sel
ch0_RXDET_1
ch0_RXDET_0
0x0B [3]
0x0B [2]
0x0B [1]
0x0B [0]
0x0E [5]
0x0E [4]
0x0E [3]
0x0E [2]
0
0
0
0
0
0
0
0
ch0_BST_7
ch0_BST_6
ch0_BST_5
ch0_BST_4
ch0_BST_3
ch0_BST_2
ch0_BST_1
ch0_BST_0
0x0F [7]
0x0F [6]
0x0F [5]
0x0F [4]
0x0F [3]
0x0F [2]
0x0F [1]
0x0F [0]
0
0
1
0
1
1
1
1
ch0_Sel_scp
ch0_Sel_mode
ch0_RES_2
ch0_RES_1
ch0_RES_0
ch0_VOD_2
ch0_VOD_1
ch0_VOD_0
0x10 [7]
0x10 [6]
0x10 [5]
0x10 [4]
0x10 [3]
0x10 [2]
0x10 [1]
0x10 [0]
1
0
1
0
1
1
0
1
ch0_DEM_2
ch0_DEM_1
ch0_DEM_0
ch0_Slow
ch0_idle_tha_1
ch0_idle_tha_0
ch0_idle_thd_1
ch0_idle_thd_0
0x11 [2]
0x11 [1]
0x11 [0]
0x12 [7]
0x12 [3]
0x12 [2]
0x12 [1]
0x12 [0]
0
1
0
0
0
0
0
0
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Table 7. EEPROM Register Map - Single Device With Default Value (continued)
EEPROM Address Byte
Description
0x0B
SMBus Register
Default Value
02
Description
0x0C
SMBus Register
Default Value
FA
Description
0x0D
SMBus Register
Default Value
2F
Description
0x0E
SMBus Register
Default Value
00
Description
0x0F
SMBus Register
Default Value
2F
Description
0x10
SMBus Register
Default Value
AD
Description
0x11
SMBus Register
Default Value
40
Description
0x12
SMBus Register
Default Value
02
Description
0x13
SMBus Register
Default Value
FA
Description
0x14
SMBus Register
Default Value
D4
Description
0x15
SMBus Register
Default Value
09
Bit 3
Bit 2
Bit 1
ch1_Idle_auto
Bit 7
ch1_Idle_sel
Bit 6
ch1_RXDET_1
Bit 5
ch1_RXDET_0
Bit 4
ch1_BST_7
ch1_BST_6
ch1_BST_5
ch1_BST_4
BIt 0
0x15 [5]
0x15 [4]
0x15 [3]
0x15 [2]
0x16 [7]
0x16 [6]
0x16 [5]
0x16 [4]
0
0
0
0
0
0
1
0
ch1_BST_3
ch1_BST_2
ch1_BST_1
ch1_BST_0
ch1_Sel_scp
ch1_Sel_mode
ch1_RES_2
ch1_RES_1
0x16 [3]
0x16 [2]
0x16 [1]
0x16 [0]
0x17 [7]
0x17 [6]
0x17 [5]
0x17 [4]
1
1
1
1
1
0
1
0
ch1_RES_0
ch1_VOD_2
ch1_VOD_1
ch1_VOD_0
ch1_DEM_2
ch1_DEM_1
ch1_DEM_0
ch1_Slow
0x17 [3]
0x17 [2]
0x17 [1]
0x17 [0]
0x18 [2]
0x18 [1]
0x18 [0]
0x19 [7]
1
1
0
1
0
1
0
0
ch1_idle_tha_1
ch1_idle_tha_0
ch1_idle_thd_1
ch1_idle_thd_0
ch2_Idle_auto
ch2_Idle_sel
ch2_RXDET_1
ch2_RXDET_0
0x19 [3]
0x19 [2]
0x19 [1]
0x19 [0]
0x1C [5]
0x1C [4]
0x1C [3]
0x1C [2]
0
0
0
0
0
0
0
0
ch2_BST_7
ch2_BST_6
ch2_BST_5
ch2_BST_4
ch2_BST_3
ch2_BST_2
ch2_BST_1
ch2_BST_0
0x1D [7]
0x1D [6]
0x1D [5]
0x1D [4]
0x1D [3]
0x1D [2]
0x1D [1]
0x1D [0]
0
0
1
0
1
1
1
1
ch2_Sel_scp
ch2_Sel_mode
ch2_RES_2
ch2_RES_1
ch2_RES_0
ch2_VOD_2
ch2_VOD_1
ch2_VOD_0
0x1E [7]
0x1E [6]
0x1E [5]
0x1E [4]
0x1E [3]
0x1E [2]
0x1E [1]
0x1E [0]
1
0
1
0
1
1
0
1
ch2_DEM_2
ch2_DEM_1
ch2_DEM_0
ch2_Slow
ch2_idle_tha_1
ch2_idle_tha_0
ch2_idle_thd_1
ch2_idle_thd_0
0x1F [2]
0x1F [1]
0x1F [0]
0x20 [7]
0x20 [3]
0x20 [2]
0x20 [1]
0x20 [0]
0
1
0
0
0
0
0
0
ch3_Idle_auto
ch3_Idle_sel
ch3_RXDET_1
ch3_RXDET_0
ch3_BST_7
ch3_BST_6
ch3_BST_5
ch3_BST_4
0x23 [5]
0x23 [4]
0x23 [3]
0x23 [2]
0x24 [7]
0x24 [6]
0x24 [5]
0x24 [4]
0
0
0
0
0
0
1
0
ch3_BST_3
ch3_BST_2
ch3_BST_1
ch3_BST_0
ch3_Sel_scp
ch3_Sel_mode
ch3_RES_2
ch3_RES_1
0x24 [3]
0x24 [2]
0x24 [1]
0x24 [0]
0x25 [7]
0x25 [6]
0x25 [5]
0x25 [4]
1
1
1
1
1
0
1
0
ch3_RES_0
ch3_VOD_2
ch3_VOD_1
ch3_VOD_0
ch3_DEM_2
ch3_DEM_1
ch3_DEM_0
ch3_Slow
0x25 [3]
0x25 [2]
0x25 [1]
0x25 [0]
0x26 [2]
0x26 [1]
0x26 [0]
0x27 [7]
1
1
0
1
0
1
0
0
ch3_idle_tha_1
ch3_idle_tha_0
ch3_idle_thd_1
ch3_idle_thd_0
ovrd_fast_idle
en_high_idle_th_n
en_high_idle_th_s
en_fast_idle_n
0x27 [3]
0x27 [2]
0x27 [1]
0x27 [0]
0x28 [6]
0x28 [5]
0x28 [4]
0x28 [3]
0
0
0
0
0
0
0
1
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Table 7. EEPROM Register Map - Single Device With Default Value (continued)
EEPROM Address Byte
Description
0x16
SMBus Register
Default Value
80
Description
0x17
SMBus Register
Default Value
5F
Description
0x18
SMBus Register
Default Value
5A
Description
0x19
SMBus Register
Default Value
80
Description
0x1A
SMBus Register
Default Value
05
Description
0x1B
SMBus Register
Default Value
F5
Description
0x1C
SMBus Register
Default Value
A8
Description
0x1D
SMBus Register
Default Value
00
Description
0x1E
SMBus Register
Default Value
5F
Description
0x1F
SMBus Register
Default Value
5A
Description
0x20
SMBus Register
Default Value
20
80
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
en_fast_idle_s
eqsd_mgain_n
eqsd_mgain_s
ch4_Idle_auto
ch4_Idle_sel
ch4_RXDET_1
ch4_RXDET_0
ch4_BST_7
0x28 [2]
0x28 [1]
0x28 [0]
0x2B [5]
0x2B [4]
0x2B [3]
0x2B [2]
0x2C [7]
1
0
0
0
0
0
0
0
ch4_BST_6
ch4_BST_5
ch4_BST_4
ch4_BST_3
ch4_BST_2
ch4_BST_1
ch4_BST_0
ch4_Sel_scp
0x2C [6]
0x2C [5]
0x2C [4]
0x2C [3]
0x2C [2]
0x2C [1]
0x2C [0]
0x2D [7]
0
1
0
1
1
1
1
1
ch4_Sel_mode
ch4_RES_2
ch4_RES_1
ch4_RES_0
ch4_VOD_2
ch4_VOD_1
ch4_VOD_0
ch4_DEM_2
0x2D [6]
0x2D [5]
0x2D [4]
0x2D [3]
0x2D [2]
0x2D [1]
0x2D [0]
0x2E [2]
0
1
0
1
1
0
1
0
ch4_DEM_1
ch4_DEM_0
ch4_Slow
ch4_idle_tha_1
ch4_idle_tha_0
ch4_idle_thd_1
ch4_idle_thd_0
ch5_Idle_auto
0x2E [1]
0x2E [0]
0x2F [7]
0x2F [3]
0x2F [2]
0x2F [1]
0x2F [0]
0x32 [5]
1
0
0
0
0
0
0
0
ch5_Idle_sel
ch5_RXDET_1
ch5_RXDET_0
ch5_BST_7
ch5_BST_6
ch5_BST_5
ch5_BST_4
ch5_BST_3
0x32 [4]
0x32 [3]
0x32 [2]
0x33 [7]
0x33 [6]
0x33 [5]
0x33 [4]
0x33 [3]
0
0
0
0
0
1
0
1
ch5_BST_2
ch5_BST_1
ch5_BST_0
ch5_Sel_scp
ch5_Sel_mode
ch5_RES_2
ch5_RES_1
ch5_RES_0
0x33 [2]
0x33 [1]
0x33 [0]
0x34 [7]
0x34 [6]
0x34 [5]
0x34 [4]
0x34 [3]
1
1
1
1
0
1
0
1
ch5_VOD_2
ch5_VOD_1
ch5_VOD_0
ch5_DEM_2
ch5_DEM_1
ch5_DEM_0
ch5_Slow
ch5_idle_tha_1
0x34 [2]
0x34 [1]
0x34 [0]
0x35 [2]
0x35 [1]
0x35 [0]
0x36 [7]
0x36 [3]
1
0
1
0
1
0
0
0
ch5_idle_tha_0
ch5_idle_thd_1
ch5_idle_thd_0
ch6_Idle_auto
ch6_Idle_sel
ch6_RXDET_1
ch6_RXDET_0
ch6_BST_7
0x36 [2]
0x36 [1]
0x36 [0]
0x39 [5]
0x39 [4]
0x39 [3]
0x39 [2]
0x3A [7]
0
0
0
0
0
0
0
0
ch6_BST_6
ch6_BST_5
ch6_BST_4
ch6_BST_3
ch6_BST_2
ch6_BST_1
ch6_BST_0
ch6_Sel_scp
0x3A [6]
0x3A [5]
0x3A [4]
0x3A [3]
0x3A [2]
0x3A [1]
0x3A [0]
0x3B [7]
0
1
0
1
1
1
1
1
ch6_Sel_mode
ch6_RES_2
ch6_RES_1
ch6_RES_0
ch6_VOD_2
ch6_VOD_1
ch6_VOD_0
ch6_DEM_2
0x3B [6]
0x3B [5]
0x3B [4]
0x3B [3]
0x3B [2]
0x3B [1]
0x3B [0]
0x3C [2]
0
1
0
1
1
0
1
0
ch6_DEM_1
ch6_DEM_0
ch6_Slow
ch6_idle_tha_1
ch6_idle_tha_0
ch6_idle_thd_1
ch6_idle_thd_0
ch7_Idle_auto
0x3C [1]
0x3C [0]
0x3D [7]
0x3D [3]
0x3D [2]
0x3D [1]
0x3D [0]
0x40 [5]
1
0
0
0
0
0
0
0
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SNLS419D – JULY 2012 – REVISED MAY 2015
Table 7. EEPROM Register Map - Single Device With Default Value (continued)
EEPROM Address Byte
Description
0x21
SMBus Register
Default Value
05
Description
0x22
SMBus Register
Default Value
F5
Description
0x23
SMBus Register
Default Value
A8
Description
0x24
SMBus Register
Default Value
00
Description
0x25
SMBus Register
Default Value
00
Description
0x26
SMBus Register
Default Value
54
Description
0x27
SMBus Register
Default Value
54
Bit 4
Bit 3
Bit 2
Bit 1
ch7_Idle_sel
Bit 7
ch7_RXDET_1
Bit 6
ch7_RXDET_0
Bit 5
ch7_BST_7
ch7_BST_6
ch7_BST_5
ch7_BST_4
ch7_BST_3
BIt 0
0x40 [4]
0x40 [3]
0x40 [2]
0x41 [7]
0x41 [6]
0x41 [5]
0x41 [4]
0x41 [3]
0
0
0
0
0
1
0
1
ch7_BST_2
ch7_BST_1
ch7_BST_0
ch7_Sel_scp
ch7_Sel_mode
ch7_RES_2
ch7_RES_1
ch7_RES_0
0x41 [2]
0x41 [1]
0x41 [0]
0x42 [7]
0x42 [6]
0x42 [5]
0x42 [4]
0x42 [3]
1
1
1
1
0
1
0
1
ch7_VOD_2
ch7_VOD_1
ch7_VOD_0
ch7_DEM_2
ch7_DEM_1
ch7_DEM_0
ch7_Slow
ch7_idle_tha_1
0x42 [2]
0x42 [1]
0x42 [0]
0x43 [2]
0x43 [1]
0x43 [0]
0x44 [7]
0x44 [3]
1
0
1
0
1
0
0
0
ch7_idle_tha_0
ch7_idle_thd_1
ch7_idle_thd_0
Reserved
Reserved
Reserved
Reserved
Reserved
0x44 [2]
0x44 [1]
0x44 [0]
0x47 [3]
0x47 [2]
0x47 [2]
0x47 [0]
0x48 [7]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x48 [6]
0x4C [7]
0x4C [6]
0x4C [5]
0x4C [4]
0x4C [3]
0x4C [0]
0x59 [0]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x5A [7]
0x5A [6]
0x5A [5]
0x5A [4]
0x5A [3]
0x5A [2]
0x5A [1]
0x5A [0]
0
1
0
1
0
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x5B [7]
0x5B [6]
0x5B [5]
0x5B [4]
0x5B [3]
0x5B [2]
0x5B [1]
0x5B [0]
0
1
0
1
0
1
0
0
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Table 8. Example of EEPROM for Four Devices Using Two Address Maps
22
EEPROM
Address
Address (Hex)
EEPROM Data
0
00
0x43
1
01
0x00
2
02
0x08
EEPROM Burst Size
3
03
0x00
CRC not used
4
04
0x0B
Device 0 Address Location
5
05
0x00
CRC not used
6
06
0x0B
Device 1 Address Location
7
07
0x00
CRC not used
8
08
0x30
Device 2 Address Location
9
09
0x00
CRC not used
10
0A
0x30
Device 3 Address Location
11
0B
0x00
Begin Device 0, 1 - Address Offset 3
12
0C
0x00
13
0D
0x04
14
0E
0x07
15
0F
0x00
16
10
0x00
EQ CHB0 = 00
17
11
0xAB
VOD CHB0 = 1 V
18
12
0x00
DEM CHB0 = 0 (0 dB)
19
13
0x00
EQ CHB1 = 00
20
14
0x0A
VOD CHB1 = 1 V
21
15
0xB0
DEM CHB1 = 0 (0 dB)
22
16
0x00
23
17
0x00
EQ CHB2 = 00
24
18
0xAB
VOD CHB2 = 1 V
25
19
0x00
DEM CHB2 = 0 (0 dB)
26
1A
0x00
EQ CHB3 = 00
27
1B
0x0A
VOD CHB3 = 1 V
28
1C
0xB0
DEM CHB3 = 0 (0 dB)
29
1D
0x01
30
1E
0x80
31
1F
0x01
EQ CHA0 = 00
32
20
0x56
VOD CHA0 = 1 V
33
21
0x00
DEM CHA0 = 0 (0 dB)
34
22
0x00
EQ CHA1 = 00
35
23
0x15
VOD CHA1 = 1 V
36
24
0x60
DEM CHA1 = 0 (0 dB)
37
25
0x00
38
26
0x01
EQ CHA2 = 00
39
27
0x56
VOD CHA2 = 1 V
40
28
0x00
DEM CHA2 = 0 (0 dB)
41
29
0x00
EQ CHA3 = 00
42
2A
0x15
VOD CHA3 = 1 V
43
2B
0x60
DEM CHA3 = 0 (0 dB)
44
2C
0x00
45
2D
0x00
46
2E
0x54
Comments
CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device Count[3:0] = 3
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Table 8. Example of EEPROM for Four Devices Using Two Address Maps (continued)
EEPROM
Address
Address (Hex)
EEPROM Data
47
2F
0x54
End Device 0, 1 - Address Offset 39
48
30
0x00
Begin Device 2, 3 - Address Offset 3
49
31
0x00
50
32
0x04
51
33
0x07
52
34
0x00
53
35
0x00
EQ CHB0 = 00
54
36
0xAB
VOD CHB0 = 1 V
55
37
0x00
DEM CHB0 = 0 (0 dB)
56
38
0x00
EQ CHB1 = 00
57
39
0x0A
VOD CHB1 = 1 V
58
3A
0xB0
DEM CHB1 = 0 (0 dB)
59
3B
0x00
60
3C
0x00
EQ CHB2 = 00
61
3D
0xAB
VOD CHB2 = 1 V
62
3E
0x00
DEM CHB2 = 0 (0 dB)
63
3F
0x00
EQ CHB3 = 00
64
40
0x0A
VOD CHB3 = 1 V
65
41
0xB0
DEM CHB3 = 0 (0 dB)
66
42
0x01
67
43
0x80
68
44
0x01
EQ CHA0 = 00
69
45
0x56
VOD CHA0 = 1 V
70
46
0x00
DEM CHA0 = 0 (0 dB)
71
47
0x00
EQ CHA1 = 00
72
48
0x15
VOD CHA1 = 1 V
73
49
0x60
DEM CHA1 = 0 (0 dB)
74
4A
0x00
75
4B
0x01
EQ CHA2 = 00
76
4C
0x56
VOD CHA2 = 1 V
77
4D
0x00
DEM CHA2 = 0 (0 dB)
78
4E
0x00
EQ CHA3 = 00
79
4F
0x15
VOD CHA3 = 1 V
80
50
0x60
DEM CHA3 = 0 (0 dB)
81
51
0x00
82
52
0x00
83
53
0x54
84
54
0x54
Comments
End Device 2, 3 - Address Offset 39
Note: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all eight channels
set to EQ = 00 (min boost), VOD = 1 V, DEM = 0 (0 dB) and multiple device can point to the same address map.
Maximum EEPROM size is 8Kb (1024 × 8 bits).
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9.5.3 System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ
to VDD to enable SMBus slave mode and allow access to the configuration registers.
The DS125BR401 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address
inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is 0xB0. Based on the SMBus 2.0 specification, the DS125BR401 has a 7-bit slave address.
The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the
AD[3:0] inputs. Table 9 shows the 16 addresses.
Table 9. Device Slave Address Bytes
AD[3:0] Settings
Address Bytes (HEX)
0000
B0
0001
B2
0010
B4
0011
B6
0100
B8
0101
BA
0110
BC
0111
BE
1000
C0
1001
C2
1010
C4
1011
C6
1100
C8
1101
CA
1110
CC
1111
CE
The SDA, SCL pins are 3.3-V tolerant, but are not 5-V tolerant. External pullup resistor is required on the SDA.
The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also
require an external pullup resistor and it depends on the Host that drives the bus.
9.5.3.1 Transfer of Data Through the SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
9.5.3.2 SMBus Transactions
The device supports WRITE and READ transactions. See Table 10 for register address, type (Read/Write, Read
Only), default value and function information.
9.5.3.3 Writing a Register
To
1.
2.
3.
4.
24
write a register, the following protocol is used (see SMBus 2.0 specification).
The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
The Device (Slave) drives the ACK bit (“0”).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (“0”).
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5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
9.5.3.4 Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
2. The Device (Slave) drives the ACK bit (0).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (0).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a 1 indicating a READ.
7. The Device drives an ACK bit 0.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit 1 indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
See Table 10 for more information.
9.6 Register Maps
Table 10. SMBUS Slave Mode Register Map
Addres Register Name
s
Bit
Field
Type Default
0x00
7
Reserved
R/W
6:3
Address Bit
AD[3:0]
R
Observation of AD[3:0] bits
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
2
EEPROM Read
Done
R
1: Device completed the read from external
EEPROM.
1:0
Reserved
R/W
7:0
PWDN CHx
R/W
0x01
Device Address
Observation
PWDN Channels
EEPROM
Bit
0x00
Description
Set bit to 0.
Set bits to 0.
0x00
Yes
Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
0x00 = all channels enabled
0xFF = all channels disabled
Note: override PWDN pin.
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x02
7:6
Reserved
R/W
5:4
LPBK
Control
3:1
Reserved
0
Override PWDN
pin
Override PWDN,
LPBK Control
EEPROM
Bit
0x00
Description
Set bits to 0.
Yes
00: Use LPBK pin control
01: INA_n to OUTB_n loopback
10: INB_n to OUTA_n loopback
11: Disable loopback and ignore LPBK pin.
Set bits to 0.
Yes
1: Block PWDN pin control
0: Allow PWDN pin control
0x03
Reserved
7:0
Reserved
R/W
0x00
0x04
Reserved
7:0
Reserved
R/W
0x00
0x05
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x05
Reserved
7:0
Reserved
R/W
0x00
Reserved
0x06
Slave Register
Control
7:5
Reserved
R/W
0x10
4
Reserved
3
Register Enable
7
Reserved
6
Reset Registers
Self clearing bit, set to 1 to reset the register to
default values
5
Reset SMBus
Master
Self clearing reset to SMBus master state machine
4:0
Reserved
7
Reserved
6
Override SD_TH
Yes
1: Block SD_TH pin control
0: Allow SD_TH pin control
5
Reserved
Yes
Set bit to 0.
4
Override IDLE
Yes
1: IDLE control by registers
0: IDLE control by signal detect
3
Override
RXDET
Yes
1: Block RXDET pin control
0: Allow RXDET pin control
2
Override MODE
Yes
1: Block MODE pin control
0: Allow MODE pin control
1
Reserved
0x07
0x08
Digital Reset and
Control
Override
Pin Control
Set bits to 0
Yes
Set bits to 0
Set bits to 0.
Yes
Set bit to 1.
1 = Enable SMBus Register Control
0 = Disable SMBus Register Control
Note: In order to change VOD, DEM, and EQ of
the channels in slave mode, this bit must be set
to 1.
R/W
0x01
Set bit to 0.
Set bits to 0 0001'b.
R/W
0x00
Set bit to 0.
Set bit to 0.
0
Reserved
0x09
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x0A
Signal Detect
Monitor
7:0
SD_TH Status
R
0x00
CH7 - CH0 Internal Signal Detector Indicator
[7]: CH7 - CHA_3
[6]: CH6 - CHA_2
[5]: CH5 - CHA_1
[4]: CH4 - CHA_0
[3]: CH3 - CHB_3
[2]: CH2 - CHB_2
[1]: CH1 - CHB_1
[0]: CH0 - CHB_0
0 = Signal detected at input (active data)
1 = Signal not detected at input (idle state)
NOTE: These bits only function when RATE pin =
FLOAT
0x0B
Reserved
7
Reserved
R/W
0x00
Set bits to 0
6:0
Reserved
R/W
0x70
26
Set bit to 0.
Yes
Set bits to 111 0000'b
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x0C
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x0D
CH0 - CHB0
Signal Detect
7:3
Reserved
R/W
0x00
Set bits to 0.
2
SD Reset
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
7:6
Reserved
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
Yes
00: Input is hi-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is hi-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
0x0E
CH0 - CHB0
IDLE, RXDET
EEPROM
Bit
Description
Set bit to 0.
R/W
0x00
Set bits to 0.
1:0
Reserved
0x0F
CH0 - CHB0
EQ
7:0
EQ Control
R/W
0x2F
Yes
Set bits to 0.
IB0 EQ Control - total of 256 levels.
See Table 2.
0x10
CH0 - CHB0
VOD
7
Short Circuit
Protection
R/W
0xAD
Yes
1: Enable the short circuit protection
0: Disable the short circuit protection
6
MODE_SEL
Yes
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
Reserved
Yes
Set bits to default value - 101.
2:0
VOD Control
Yes
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x11
7
RXDET
STATUS
R
6:5
MODE_DET
STATUS
R
4:3
Reserved
R/W
2:0
DEM Control
R/W
7:4
Reserved
R/W
3:2
IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x12
CH0 - CHB0
DEM
CH0 - CHB0
IDLE Threshold
EEPROM
Bit
0x02
Description
Observation bit for RXDET CH0 - CHB0.
1: RX = detected
0: RX = not detected
Observation bit for MODE_DET CH0 - CHB0.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
Set bits to 0.
Yes
0x00
OB0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
Set bits to 0.
0x13
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x14
CH1 - CHB1
Signal Detect
7:3
Reserved
R/W
0x00
Set bits to 0.
2
SD Reset
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
Set bit to 0.
7:6
Reserved
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
Yes
00: Input is hi-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is hi-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
0x15
28
CH1 - CHB1
IDLE, RXDET
R/W
0x00
Set bits to 0.
Set bits to 0.
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
EEPROM
Bit
Description
0x16
CH1 - CHB1
EQ
7:0
EQ Control
R/W
0x2F
Yes
IB1 EQ Control - total of 256 levels.
See Table 2.
0x17
CH1 - CHB1
VOD
7
Short Circuit
Protection
R/W
0xAD
Yes
1: Enable the short circuit protection
0: Disable the short circuit protection
6
MODE_SEL
Yes
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
Reserved
Yes
Set bits to default value - 101.
2:0
VOD Control
Yes
OB1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET
STATUS
R
6:5
MODE_DET
STATUS
R
4:3
Reserved
R/W
2:0
DEM Control
R/W
7:4
Reserved
R/W
3:2
IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x18
0x19
CH1 - CHB1
DEM
CH1 - CHB1
IDLE Threshold
0x02
Observation bit for RXDET CH1 - CHB1.
1: RX = detected
0: RX = not detected
Observation bit for MODE_DET CH1 - CHB1.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
Set bits to 0.
Yes
0x00
OB1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
Set bits to 0.
0x1A
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x1B
CH2 - CHB2
Signal Detect
7:3
Reserved
R/W
0x00
Set bits to 0.
2
SD Reset
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
Set bit to 0.
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x1C
7:6
Reserved
R/W
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
Yes
00: Input is hi-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is hi-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
CH2 - CHB2
IDLE, RXDET
EEPROM
Bit
0x00
Description
Set bits to 0.
1:0
Reserved
0x1D
CH2 - CHB2
EQ
7:0
EQ Control
R/W
0x2F
Yes
IB2 EQ Control - total of 256 levels.
See Table 2.
0x1E
CH2 - CHB2
VOD
7
Short Circuit
Protection
R/W
0xAD
Yes
1: Enable the short circuit protection
0: Disable the short circuit protection
6
MODE_SEL
Yes
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
Reserved
Yes
Set bits to default value - 101.
2:0
VOD Control
Yes
OB2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET
STATUS
R
6:5
MODE_DET
STATUS
R
4:3
Reserved
R/W
2:0
DEM Control
R/W
0x1F
30
CH2 - CHB2
DEM
Set bits to 0.
0x02
Observation bit for RXDET CH2 - CHB2.
1: RX = detected
0: RX = not detected
Observation bit for MODE_DET CH2 - CHB2.
00: PCIe Gen-1 (2.5 G)
01: PCIe Gen-2 (5 G)
11: PCIe Gen-3 (8 G+)
Note: Only functions when MODE Pin = Automatic
Set bits to 0.
Yes
OB2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x20
7:4
Reserved
R/W
3:2
IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
CH2 - CHB2
IDLE Threshold
EEPROM
Bit
0x00
Description
Set bits to 0.
0x21
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x22
CH3 - CHB3
Signal Detect
7:3
Reserved
R/W
0x00
Set bits to 0.
2
SD Reset
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
7:6
Reserved
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
Yes
00: Input is hi-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is hi-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
0x23
CH3 - CHB3
IDLE, RXDET
Set bit to 0.
R/W
0x00
Set bits to 0.
1:0
Reserved
0x24
CH3 - CHB3
EQ
7:0
EQ Control
R/W
0x2F
Yes
Set bits to 0.
IB3 EQ Control - total of 256 levels.
See Table 2.
0x25
CH3 - CHB3
VOD
7
Short Circuit
Protection
R/W
0xAD
Yes
1: Enable the short circuit protection
0: Disable the short circuit protection
6
MODE_SEL
Yes
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
Reserved
Yes
Set bits to default value - 101.
2:0
VOD Control
Yes
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x26
7
RXDET
STATUS
R
6:5
MODE_DET
STATUS
R
4:3
Reserved
R/W
2:0
DEM Control
R/W
7:4
Reserved
R/W
3:2
IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
7:6
Reserved
5:4
High IDLE
Yes
Enable higher range of Signal Detect Thresholds
[5]: CH0 - CH3
[4]: CH4 -CH7
3:2
Fast IDLE
Yes
Enable Fast OOB response
[3]: CH0 - CH3
[2]: CH4 -CH7
1:0
Reduced SD
Gain
Yes
Enable reduced Signal Detect Gain
[1]: CH0 - CH3
[0]: CH4 -CH7
0x27
0x28
CH3 - CHB3
DEM
CH3 - CHB3
IDLE Threshold
Signal Detect
Control
R/W
EEPROM
Bit
0x02
Description
Observation bit for RXDET CH3 - CHB3.
1: RX = detected
0: RX = not detected
Observation bit for MODE_DET CH3 - CHB3.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
Set bits to 0.
Yes
0x00
OB3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
Set bits to 0.
0x0C
Set bits to 0.
0x29
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x2A
CH4 - CHA0
Signal Detect
7:3
Reserved
R/W
0x00
Set bits to 0.
2
SD Reset
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
Set bit to 0.
32
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x2B
7:6
Reserved
R/W
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
Yes
00: Input is hi-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is hi-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
CH4 - CHA0
IDLE, RXDET
EEPROM
Bit
0x00
Description
Set bits to 0.
1:0
Reserved
0x2C
CH4 - CHA0
EQ
7:0
EQ Control
R/W
0x2F
Yes
IA0 EQ Control - total of 256 levels.
See Table 2.
0x2D
CH4 - CHA0
VOD
7
Short Circuit
Protection
R/W
0xAD
Yes
1: Enable the short circuit protection
0: Disable the short circuit protection
6
MODE_SEL
Yes
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
Reserved
Yes
Set bits to default value - 101.
2:0
VOD Control
Yes
OA0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET
STATUS
R
6:5
MODE_DET
STATUS
R
4:3
Reserved
R/W
2:0
DEM Control
R/W
0x2E
CH4 - CHA0
DEM
Set bits to 0.
0x02
Observation bit for RXDET CH4 - CHA0.
1: RX = detected
0: RX = not detected
Observation bit for MODE_DET CH4 - CHA0.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
Set bits to 0.
Yes
OA0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x2F
7:4
Reserved
R/W
3:2
IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
CH4 - CHA0
IDLE Threshold
EEPROM
Bit
0x00
Description
Set bits to 0.
0x30
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x31
CH5 - CHA1
Signal Detect
7:3
Reserved
R/W
0x00
Set bits to 0.
2
SD Reset
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
7:6
Reserved
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
Yes
00: Input is hi-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is hi-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
0x32
CH5 - CHA1
IDLE, RXDET
Set bit to 0.
R/W
0x00
Set bits to 0.
1:0
Reserved
0x33
CH5 - CHA1
EQ
7:0
EQ Control
R/W
0x2F
Yes
IA1 EQ Control - total of 256 levels.
See Table 2.
0x34
CH5 - CHA1
VOD
7
Short Circuit
Protection
R/W
0xAD
Yes
1: Enable the short circuit protection
0: Disable the short circuit protection
6
MODE_SEL
Yes
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
Reserved
Yes
Set bits to default value - 101.
2:0
VOD Control
Yes
OA1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
34
Set bits to 0.
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x35
7
RXDET
STATUS
R
6:5
MODE_DET
STATUS
R
4:3
Reserved
R/W
2:0
DEM Control
R/W
7:4
Reserved
R/W
3:2
IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x36
CH5 - CHA1
DEM
CH5 - CHA1
IDLE Threshold
EEPROM
Bit
0x02
Description
Observation bit for RXDET CH5 - CHA1.
1: RX = detected
0: RX = not detected
Observation bit for MODE_DET CH5 - CHA1.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
Set bits to 0.
Yes
0x00
OA1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
Set bits to 0.
0x37
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x38
CH6 - CHA2
Signal Detect
7:3
Reserved
R/W
0x00
Set bits to 0.
2
SD Reset
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
Set bit to 0.
7:6
Reserved
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
Yes
00: Input is hi-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is hi-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
0x39
CH6 - CHA2
IDLE, RXDET
R/W
0x00
Set bits to 0.
Set bits to 0.
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
EEPROM
Bit
Description
0x3A
CH6 - CHA2
EQ
7:0
EQ Control
R/W
0x2F
Yes
IA2 EQ Control - total of 256 levels.
See Table 2.
0x3B
CH6 - CHA2
VOD
7
Short Circuit
Protection
R/W
0xAD
Yes
1: Enable the short circuit protection
0: Disable the short circuit protection
6
MODE_SEL
Yes
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
Reserved
Yes
Set bits to default value - 101.
2:0
VOD Control
Yes
OA2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET
STATUS
R
6:5
MODE_DET
STATUS
R
4:3
Reserved
R/W
2:0
DEM Control
R/W
7:4
Reserved
R/W
3:2
IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x3C
0x3D
CH6 - CHA2
DEM
CH6 - CHA2
IDLE Threshold
0x02
Observation bit for RXDET CH6 - CHA2.
1: RX = detected
0: RX = not detected
Observation bit for MODE_DET CH6 - CHA2.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
Set bits to 0.
Yes
0x00
OA2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
Set bits to 0.
0x3E
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x3F
CH7 - CHA3
Signal Detect
7:3
Reserved
R/W
0x00
Set bits to 0.
2
SD Reset
1: Force signal detect "off"
0: Normal operation
1
SD Preset
1: Force signal detect "on"
0: Normal operation
0
Reserved
Set bit to 0.
36
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x40
7:6
Reserved
R/W
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
Yes
00: Input is hi-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is hi-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
CH7 - CHA3
IDLE, RXDET
EEPROM
Bit
0x00
Description
Set bits to 0.
1:0
Reserved
0x41
CH7 - CHA3
EQ
7:0
EQ Control
R/W
0x2F
Yes
IA3 EQ Control - total of 256 levels.
See Table 2.
0x42
CH7 - CHA3
VOD
7
Short Circuit
Protection
R/W
0xAD
Yes
1: Enable the short circuit protection
0: Disable the short circuit protection
6
MODE_SEL
Yes
1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3
Reserved
Yes
Set bits to default value - 101.
2:0
VOD Control
Yes
OA3 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET
STATUS
R
6:5
MODE_DET
STATUS
R
4:3
Reserved
R/W
2:0
DEM Control
R/W
0x43
CH7 - CHA3
DEM
Set bits to 0.
0x02
Observation bit for RXDET CH7 - CHA3.
1: RX = detected
0: RX = not detected
Observation bit for MODE_DET CH7 - CHA3.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
Set bits to 0.
Yes
OA3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
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Register Maps (continued)
Table 10. SMBUS Slave Mode Register Map (continued)
Addres Register Name
s
Bit
Field
Type Default
0x44
7:4
Reserved
R/W
3:2
IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0
IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
CH7 - CHA3
IDLE Threshold
EEPROM
Bit
0x00
Description
Set bits to 0.
0x45
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x46
Reserved
7:0
Reserved
R/W
0x38
Set bits to 0x38
0x47
Reserved
7:4
Reserved
R/W
0x00
Set bits to 0
3:0
Reserved
R/W
0x48
Reserved
7:6
Reserved
R/W
5:0
Reserved
R/W
0x05
Yes
Set bits to 0
Yes
Set bits to 0
Set bits to 00 0101'b
0x49
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x4A
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x4B
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x4C
Reserved
7:3
Reserved
R/W
0x00
2:1
Reserved
R/W
0
Reserved
R/W
Yes
Set bits to 0
Set bits to 0
Yes
Set bits to 0
0x4D
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x4E
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x4F
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x50
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x51
Device ID
7:5
VERSION
R
0x44
010'b
4:0
ID
00100'b
0x52
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x53
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x54
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x55
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x56
Reserved
7:0
Reserved
R/W
0x10
Set bits to 0x10
0x57
Reserved
7:0
Reserved
R/W
0x64
Set bits to 0x64
0x58
Reserved
7:0
Reserved
R/W
0x21
Set bits to 0x21
0x59
Reserved
7:1
Reserved
R/W
0x00
Set bits to 0
0
Reserved
Yes
Set bit to 0
0x5A
Reserved
7:0
Reserved
R/W
0x54
Yes
Set bits to 0x54
0x5B
Reserved
7:0
Reserved
R/W
0x54
Yes
Set bits to 0x54
0x5C
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x5D
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x5E
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x5F
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x60
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
0x61
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0
38
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The DS125BR401 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the following information and Revision 4 of the LVDS Owner's Manual for more detailed information on highspeed design tips to address signal integrity design issues.
10.2 Typical Application
The DS125BR401 works to extend the reach possible by using active equalization on the channel, boosting
attenuated signals so that they can be more easily recovered at the Rx endpoint. The capability of the repeater
can be explored across a range of data rates and ASIC-to-link-partner signaling, as shown in the following test
setup connections. The test setup connections diagrams shown represent typical generic application scenarios
for the DS125BR401.
Pattern
Generator
TL
Lossy Channel
VID = 1.0 Vp-p,
DE = 0 dB
PRBS15
IN
DS125BR401
Scope
BW = 60 GHz
OUT
Figure 9. Test Setup Connections Diagram
Pattern
Generator
VID = 1.0 Vp-p,
DE = -6 dB
PRBS15
TL1
Lossy Channel
IN
DS125BR401
OUT
TL2
Lossy Channel
Scope
BW = 60 GHz
Figure 10. Test Setup Connections Diagram
10.2.1 Design Requirements
As with any high speed design, there are many factors which influence the overall performance. Below are a list
of critical areas for consideration and study during design.
• Use 100-Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use Reference plane vias to ensure a low inductance path for the return current.
10.2.2 Detailed Design Procedure
The DS125BR401 is designed to be placed at a location where the input CTLE can help to compensate for a
portion of the overall channel attenuation. In order to optimize performance, the repeater requires tuning to
extend the reach of the cable or trace length while also recovering a solid eye opening. To tune the repeater, TI
recommends the settings mentioned in Table 2 and Table 3 (for Pin Mode) as a default starting point for most
applications. Once these settings are configured, additional tuning of the EQ and, to a lesser extent, VOD may
be required to optimize the repeater performance for each specific application environment. Examples of the
repeater performance as a generic high-speed datapath repeater are illustrated in the performance curves in the
next section.
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Typical Application (continued)
10.2.3 Application Curves
DS125BR401 settings: EQ[1:0] = 0, F = 0x02, DEM[1:0] = 0, 1
Figure 11. TL = 10-Inch 5-Mil FR4 Trace, 5 Gbps
DS125BR401 settings: EQ[1:0] = 0, F = 0x02, DEM[1:0] = 0, 1
Figure 12. TL = 10-Inch 5-Mil FR4 Trace, 8 Gbps
DS125BR401 settings: EQ[1:0] = 0, R = 0x01, DEM[1:0] = 0, 1
Figure 13. TL = 10-Inch 5-Mil FR4 Trace, 12 Gbps
DS125BR401 settings: EQ[1:0] = 0, 1 = 0x03, DEM[1:0] = 0, 1
Figure 14. TL = 20-Inch 5-Mil FR4 Trace, 5 Gbps
DS125BR401 settings: EQ[1:0] = 0, 1 = 0x03, DEM[1:0] = 0, 1
Figure 15. TL = 20-Inch 5-Mil FR4 Trace, 8 Gbps
DS125BR401 settings: EQ[1:0] = 0, 1 = 0x03, DEM[1:0] = 0, 1
Figure 16. TL = 20-Inch 5-Mil FR4 Trace, 12 Gbps
40
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Typical Application (continued)
DS125BR401 settings: EQ[1:0] = R, 0 = 0x07, DEM[1:0] = 0, 1
Figure 17. TL = 30-Inch 5-Mil FR4 Trace, 5 Gbps
DS125BR401 settings: EQ[1:0] = R, 0 = 0x07, DEM[1:0] = 0, 1
Figure 18. TL = 30-Inch 5-Mil FR4 Trace, 8 Gbps
DS125BR401 settings: EQ[1:0] = R, 0 = 0x07, DEM[1:0] = 0, 1
Figure 19. TL = 30-Inch 5-Mil FR4 Trace, 12 Gbps
DS125BR401 settings: EQ[1:0] = R, 0 = 0x07, DEM[1:0] = 0, 1
Figure 20. TL1 = 5-Meter 30-AWG 100-Ω Twin-Axial Cable,
12 Gbps
DS125BR401 settings: EQ[1:0] = R, 1 = 0x0F, DEM[1:0] = 0, 1
Figure 21. TL1 = 8-Meter 30-AWG 100-Ω Twin-Axial Cable,
12 Gbps
DS125BR401 settings: EQ[1:0] = 0, 1 = 0x03, DEM[1:0] = R, 0
Figure 22. TL1 = 20-Inch 5-Mil FR4 Trace,
TL2 = 10-Inch 5-Mil FR4 Trace, 5 Gbps
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Typical Application (continued)
DS125BR401 settings: EQ[1:0] = R, 1 = 0x0F, DEM[1:0] = R, 0
Figure 23. TL1 = 20-Inch 5-Mil FR4 Trace,
TL2 = 10-Inch 5-Mil FR4 Trace, 8 Gbps
42
DS125BR401 settings: EQ[1:0] = R, 1 = 0x0F, DEM[1:0] = R, 0
Figure 24. TL1 = 20-Inch 5-Mil FR4 Trace, TL2 = 10-Inch 5Mil FR4 Trace, 12 Gbps
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11 Power Supply Recommendations
11.1 3.3-V or 2.5-V Supply Mode Operation
The DS125BR401 has an optional internal voltage regulator to provide the 2.5-V supply to the device. In 3.3-V
mode operation, the VIN pin = 3.3 V is used to supply power to the device. The internal regulator will provide the
2.5 V to the VDD pins of the device and a 0.1 µF capacitor is needed at each of the 5 VDD pins for power supply
decoupling (total capacitance should be ≤ 0.5 µF), and the VDD pins should be left open. The VDD_SEL pin
must be tied to GND to enable the internal regulator. In 2.5-V mode operation, the VIN pin should be left open
and the 2.5-V supply must be applied to the 5 VDD pins to power the device. The VDD_SEL pin must be left
open (no connect) to disable the internal regulator.
3.3 V mode
2.5 V mode
VDD_SEL
Enable
VDD_SEL
open
VIN
open
Disable
3.3 V
1 µF
VIN
10 µF
Internal
voltage
regulator
2.5 V
VDD
VDD
0.1 µF
0.1 µF
VDD
VDD
0.1 µF
0.1 µF
1 µF
2.5 V
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
10 µF
Internal
voltage
regulator
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
VDD
VDD
0.1 µF
0.1 µF
VDD
VDD
0.1 µF
0.1 µF
VDD
VDD
0.1 µF
0.1 µF
Place 0.1 µF close to VDD Pin
Total capacitance should be 7 0.5 µF
Place capacitors close to VDD Pin
Figure 25. 3.3-V or 2.5-V Supply Connection Diagram
11.2 Power Supply Bypassing
TI recommends two routing options to ensure that the DS125BR401 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1-μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS125BR401. Smaller
body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in
the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These
capacitors can be either tantalum or an ultra-low ESR ceramic.
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Product Folder Links: DS125BR401
43
DS125BR401
SNLS419D – JULY 2012 – REVISED MAY 2015
www.ti.com
12 Layout
12.1 Layout Guidelines
12.1.1 PCB Layout Considerations for Differential Pairs
The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 Ω to 100 Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN1187 Leadless Leadframe Package (LLP) Application Report (SNOA401) for additional information on QFN
(WQFN) packages.
Figure 26 depicts different transmission line topologies which can be used in various combinations to achieve the
optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by
increasing the swell around each hole and providing for a low inductance return current path. When the via
structure is associated with thick backplane PCB, further optimization such as back drilling is often used to
reduce the detrimental high frequency effects of stubs on the signal path.
12.2 Layout Example
20 mils
EXTERNAL MICROSTRIP
100 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
19
54
20
53
52
21
51
22
23
VDD
BOTTOM OF PKG
50
GND
24
49
25
48
47
26
46
27
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD
VDD
Figure 26. Typical Routing Options
44
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Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS125BR401
DS125BR401
www.ti.com
SNLS419D – JULY 2012 – REVISED MAY 2015
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
•
•
Leadless Leadframe Package (LLP) Application Report (SNOA401)
Absolute Maximum Ratings for Soldering (SNOA549)
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: DS125BR401
45
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS125BR401SQ/NOPB
ACTIVE
WQFN
NJY
54
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
DS125BR401SQ
DS125BR401SQE/NOPB
ACTIVE
WQFN
NJY
54
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
DS125BR401SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS125BR401SQ/NOPB
WQFN
NJY
54
2000
330.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
DS125BR401SQE/NOPB
WQFN
NJY
54
250
178.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS125BR401SQ/NOPB
WQFN
NJY
54
2000
367.0
367.0
38.0
DS125BR401SQE/NOPB
WQFN
NJY
54
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJY0054A
WQFN
SCALE 2.000
WQFN
5.6
5.4
B
A
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
10.1
9.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
2X 4
SEE TERMINAL
DETAIL
3.51±0.1
19
(0.1)
27
28
18
50X 0.5
7.5±0.1
2X
8.5
1
45
54
PIN 1 ID
(OPTIONAL)
46
54X
54X
0.5
0.3
0.3
0.2
0.1
0.05
C A
C
B
4214993/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NJY0054A
WQFN
WQFN
(3.51)
SYMM
54X (0.6)
54
54X (0.25)
SEE DETAILS
46
1
45
50X (0.5)
(7.5)
SYMM
(9.8)
(1.17)
TYP
2X
(1.16)
28
18
( 0.2) TYP
VIA
19
27
(1) TYP
(5.3)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214993/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
NJY0054A
WQFN
WQFN
SYMM
METAL
TYP
(0.855) TYP
46
54
54X (0.6)
54X (0.25)
1
45
50X (0.5)
(1.17)
TYP
SYMM
(9.8)
12X (0.97)
18
28
19
27
12X (1.51)
(5.3)
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
4214993/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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