Texas Instruments | TPIC8101 Knock Sensor Interface (Rev. C) | Datasheet | Texas Instruments TPIC8101 Knock Sensor Interface (Rev. C) Datasheet

Texas Instruments TPIC8101 Knock Sensor Interface (Rev. C) Datasheet
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TPIC8101
SLIS110C – APRIL 2003 – REVISED MARCH 2015
TPIC8101 Knock Sensor Interface
1 Features
3 Description
•
•
The TPIC8101 is a dual-channel signal processing IC
for detection of premature detonation in combustion
engine. The two sensor channels are selectable
through the SPI bus. The knock sensor typically
provides an electrical signal to the amplifier inputs.
The sensed signal is processed through a
programmable band-pass filter to extract the
frequency of interest (engine knock or ping signals).
The band-pass filter eliminates any engine
background noise associated with combustion. The
engine background noise is typically low in amplitude
compared to the predetonation noise.
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM Classification Level 3A
– Device CDM Classification Level C6
Dual-Channel Knock Sensor Interface
Programmable Input Frequency Prescaler
(OSCIN)
Serial Interface With Microprocessor (SPI)
Programmable Gain
Programmable Band-Pass Filter Center
Frequency
External Clock Frequencies up to 24 MHz
– 4, 5, 6, 8, 10, 12, 16, 20, and 24 MHz
Programmable Integrator Time Constants
Operating Temperature Range −40°C to 125°C
The detected signal is full-wave rectified and
integrated by use of the INT/HOLD signal. The digital
output from the integration stage is either converted
to an analog signal, passed through an output buffer,
or be read directly by the SPI.
This analog buffered output may be interfaced to an
A/D converter and read by the microprocessor. The
digital output may be directly interfaced to the
microprocessor.
2 Applications
•
•
Device Information(1)
Engine Knock Detector Signal Processing
Analog Signal Processing With Filter
Characteristics
PART NUMBER
TPIC8101
PACKAGE
SOIC (20)
BODY SIZE (NOM)
7.50 mm × 12.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Vref
VDD / 2
+
−
+
−
CH1P
CH1N
CH1FB
CH2P
CH2N
CH2FB
Mux
SAR
10-Bit ADC <1:10>
rd
3 Order AAF
+
−
Programmable
Band-Pass
Filter
Programmable
Gain
fS = 200 kHz
Rectifier
Programmable
Integrator
DSP
XOUT
XIN
INT/HOLD
TEST
CS
SDI
SDO
SCLK
SPI
Test Mode
DSP Control
+
−
OUT
GND
VDD
R2R
10-Bit DAC
fS = 200 kHz
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC8101
SLIS110C – APRIL 2003 – REVISED MARCH 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2
8.3
8.4
8.5
9
Functional Block Diagram ......................................... 9
Feature Description................................................... 9
Device Functional Modes........................................ 12
Programming........................................................... 14
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1 Trademarks ........................................................... 20
12.2 Electrostatic Discharge Caution ............................ 20
12.3 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2014) to Revision C
Page
•
Added qualification for automotive applications to Features ................................................................................................. 1
•
Added the ESD Ratings table with HBM and CDM ratings ................................................................................................... 4
Changes from Revision A (May 2005) to Revision B
•
2
Page
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
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5 Description (continued)
The data from the A/D enables the system to analyze the amount of retard timing for the next spark ignition
timing cycle. With the microprocessor closed-loop system, advancing and retarding the spark timing optimizes
the load/RPM conditions for a particular engine (data stored in RAM).
6 Pin Configuration and Functions
SOIC Package
(Top View)
VDD
1
20
CH1P
GND
2
19
CH1N
Vref
3
18
CH1FB
OUT
4
17
CH2FB
NC
5
16
CH2N
NC
6
15
CH2P
INT/HOLD
7
14
CS
8
13
TEST
SCLK
XIN
9
12
SDI
10
11
SDO
XOUT
Pin Functions
PIN
NO.
TYPE
(PULLUP/PULLDOWN)
VDD
1
I
5-V input supply
GND
2
I
Ground connection
Vref
3
O
Supply reference generator with external bypass capacitor
OUT
4
O
Buffered integrator output
—
No connection
NAME
NC (1)
5
6
DESCRIPTION
INT/HOLD
7
I (pulldown)
CS
8
I (pullup)
XIN
9
I
Inverter input for oscillator
XOUT
10
O
Inverter output for oscillator
SDO
11
O
Serial data output for SPI bus
SDI
12
I (pullup)
Serial data input line
SCLK
13
I (pullup)
SPI clock
TEST
14
I (pullup)
Test mode (active low), open for normal operation
CH2P
15
I
Positive input for amplifier 2
CH2N
16
I
Negative input for amplifier 2
CH2FB
17
O
Output of amplifier 2, for feedback connection
CH1FB
18
O
Output of amplifier 1, for feedback connection
CH1N
19
I
Negative input for amplifier 1
CH1P
20
I
Positive input for amplifier 1
(1)
Selectable for integrate (high) or hold (low) mode (with internal pulldown)
Chip select for SPI communications (active low with internal pullup)
These terminals are to be used for test purposes only and are not connected in the system application. No signal traces should be
connected to the NC terminals.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VDD
Regulated input voltage
(1)
(2) (3)
(2) (3)
MIN
MAX
UNIT
−0.3
7
V
−0.3
7
V
−0.3
7
V
2
mA
VO
Output voltage
VIN
Input voltage (2) (3)
IIN
DC input current on terminals CH1P, CH1N, CH2P, and CH2N (2) (3)
VDCIN
DC input voltage on terminals CH1P, CH1N, CH2P and CH2N (2) (3)
14
V
RθJA
Junction-to-ambient thermal impedance
120
°C/W
PD
Continuous power dissipation
200
mW
TA
Operating ambient temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Absolute negative voltage on these terminals is not to go < –0.5 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM) (1)
4000
Charged-device model (CDM)
1500
UNIT
V
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each terminal.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD
Regulated input voltage
−0.3
5.5
V
VO
Output voltage
−0.3
5.5
V
VIN
Input voltage
0.05
VDD − 0.05
V
IIN
DC input current on terminals CH1P, CH1N, CH2P, and CH2N
1
µA
VDCIN
DC input voltage on terminals CH1P, CH1N, CH2P, and CH2N
PD
Continuous power dissipation
–1
Vref, (VDD / 2)
100
V
mW
7.4 Thermal Information
TPIC8101
THERMAL METRIC
(1)
DW [SOIC]
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
66.2
RθJC(top)
Junction-to-case (top) thermal resistance
29.6
RθJB
Junction-to-board thermal resistance
34.4
ψJT
Junction-to-top characterization parameter
7.1
ψJB
Junction-to-board characterization parameter
33.8
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
VDD = 5 V ±5%, input frequency before prescaler = 4 to 20 MHz (±0.5%), TA = −40°C to 125°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
IDD(Q)
Quiescent current
VDD = 5 V
IDD(OP)
Operating current
VDD = 5 V, XIN = 8 MHz
Vmid0
Midpoint voltage
VDD = 5 V, ISource = 2 mA
2.3
2.5
2.55
V
Vmid1
Midpoint voltage
VDD = 5 V, ISink = 2 mA
2.4
2.5
2.7
V
Vmid2
Midpoint voltage
VDD = 5 V, IL = 0 mA
2.4
2.5
2.6
V
Rpull0
Internal pullup resistor CS, SDI, SCLK,
VIN = GND
TEST
30
kΩ
Rpull1
Internal pulldown resistor INT/HOLD
VIN = VDD
20
kΩ
Ilkg
Input leakage current CS, SDI, SCLK,
INT/HOLD, TEST
Measured at GND and VDD,
VDD = 5.5 V = VIN
VIL
Low-level input voltage INT/HOLD, CS,
TEST, SDI, SCLK
VIH
High-level input voltage INT/HOLD,
CS, TEST, SDI, SCLK
VOL
Low-level output voltage SDO
ISink = 4 mA, VDD = 5V
VOH
High-level output voltage SDO
ISource = 100 µA, VDD = 5 V
Low-level leakage current SDO
Measured at GND and VDD = 5 V,
SDO in high impedance
Ilkg(OL)
VOL(XOUT) Low-level output voltage
VOH(XOUT
High-level output voltage
)
Vhyst
7.5
UNIT
mA
20
±3
mA
µA
30% of
VDD
70% of
VDD
0.7
4.4
V
−10
ISink = 500 µA, VDD = 4.5 V
ISource = 500 µA, VDD = 5 V
Hysteresis voltage INT/HOLD, CS,
XIN, SDI, SCLK, TEST
V
10
µA
1.5
V
4.4
V
0.4
V
INPUT AMPLIFIERS
VOH (1)
CH1FB and CH2FB high-level output
voltage
VDD = 5 V, ISource = 100 µA
VOL (1)
CH1FB and CH2FB low-level output
voltage
ISink = 100 µA
CATTEN
Cross-coupling attenuation CH1FB and ƒin max(ch1) = 20 kHz, measured on
CH2FB
channel 2
40
Av
Open-loop gain
60
100
GBW
Gain bandwidth product
1
2.6
VIN
Input voltage range
0.05
VDD – 0.05
V(offset)
Offset voltage at input
−10
10
CMRR
Common-mode rejection ratio
Inputs at Vmid ƒin = 0 to 20 kHz
60
PM
Phase margin
Gain = 1, CL = 200 pF, RL = 100 kΩ
45
°
150
mV
VDD = 5 V, ISource = 2 mA
VDD – 0.05 VDD – 0.02
15
ISink = 2 mA
Input range 0.5 to 4.5 V
V
VDD – 0.5
50
500
mV
dB
dB
MHz
80
V
mV
dB
PRESCALER, XIN
VOSC
Minimum input peak amplitude (1)
VDD = Vmin, oscillator inverter biased
feedback resistor 1 MΩ, ƒosc = 24 MHz
CIN
Input capacitance
Assured by design
Ilkg(XIN)
Leakage current
−1
7
pF
1
µA
MULTIPLEXER
CATTEN
(1)
Cross-coupling attenuation (assured by ƒin max(ch1) = 20 kHz, measured on
design)
channel 2
40
dB
150-mV input amplitude on the 4-MHz clock input only applies if the feedback network is completed. Without the feedback network, the
4-MHz signal should be at 0- to 5-V levels.
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Electrical Characteristics (continued)
VDD = 5 V ±5%, input frequency before prescaler = 4 to 20 MHz (±0.5%), TA = −40°C to 125°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANTI-ALIASING FILTER
ƒc (2)
Cut-off frequency at –3 dB
35
45
55
kHz
BW
Response 1 to 20 kHz referenced to 1
kHz
70-mV RMS, input: CH1FB or CH2FB,
output: OUT
−1
−0.5
1
dB
ATTEN
Attenuation at 100 kHz referenced to 1
kHz
70-mV RMS, input: CH1FB or CH2FB,
output: OUT
−10
−15
For all frequencies stated
198
200
dB
ANALOG-TO-DIGITAL CONVERTER
ƒs
Sampling frequency
AR
Analog resolution
202
ADNL
Differential linearity error (DNL)
1
bit
AINL
Linearity error (INL)
1
bit
10
kHz
bit
DIGITAL-TO-ANALOG CONVERTER
ƒs(DA)
Sampling frequency
DR
Resolution at 200 kHz
198
200
202
DDNL
Differential linearity error (DNL)
(Vreset < DACout < 0.98 VDD)
−1
1
LSB
DINL
Linearity error (INL)
(Vreset < DACout < 0.98 VDD)
−2.5
2.5
LSB
DRNIL
Repeatability (for characterization
purposes only)
−1
1
LSB
175
mV
10
kHz
bit
OUTPUT BUFFER
VOH
High-level output voltage
VDD = 5 V, ISource = 2 mA
VOL
Low-level output voltage
VDD = 5 V, ISink = 2 mA
Av
Open-loop gain
IO = ±2 mA
G
Output gain
IO = ±2 mA
Vripple
Ripple voltage
CL = 0 to 22 nF, max slew rate,
12 mV/µs from Vreset to 4 V
10
mV
ts
Settling time
CL = 0 to 22 nF, max slew rate,
12 mV/µs from Vreset to 4 V, output:
±0.5 LSB
20
µs
(2)
6
VDD – 0.2 VDD – 0.15
120
60
V
100
dB
1
ƒc is programmable (see Table 3).
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7.6 Timing Requirements
VDD = 5 V ±5%, TA = −40°C to 125°C (unless otherwise specified)
MIN
NOM
MAX
UNIT
5
MHz
ƒSPI
SPI frequency
t1
Time from CS falling edge to SCLK rising edge
10
ns
t2
Time from CS falling edge to SCLK falling edge
80
ns
t3
Time for SCLK to go high
60
ns
t4
Time for SCLK to go low
60
ns
t5
Time from last SCLK falling edge to CS rising edge
80
ns
t6
Time from SDI valid to falling edge of SCLK
60
ns
t7
Time for SDI valid after falling edge of SCLK
10
ns
t8
Time after CS rises until INT/HOLD to go high
8
ns
t9
Time between two words for transmitting
170
ns
t10
Time for SDO valid after SDI on bus, at VDD = 5 V and load = 20 pF
40
t2
ns
t9
t8
t3
t1
t5
t1
t4
CS
SCLK
SDI
XXX MSB
6
5
4
3
5
4
3
2
1
LSB
1
LSB
t7
t6
INT/HOLD
SDO
XXX
MSB
6
2
t10
Figure 1. Serial Peripheral Interface (SPI)
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7.7 Typical Characteristics
Input Signal
Input Signal
Int/Hold Signal
Int/Hold Signal
Output Signal
Output Signal
Figure 2. Amplified Input Signal Process
8
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Figure 3. Input Signal Processing
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8 Detailed Description
8.1 Overview
The TPIC8101 is designed for knock sensor signal conditioning in automotive applications. The device is an
analog interface between the engine acoustical sensors or accelerometers and the fuel management systems of
a gasoline engine. The two wide-band amplifiers process signals from the piezoelectric sensors. Outputs of the
amplifiers feed a channel select MUX switch and then a third-order antialiasing filter. This signal is converted
using an analog-to-digital conversion (10 bits with a sampling frequency of 200 kHz) prior to the gain stage.
8.2 Functional Block Diagram
Vref
VDD/2
+
−
CH1P
+
CH1N
−
Mux
CH1FB
SAR
<1:10>
10-Bit ADC
fs = 200 kHz
3rd Order AAF
CH2P
+
CH2N
−
CH2FB
Programmable
Band-Pass
Filter
Programmable
Gain
Programmable
Integrator
Rectifier
DSP
R2R
10-Bit DAC
fs = 200 kHz
SPI
Test Mode
DSP Control
+
−
VDD
GND
OUT
SDO SDI
SCLK
CS
TEST
INT/HOLD XIN
XOUT
8.3 Feature Description
The gain stage is adjustable through the SPI to compensate for the knock energies. The gain setting is
selectable up to 64 values ranging from 0.111 to 2.0.
The output of the gain stage feeds a band-pass filter circuit to process the particular frequency component
associated with the engine and transducer.
The band-pass filter has a gain of two and a center frequency range between 1.22 and 19.98 kHz (64-bit
selection). The output from this stage is internally clamped.
The output from the band-pass filter is full-wave rectified with its output clamped below VDD.
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Feature Description (continued)
The full-wave rectified signals are integrated using an integrator time constant set by the SPI and integration time
window set by the pulse duration of INT/HOLD. At the start of each knock window, the integrator output is reset.
The output of the integrator is internally clamped and the digital output may be directly interfaced to the
microprocessor.
The integrated signal is converted to an analog format by a 10-bit DAC. The microprocessor may interface to this
signal, read this data, and adjust the spark ignition timing to optimize fuel efficiency related to load versus engine
RPM.
8.3.1 Functional Terminal Description
8.3.1.1 Supply Voltage (VDD)
The VDD terminal is the input supply for the IC, typically 5-V ±5% tolerant. A noise filter capacitor of 4.7 µF
(typical) is required on this terminal to ensure stability of the internal circuits.
8.3.1.2 Ground (GND)
The GND terminal is connected to the system ground rail.
8.3.1.3 Reference Supply (Vref)
The Vref is an internally generated supply reference voltage for biasing the amplifier inputs. The terminal is used
to decouple any noise in the system by placing an external capacitor of 22 nF (typical).
8.3.1.4 Buffered Integrator Output (OUT)
The OUT terminal is the output of the integrated signal. This is an analog signal interfaced to the microprocessor
A/D channel for data acquisition. A capacitor of 2.2 nF is used to stabilize the signal output.
8.3.1.5 Integration/Hold Mode Selection (INT/HOLD)
The INT/HOLD is an input control signal from the microprocessor to select either to integrate the sensed signal
or to hold the data for acquisition. There is an internal pulldown on this terminal (default HOLD mode).
8.3.1.6 Chip Select for SPI (CS)
The CS terminal allows serial communication to the IC through the SPI from a master controller. The chip select
is active low with an internal pullup (default inactive).
8.3.1.7 Oscillator Input (XIN)
The XIN terminal is the input to the inverter used for the oscillator circuit. An external clock signal from the MCU,
crystal, or ceramic resonator is configured with resistors and capacitors. To bias the inverter, place a resistor (1
MΩ typical) across XIN and XOUT.
This clock signal is prescaled to set the internal sampling frequency of the A/D converter.
8.3.1.8 Oscillator Output (XOUT)
The XOUT terminal is the output of the inverter used for the oscillator circuit.
8.3.1.9 Data Output (SDO)
The SDO output is the SPI data bus reporting information back to the microprocessor. This is a tri-state output
with the output set to high-impedance mode when CS is pulled to VDD. The high-impedance state can also be
programmed by setting a bit in the prescale word, which takes precedence over the CS setting. The output is
disabled when the CS terminal is pulled high (VDD).
8.3.1.10 Data Input (SDI)
The SDI terminal is the communication interface for data transfer between the master and slave components.
The SDI has an internal pullup to VDD; the data stream is in 8-bit word format.
10
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Feature Description (continued)
8.3.1.11 Serial Clock (SCLK)
The SCLK output signal is used for synchronous communication of data. Typically, the output from the master
clock is low with the IC having an internal pullup resistor to VDD. The data is clocked to the internal shift register
on the falling clock edge.
8.3.1.12 Test (TEST)
The TEST terminal, when pulled low, allows the IC to enter the test mode. During normal operation, this terminal
is left open or tied high (VDD). There is an internal pullup to VDD (default).
8.3.1.13 Feedback Output for Amplifiers (CH1FB and CH2FB)
The CHXFB are amplifier outputs for the sensor signals. The gain of the respective amplifiers is set using the
CHXFB and CHX input terminals (see Figure 1).
8.3.1.14 Input Amplifiers (CH1P, CH1N, CH2P, and CH2N)
CH1P, CH1N, CH2P, and CH2N are the inputs for the two amplifiers which interface to the external knock
sensors.
The gain is set by external resistors R1 and R2. The inputs and outputs of the amplifier are rail-to-rail compatible
to the supply VDD.
An internal multiplexer selects the desired sensor signal to process, which is programmable through the SPI.
R2
C
CH1N
−
R1
Knock Sensor 1
CH1P
+
CH1FB
+
CH2FB
Vref
CH2P
C
R1
−
CH2N
Knock Sensor 2
R2
NOTE: The series capacitor C is not mandatory and may be removed in some application circuits
Figure 4. Input Signal Configuration
8.3.2 Timing Information
This is an 8-bit SPI protocol used to communicate with the microcontroller in the system for setting various
operating parameters.
When CS is held high, the signals on the SCLK and SDI lines are ignored and SDO is forced into a highimpedance state. SCLK must be low when CS is asserted low.
On each falling edge of the SCLK pulse after CS is asserted low, the new byte is serially shifted into the register.
The most significant bit (MSB) is shifted first. Only eight bits in a frame are acceptable. When a number of bits
shifted varies from the value eight, the information is ignored and the register retains the old setting.
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Feature Description (continued)
The shift register transfers the data into a latch register after the eighth SCLK clock pulse and when CS
transitions from low to high (see Figure 1).
The function of the integration mode is to ignore any SPI frame transmission when the INT/HOLD bit = 1. In the
hold mode with INT/HOLD = 0, all necessary bytes may be transmitted.
8.4 Device Functional Modes
8.4.1 System Transfer Equation
The output voltage may be derived from:
t
VO = VIN ´ AIN ´ AP ´ ABP ´ AINT ´ INT ´ A O + VRESET
tC
where
•
•
•
•
•
•
•
•
•
•
VIN = Input voltage peak (amplitude)
VO = Output voltage
AIN = Input amplifier gain setting
AP = Programmable gain setting
ABP = Gain of band-pass filter
AINT = Gain of integrator
tINT = Integration time from 0.5 to 10 ms
AO = Output buffer gain
τC = Programmable integrator time constant
VRESET = Reset voltage from which the integration operation starts
If ABP = AINT = 2 and AIN = AO = 1, then:
8 t
VO = VIN ´ AP ´ ´ INT + VRESET
P tC
(1)
(2)
8.4.2 Programming in Normal Mode (TEST = 1)
To enable programming in the normal mode, the TEST terminal must be high. Communication is through the SPI
and the CS terminal is used to enable the IC. The information on the SDI line consists of two parts: address and
data.
After power up, the SPI is in default mode (see Table 1).
8.4.3 Default SPI Mode
The SPI is in the default mode on the power-up sequence. In this case, the SDO directly equals the SDI (echo
function). In this mode, five commands can be transmitted by the master controller to configure the IC (see
Table 1).
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Device Functional Modes (continued)
Table 1. Default SPI Mode
NO.
1
Code
010 D[4:0]
Command (t)
Data
Response (t)
OSCIN frequency
D[4:1] = 0000 → 4 MHz
D[4:1] = 0001 → 5 MHz
D[4:1] = 0010 → 6 MHz
D[4:1] = 0011 → 8 MHz
D[4:1] = 0100 → 10 MHz
D[4:1] = 0101 → 12 MHz
D[4:1] = 0110 → 16 MHz
D[4:1] = 0111 → 20 MHz
D[4:1] = 1000 → 24 MHz
Set the prescaler and SDO status
SDI
(010 D[4:0])
D[0] = 0 → SDO active
D[1] = 1 → SDO high impedance
2
1110 000 D[0]
Select the channel
D[0] = 0 → Channel 1 selected
D[1] = 1 → Channel 2 selected
SDI
(1110 000 D[0])
3
00 D[5:0]
Set the band-pass center frequency
D[5:0] (see Table 3)
SDI
(00 D[5:0])
4
10 D[5:0]
Set the gain
D[5:0] (see Table 3)
SDI
(10 D[5:0])
5
110 D[4:0]
Set the integration time constant
D[4:0] (see Table 3)
SDI
(100 D[4:0])
6
0111 0001
Set SPI configuration to the advanced mode (1)
None
SDI
(0111 0001)
(1)
Command number 6 is to enter into the advanced mode.
8.4.4 Advanced SPI Mode
The advanced SPI mode has additional features to the default SPI mode. A control byte is written to the SDI and
shifted with the MSB first. The response byte on the SDO is shifted out with the MSB first. The response byte
corresponds to the previous command. Therefore, the SDI shifts in a control byte n and shifts out a response
command byte n − 1. Each control/response pair of commands requires two full 8-bit shift cycles to complete a
transmission. Table 2 shows the control bytes with the expected response.
In the advanced SPI mode, only a power-down condition may reset the SPI mode to the default state on the
subsequent power-up cycle.
Table 2. Advanced SPI Mode Control Bytes and Expected Response
NO.
1
Code
010 D[4:0]
Command (t)
Data
Set the prescaler and SDO status
Response (t)
OSCIN frequency
D[4:1] = 0000 → 4 MHz
D[4:1] = 0001 → 5 MHz
D[4:1] = 0010 → 6 MHz
D[4:1] = 0011 → 8 MHz
D[4:1] = 0100 → 10 MHz
D[4:1] = 0101 → 12 MHz
D[4:1] = 0110 → 16 MHz
D[4:1] = 0111 → 20 MHz
D[4:1] = 1000 → 24 MHz
Byte 1 (D7 to D0) of the digital
integrator output
D[0] = 0 → SDO active
D[1] = 1 → SDO high impedance
2
1110 000 D[0]
Select the channel
D[0] = 0 → Channel 1 selected
D[1] = 1 → Channel 2 selected
D9 to D8 of digital integrator
output followed by six zeros
3
00 D[5:0]
Set the band-pass center frequency
D[5:0] (see Table 3)
Byte 1 (MSB) of the 00000001
4
10 D[5:0]
Set the gain
D[5:0] (see Table 3)
Byte 2 (LSB) 11100000
5
110 D[4:0]
Set the integration time constant
D[4:0] (see Table 3)
SPI configuration (MSB)
01110001(LSB)
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Table 2. Advanced SPI Mode Control Bytes and Expected Response (continued)
NO.
6
Code
0111 0001
Command (t)
Data
Response (t)
Inverted SPI configuration
(MSB)10001110(LSB)
Set SPI configuration to the advanced mode None
8.4.5 Digital Data Output from the TPIC8101
Digital output:
• Digital integrator output (10 bits, D[9:0])
• First response byte (MSB): 8 bits for D7 to D0 of the integrator output
• Second response byte (LSB): 2 bits for D9 to D8 of the integrator output followed by six zeros
8.5 Programming
Table 3. Integrator Programming
Decimal Value
(D4:D0)
Integrator Time
Constant
(µs)
Band-Pass
Frequency
(kHz)
Gain
Decimal Value
(D5:D0)
Band-Pass
Frequency
(kHz)
Gain
0
40
1.22
2
32
4.95
0.421
1
45
1.26
1.882
33
5.12
0.4
2
50
1.31
1.778
34
5.29
0.381
3
55
1.35
1.684
35
5.48
0.364
4
60
1.4
1.6
36
5.68
0.348
5
65
1.45
1.523
37
5.9
0.333
6
70
1.51
1.455
38
6.12
0.32
7
75
1.57
1.391
39
6.37
0.308
8
80
1.63
1.333
40
6.64
0.296
9
90
1.71
1.28
41
6.94
0.286
10
100
1.78
1.231
42
7.27
0.276
11
110
1.87
1.185
43
7.63
0.267
12
120
1.96
1.143
44
8.02
0.258
13
130
2.07
1.063
45
8.46
0.25
14
140
2.18
1
46
8.95
0.236
15
150
2.31
0.944
47
9.5
0.222
16
160
2.46
0.895
48
10.12
0.211
17
180
2.54
0.85
49
10.46
0.2
18
200
2.62
0.81
50
10.83
0.19
19
220
2.71
0.773
51
11.22
0.182
20
240
2.81
0.739
52
11.65
0.174
21
260
2.92
0.708
53
12.1
0.167
22
280
3.03
0.68
54
12.6
0.16
23
300
3.15
0.654
55
13.14
0.154
24
320
3.28
0.63
56
13.72
0.148
25
360
3.43
0.607
57
14.36
0.143
26
400
3.59
0.586
58
15.07
0.138
27
440
3.76
0.567
59
15.84
0.133
28
480
3.95
0.548
60
16.71
0.129
29
520
4.16
0.5
61
17.67
0.125
30
560
4.39
0.471
62
18.76
0.118
31
600
4.66
0.444
63
19.98
0.111
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8.5.1 Programming Examples
• Prescaler/SDO status:
– 01000101 programs an input frequency of 6 MHz with SDO terminal in high impedance.
• Channel selection:
– 1110001 selects channel 2.
• Band-pass frequency:
– 00100111 programs a band-pass filter with center frequency of 6.37 kHz.
• Gain control:
– 10010100 programs the gain with attenuation of 0.739.
• Integrator time constant:
– 11000011 programs integrator time constant of 55 µs. Table 1 through Table 3 show the binary values.
8.5.2 Programming in TEST Mode (TEST = 0)
To enter test mode, the TEST terminal must be low. See Table 4 for the signal that may be accessed in this
mode.
Table 4. Programming in TEST Mode
SDI
Command
MSB, LSB
NO.
Test Description
T1
AAF individual test
1111, 0000
ADC clock
Deactivates the input and output operational amplifiers
AAF input connected to CH1FB terminal
AAF output connected to OUT terminal
T2
In-line test to AAF
output
1111, 0000
None
Deactivates the output operational amplifier
AAF output connected to OUT terminal
T3
Output buffer individual
test
None
Opens the feedback loop of the output buffer and deactivates the input
operational amplifier and AAF
CH1FB connected to positive input terminal of operational amplifier
CH2FB connected to negative input terminal of operational amplifier
T4
ADC/DAC individual
test (with the output
buffer)
1111, 0011
ADC data
Deactivates the input operational amplifiers and AAF INT/HOLD =
ADC_Sync
OSCIN = ADC_SCLK
DAC shifted in from SDI terminal
T5
ADC/DAC individual
test (without the output
buffer)
1111, 0100
ADC data
Deactivates the input operational amplifiers, AAF, and output buffer
INT/HOLD = ADC_Sync
OSCIN = ADC_SCLK
DAC is shifted in from SDI terminal
T6
In-line test to ADC
output
1111, 0011
ADC data
INT/HOLD = ADC_Sync
OSCIN = ADC_SCLK
DAC shifted in from SDI terminal
Clamp flag
D[2:0]
Implies command number 6 (advanced SPI mode)
D[0]: Gain stage clamp status
D[1]: BPF stage clamp status
D[2]: INT stage clamp status
D = 0 → No clamp activated
D = 1 → Clamp activated
T7
Reading of digital
clamp flag
1111, 0010
1111, 1000
Response
Description
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPIC8101 can interface with one or two flat type or resonant knock sense elements. Flat type (non-resonant)
sensors have a wider frequency bandwidth than resonant type sensors. A microprocessor must also interface
with the TPIC8101 as shown in Figure 5. The microprocessor may sample the output data either through SPI or
by sampling the analog OUT signal.
9.2 Typical Application
VDD
OUT
4.7 µF
A/D
R2
CH1FB
3.3 nF
CS
CH1N
SCLK
R1
Knock Sensor 1
TPIC8101
CH1P
SDI
SDO
Microprocessor
Vref
100 nF
CH2P
INT/HOLD
470 pF
XIN
R2
CH2FB
3.3 nF
TEST
1 kΩ
XOUT
CH2N
1 MΩ
R1
Knock Sensor 2
GND
Figure 5. Application Schematic
9.2.1 Design Requirements
After the knock sense element and the microprocessor are chosen, the designer can choose the TPIC8101
settings. The settings that must be programmed through SPI are: ƒbp, ƒosc, AP, τC, and channel. If the analog
output is used, then the INT/HOLD signal must be supplied by the microprocessor.
The input amplifier gain (AIN) is typically set to 1 by setting R1 = R2. R1 and R2 should be chosen to be greater
than 25 kΩ.
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Typical Application (continued)
Table 5. System Design Constraints
PARAMETER
CONSTRAINT
VALUE FOR DESIGN EXAMPLE
VIN
Amplitude of input signal from knock sensor; determined by knock
300 mVpp
sensor specification
ƒbp
Bandpass center frequency; determined by knock sensor
specification
7.3 kHz
ƒosc
Oscillator frequency; determined by microprocessor
6 MHz
tINT
Integration window; determined by system specification. This is
half the period of the INT/HOLD signal (when using a 50% duty
cycle) which is generated by the microprocessor.
3 ms
Maximum voltage on the OUT pin for the maximum VIN
4.5 V
VOUT
9.2.2 Detailed Design Procedure
Design parameters to set:
AIN: Input amplifier gain, typically set to 1
AP: Programmable gain
τC: Integration time constant
Design equations:
R2
AIN
R1
tINT
WC
2 u S u VOUT
(3)
(4)
Use Equation 2 to solve for AP:
VRESET
V
S
AP ( ) u WC u OUT
8
VIN u tINT
(5)
For this design example, use the parameters specified in Table 5. This example is for a resonant knock sensor.
Using Equation 4:
3 ms
WC
2 u S u 4.5
106 Ps
(6)
Using Equation 5:
4.5 V 0.125 V
S
AP ( ) u (106 Ps) u
8
(0.15 V) u (3 ms)
(7)
AP = 0.38
Table 6 lists the parameters to program.
Table 6. Parameters to Program
Parameter
Programmed
Value
Calculated Value
Code
DEC
SPI
HEX
Oscillator
6 MHz
6 MHz
1000010
Channel
1
1
ƒC0
7.3 kHz
7.27 kHz
42
2A
101010
AP
0.38
0.381
34
22
10100010
τC
106 µs
100 µs
10
0A
10001010
11100000
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Figure 6 shows the input and output signals for this design example.
For a resonant knock sensor (as in the design example), the center frequency of the bandpass filter is set to the
resonant frequency of the knock sensor. For a flat-type knock sensor, the bandpass filter design equation can be
used to determine where the center frequency should be set.
The transfer function of the biquadratic bandpass IIR filter is:
HBP (z)
GBP u
With b0
Z
u Su
b0 b2 u z 2
a0 a1 u z 1 a2 u z 2
D , b2
fcenter
fsampling
With GBP
2, Q
Da0
,Q
1 D , a1
2 u cos(Z) , a2
fcenter
, and G(fc2 )
fc2 fc1
G(fc1)
1 D , D
sin(Z)
2uQ
(8)
G(fcenter ) 3 dB
2.3
(9)
9.2.3 Application Curve
7270 kHz,
300 mVpp
INT, 3 ms
4.48 V
Output
Figure 6. TPIC8101 Waveform
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10 Power Supply Recommendations
A 5-V ±0.25 V power supply should be used to power the TPIC8101. It can operate on 5 V ±0.5 V; however, the
electrical characteristics are not specified in that case. The maximum operating current consumption is 20 mA.
11 Layout
11.1 Layout Guidelines
The layout of the TPIC8101 can be routed as a two layer board, with the top layer primarily used for routing
signals and the second layer used primarily as a ground plane.
The capacitors on VDD and VREF should be kept close to their respective pins and tie immediately through vias
to ground. VREF should be connected to CH1P and CH2P in as tight a loop as possible. It can be routed on the
second layer if necessary.
The resistor between Ch1N and CH1FB and CH2N and CH2FB should be kept close to the respective pins. The
rest of the input signal chain should be routed cleanly to avoid noise interference.
The filter on XIN and XOUT for the input clock should be kept close to the XIN and XOUT pins.
11.2 Layout Example
Expand GND plane to second
layer through vias, and use to
fill in spaces on top layer
To clock input
VDD
CH1P
GND
CH1N
VREF
CH1FB
OUT
CH2FB
NC
CH2N
NC
CH2P
INT/HOLD
/TEST
/CS
SCLK
XIN
SDI
XOUT
SDO
To channel 1 sensor
To channel 2 sensor
Figure 7. PCB Layout Example
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE MATERIALS INFORMATION
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14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPIC8101DWR
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPIC8101DWR
SOIC
DW
20
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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