Texas Instruments | DS26C31x CMOS Quad Tri-State Differential Line Driver (Rev. C) | Datasheet | Texas Instruments DS26C31x CMOS Quad Tri-State Differential Line Driver (Rev. C) Datasheet

Texas Instruments DS26C31x CMOS Quad Tri-State Differential Line Driver (Rev. C) Datasheet
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DS26C31M, DS26C31T
SNLS375C – JUNE 1998 – REVISED JANUARY 2015
DS26C31x CMOS Quad Tri-State Differential Line Driver
1 Features
3 Description
•
•
•
•
•
The DS26C31 device is a quad differential line driver
designed for digital data transmission over balanced
lines. The DS26C31T meets all the requirements of
EIA standard RS-422 while retaining the low power
characteristics of CMOS. The DS26C31M is
compatible with EIA standard RS-422; however, one
exception in test methodology is taken(2). This
enables the construction of serial and terminal
interfaces
while
maintaining
minimal
power
consumption.
1
•
•
•
•
•
TTL Input Compatible
Typical Propagation Delays: 6 ns
Typical Output Skew: 0.5 ns
Outputs Will Not Load Line When VCC = 0 V
DS26C31T Meets the Requirements of EIA
Standard RS-422
Operation From Single 5-V Supply
Tri-State Outputs for Connection to System Buses
Low Quiescent Current
Available in Surface Mount
Mil-Std-883C Compliant
2 Applications
Differential Line Driver for RS-422 Applications
The DS26C31 accepts TTL or CMOS input levels and
translates these to RS-422 output levels. This part
uses special output circuitry that enables the drivers
to power down without loading down the bus. This
device has enable and disable circuitry common to all
four drivers. The DS26C31 is pin compatible to the
AM26LS31 and the DS26LS31.
All inputs are protected against damage due to
electrostatic discharge by diodes to VCC and ground.
Device Information(1)
PART NUMBER
DS26C31M
DS26C31T
PACKAGE
BODY SIZE (NOM)
SNLS3759577
9.90 mm × 3.91 mm
PDIP (16)
19.304 mm × 6.35 mm
SNLS3759577
9.90 mm × 3.91 mm
PDIP (16)
19.304 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) The DS26C31M (−55°C to 125°C) is tested with VOUT
between 6 V and 0 V while RS-422A condition is 6 V and
−0.25 V.
4 Device Logic Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS26C31M, DS26C31T
SNLS375C – JUNE 1998 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
1
1
1
1
2
3
4
10 Application and Implementation........................ 14
7.1
7.2
7.3
7.4
7.5
4
4
5
6
12.1 Layout Guidelines ................................................. 16
12.2 Layout Example .................................................... 16
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
DC Electrical Characteristics ....................................
Switching Characteristics .........................................
Comparison Table of Switching Characteristics into
“LS-Type” Load ..........................................................
7.6 Typical Characteristics ..............................................
8
9
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 13
Features ..................................................................
Applications ...........................................................
Description .............................................................
Device Logic Diagram ...........................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6
7
Parameter Measurement Information ................ 11
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
10.1 Application Information.......................................... 14
10.2 Typical Application ................................................ 14
11 Power Supply Recommendations ..................... 16
12 Layout................................................................... 16
13 Device and Documentation Support ................. 17
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
14 Mechanical, Packaging, and Orderable
Information ........................................................... 17
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
•
Page
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
Changes from Revision A (April 2013) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 9
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6 Pin Configuration and Functions
D, NFG Package
16 Pins
Top View
NAJ Package
20 Pins
Top View
Pin Functions
PIN
NAME
NO. (1)
I/O
DESCRIPTION
DIFFERENTIAL SIGNALING I/O
CHANNEL A
OUTPUTS (–, +)
3, 2
O
Channel A inverting and non-inverting differential driver outputs
CHANNEL B
OUTPUTS (–, +)
5, 6
O
Channel B inverting and non-inverting differential driver outputs
CHANNEL C
OUTPUTS (–, +)
11, 10
O
Channel C inverting and non-inverting differential driver outputs
CHANNEL D
OUTPUTS (–, +)
13, 14
O
Channel D inverting and non-inverting differential driver outputs
INPUT A
1
I
TTL/CMOS compatible input for channel A
INPUT B
7
I
TTL/CMOS compatible input for channel B
INPUT C
9
I
TTL/CMOS compatible input for channel C
INPUT D
15
I
TTL/CMOS compatible input for channel D
ENABLE
4
I
Logic-high ENABLE Control
ENABLE
12
I
Logic-low ENABLE Control
GND
8
—
GND Pin
VCC
16
—
Supply pin, provide 5 V supply
CONTROL PINS
POWER
(1)
Pin numbers correspond to PDIP and SOIC packages.
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2) (3)
MIN
MAX
UNIT
Supply Voltage (VCC)
−0.5
7
V
DC Input Voltage (VIN)
−1.5
VCC +1.5
V
DC Output Voltage (VOUT)
−0.5
7
V
Clamp Diode Current (IIK, IOK)
–20
20
mA
DC Output Current, per pin (IOUT)
–150
150
mA
Ceramic “NFE” package
2419
mW
Plastic “NFG” package
1736
mW
SOIC “D” package
1226
mW
Ceramic “NAD” package
1182
mW
Ceramic “NAJ” package
2134
mW
(Soldering, 4 s)
260
°C
150
°C
DC VCC or GND Current, per pin (ICC)
Max Power Dissipation (PD) at 25°C (4)
Lead Temperature (TL)
−65
Storage Temperature, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive, all currents out of device
pins are negative.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Ratings apply to ambient temperature at 25°C. Above this temperature derate NFG package at 13.89 mW/°C, NFE package 16.13
mW/°C, D package 9.80 mW/°C, NAJ package 12.20 mW/°C, and NAD package 6.75 mW/°C.
7.2 Recommended Operating Conditions
Supply Voltage (VCC)
MIN
MAX
UNIT
4.50
5.50
V
VCC
V
DC Input or Output Voltage
(VIN, VOUT)
0
Operating Temperature Range (TA)
DS26C31T
−40
85
°C
DS26C31M
−55
125
°C
500
ns
Input Rise or Fall Times (tr, tf)
4
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7.3 DC Electrical Characteristics
VCC = 5 V ± 10% (unless otherwise specified) (1)
PARAMETER
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
TEST CONDITIONS
MIN
TYP
MAX
2.0
V
0.8
VIN = VIH or VIL,
2.5
UNIT
3.4
V
V
IOUT = −20 mA
VOL
Low Level Output Voltage
VIN = VIH or VIL,
0.3
0.5
V
IOUT = 20 mA
VT
RL = 100 Ω
Differential Output Voltage
See
|VT| − |VT |
Difference In Differential Output
2.0
3.1
V
(2)
RL = 100 Ω
0.4
V
3.0
V
0.4
V
±1.0
μA
See (2)
VOS
Common Mode Output Voltage
RL = 100 Ω
1.8
See (2)
|VOS − VOS |
Difference In Common Mode
Output
RL = 100 Ω
IIN
Input Current
VIN = VCC, GND, VIH, or VIL
ICC
Quiescent Supply Current (3)
DS26C31T
VIN = VCC or GND
200
500
μA
IOUT = 0 μA
VIN = 2.4 V or 0.5 V (3)
0.8
2.0
mA
DS26C31M
VIN = VCC or GND
200
500
μA
IOUT = 0 μA
VIN = 2.4 V or 0.5 V (3)
0.8
2.1
mA
±0.5
±5.0
μA
−150
mA
100
μA
−100
μA
100
μA
−100
μA
IOZ
TRI-STATE Output Leakage
Current
See (2)
VOUT = VCC or GND
ENABLE = VIL
ENABLE = VIH
ISC
Output Short Circuit Current
VIN = VCC or GND (2) (4)
IOFF
Output Leakage Current Power
Off (2)
DS26C31T
VOUT = 6 V
VCC = 0 V
VOUT = −0.25 V
DS26C31M
VOUT = 6 V
VCC = 0 V
VOUT = 0 V (5)
(1)
(2)
(3)
(4)
(5)
−30
Unless otherwise specified, min/max limits apply across the recommended operating temperature range. All typicals are given for VCC =
5 V and TA = 25°C.
See EIA Specification RS-422 for exact test conditions.
Measured per input. All other inputs at VCC or GND.
This is the current sourced when a high output is shorted to ground. Only one output at a time should be shorted.
The DS26C31M (−55°C to +125°C) is tested with VOUT between +6 V and 0 V while RS-422A condition is +6 V and −0.25 V.
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7.4 Switching Characteristics
VCC = 5 V ±10%, tr ≤ 6 ns, tf ≤ 6 ns (Figure 22, Figure 23, Figure 24, Figure 25) (1)
PARAMETER
tPLH, tPHL
TEST CONDITIONS
Propagation Delays Input to Output
(2)
Skew
S1 Open
MIN
TYP
2
DS26C31T
DS26C31M
MAX
MAX
UNIT
6
11
14
ns
S1 Open
0.5
2.0
3.0
ns
6
10
14
ns
tTLH, tTHL
Differential Output Rise And Fall
Times
S1 Open
tPZH
Output Enable Time
S1 Closed
11
19
22
ns
tPZL
Output Enable Time
S1 Closed
13
21
28
ns
tPHZ
Output Disable Time
(3)
S1 Closed
5
9
12
ns
tPLZ
Output Disable Time (3)
S1 Closed
7
11
14
CPD
Power Dissipation Capacitance (4)
CIN
Input Capacitance
(1)
(2)
(3)
(4)
ns
50
pF
6
pF
Unless otherwise specified, min/max limits apply across the recommended operating temperature range. All typicals are given for VCC =
5 V and TA = 25°C.
Skew is defined as the difference in propagation delays between complementary outputs at the 50% point.
Output disable time is the delay from ENABLE or ENABLE being switched to the output transistors turning off. The actual disable times
are less than indicated due to the delay added by the RC time constant of the load.
CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS
= CPD VCC f + ICC.
7.5 Comparison Table of Switching Characteristics into “LS-Type” Load
VCC = 5 V, TA = 25°C, tr ≤ 6 ns, tf ≤ 6 ns (Figure 23, Figure 25, Figure 26, Figure 27)
TEST
CONDITIONS
PARAMETER
tPLH, tPHL
Propagation Delays Input to Output
(1)
DS26C31T
DS26LS31C
UNIT
TYP
MAX
TYP
MAX
6
8
10
15
ns
0.5
1.0
2.0
6.0
ns
4
6
6
9
15
35
ns
4
7
15
25
ns
14
20
20
30
ns
11
17
20
30
ns
CL = 30 pF
S1 Closed
S2 Closed
See (2)
Skew
CL = 30 pF
S1 Closed
S2 Closed
tTHL, tTLH
Differential Output Rise and Fall
Times
CL = 30 pF
S1 Closed
ns
S2 Closed
tPLZ
Output Disable Time (3)
CL = 10 pF
S1 Closed
S2 Open
tPHZ
Output Disable Time (3)
CL = 10 pF
S1 Open
S2 Closed
tPZL
Output Enable Time
CL = 30 pF
S1 Closed
S2 Open
tPZH
Output Enable Time
CL = 30 pF
S1 Open
S2 Closed
(1)
(2)
(3)
6
This table is provided for comparison purposes only. The values in this table for the DS26C31 reflect the performance of the device but
are not tested or verified.
Skew is defined as the difference in propagation delays between complementary outputs at the 50% point.
Output disable time is the delay from ENABLE or ENABLE being switched to the output transistors turning off. The actual disable times
are less than indicated due to the delay added by the RC time constant of the load.
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7.6 Typical Characteristics
Figure 1. Differential Propagation Delay vs Temperature
Figure 2. Differential Propagation Delay vs Power Supply
Voltage
Figure 3. Differential Skew vs Temperature
Figure 4. Differential Skew vs Power Supply Voltage
Figure 5. Differential Transition Time vs Temperature
Figure 6. Differential Transition Time vs Power Supply
Voltage
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Typical Characteristics (continued)
8
Figure 7. Complementary Skew vs Temperature
Figure 8. Complementary Skew vs Power Supply Voltage
Figure 9. Differential Output Voltage vs Output Current
Figure 10. Differential Output Voltage vs Output Current
Figure 11. Output High Voltage vs Output High Current
Figure 12. Output High Voltage vs Output High Current
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Typical Characteristics (continued)
Figure 13. Output Low Voltage vs Output Low Current
Figure 14. Output Low Voltage vs Output Low Current
Figure 15. Supply Current vs Temperature
Figure 16. Output Low Voltage vs Output Low Current
Figure 17. Output Low Voltage vs Output Low Current
Figure 18. Supply Current vs Temperature
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Typical Characteristics (continued)
Figure 19. Supply Current vs Power Supply Voltage
Figure 20. Output Short Circuit Current vs Temperature
Figure 21. Output Short Circuit Current vs Power Supply Voltage
10
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8 Parameter Measurement Information
Note: C1 = C2 = C3 = 40 pF (Including Probe and Jig Capacitance), R1 = R2 = 50Ω, R3 = 500Ω.
Figure 22. AC Test Circuit
Figure 23. Propagation Delays
Figure 24. Enable and Disable Times
Input pulse; f = 1 MHz, 50%; tr ≤ 6 ns, tf ≤ 6 ns
Figure 25. Differential Rise and Fall Times
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Parameter Measurement Information (continued)
Figure 26. Load AC Test Circuit for “LS-Type” Load
Figure 27. Enable and Disable Times for “LS-Type” Load
12
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9 Detailed Description
9.1 Overview
The DS26C31 is a quad differential line driver designed for data transmission over balanced cable or printed
circuit board traces. The DS26C31M supports a temperature range of -55°C to 125°C, while the DS26C31T
supports a temperature range of -40°C to 85°C.
9.2 Functional Block Diagram
DS26C31x
INPUT A
CHANNEL
A OUTPUT
INPUT B
CHANNEL
B OUTPUT
INPUT C
CHANNEL
C OUTPUT
INPUT D
CHANNEL
D OUTPUT
ENABLE
_______
ENABLE
5.0V
VDD
GND
0.1F
9.3 Feature Description
Each driver converts the TTL or CMOS signal at its input to a pair of complementary differential outputs. The
drivers are enabled when the ENABLE control pin is a logic HIGH or when the ENABLE control pin is a logic
LOW.
9.4 Device Functional Modes
Table 1. Function Table (1)
ENABLE
ENABLE
INPUT
NON-INVERTING OUTPUT
L
H
X
Z
Z
L
L
H
H
H
L
All other combinations of enable inputs
(1)
INVERTING OUTPUT
L = Low logic state
X = Irrelevant
H = High logic state
Z = Tri-state (high impedance)
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The DS26C31 is a quad differential line driver designed for applications that require long distance digital data
transmission over balanced cables. The DS26C31 can be used in applications that require conversion from TTL
or CMOS input levels to differential signal levels, compatible to RS-422. The use of complimentary signaling in a
balanced transmission media provides good immunity in the midst of noisy environments or shifts in ground
reference potential.
10.2 Typical Application
Figure 28 depicts a typical implementation of the DS26C31x device in a RS-422 application.
*RT is optional although highly recommended to reduce reflection.
Figure 28. Two-Wire Balanced System, RS-422
10.2.1 Design Requirements
• Apply TTL or LVCMOS signal to driver input lines INPUT A-D.
• Transmit complementary outputs at OUTPUT A-D.
• Use controlled-impedance transmission lines such as printed circuit board traces, twisted-pair wires or parallel
wire cable.
• Place a terminating resistor at the far end of the differential pair.
10.2.2 Detailed Design Procedure
• Connect VCC and GND pins to the power and ground planes of the PCB with a 0.1-µF bypass capacitor.
• Use TTL/LVCMOS logic levels at INPUT A-D.
• Use controlled-impedance transmission media for the differential output signals.
• Place an optional terminating resistor at the far-end of the differential pair to avoid reflection.
14
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Typical Application (continued)
10.2.3 Application Curves
Figure 29. No Load Supply Current vs Data Rate
Figure 30. Loaded Supply Current vs Data Rate
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11 Power Supply Recommendations
It is recommended that the supply (VCC) and ground (GND) pins be connected to power planes that are placed
in the inner layers of the printed circuit board. A 0.1-µF bypass capacitor should be connect to the VCC pin such
that the capacitor is as close as possible to the device.
12 Layout
12.1 Layout Guidelines
The output differential signals of the device should be routed on one layer of the board, and clearance should be
provided in order to minimize crosstalk between differential pairs that may be running in parallel over a long
distance. Additionally, the differential pairs should have a controlled impedance with minimum impedance
discontinuities and be terminated at the far-end, near the receiver, with a resistor that is closely matched to the
differential pair impedance in order to minimize transmission line reflections. The differential pairs should be
routed with uniform trace width and spacing to minimize impedance mismatching.
12.2 Layout Example
Via to VCC
Plane
Input
Via to GND
Plane
16
1
Bypass Capacitor
TX Differential Pair
2
15
3
14
4
13
Input
TX Differential Pair
Enable
DS26C31M/DS26C31T
TX Differential Pair
Input
5
12
6
11
7
10
8
9
Enable
TX Differential Pair
Input
Via to GND
Plane
Figure 31. DS26C31 Example Layout
16
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DS26C31M
Click here
Click here
Click here
Click here
Click here
DS26C31T
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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9-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS26C31TM/NOPB
ACTIVE
SOIC
D
16
48
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS26C31TM
DS26C31TMX/NOPB
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS26C31TM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS26C31TMX/NOPB
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.3
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS26C31TMX/NOPB
SOIC
D
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
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