Texas Instruments | SNx5176B Differential Bus Transceivers (Rev. F) | Datasheet | Texas Instruments SNx5176B Differential Bus Transceivers (Rev. F) Datasheet

Texas Instruments SNx5176B Differential Bus Transceivers (Rev. F) Datasheet
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SN65176B, SN75176B
SLLS101F – JULY 1985 – REVISED JANUARY 2015
SNx5176B Differential Bus Transceivers
1 Features
3 Description
•
•
The SN65176B and SN75176B differential bus
transceivers are designed for bidirectional data
communication on multipoint bus transmission lines.
They are designed for balanced transmission lines
and meet ANSI Standards TIA/EIA-422-B and
TIA/EIA-485-A and ITU Recommendations V.11 and
X.27.
1
•
•
•
•
•
•
•
•
•
•
•
Bidirectional Transceivers
Meet or Exceed the Requirements of ANSI
Standards TIA/EIA-422-B and TIA/EIA-485-A
and ITU Recommendations V.11 and X.27
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
3-State Driver and Receiver Outputs
Individual Driver and Receiver Enables
Wide Positive and Negative Input/Output Bus
Voltage Ranges
± 60-mA Max Driver Output Capability
Thermal Shutdown Protection
Driver Positive and Negative Current Limiting
12-kΩ Min Receiver Input Impedance
± 200-mV Receiver Input Sensitivity
50-mV Typ Receiver Input Hysteresis
Operate From Single 5-V Supply
2 Applications
•
•
•
•
•
•
•
•
Chemical/Gas Sensors
Digital Signage
HMI (Human Machine Interfaces)
Motor Controls: AC Induction, Brushed and Brushless DC, Low- and High-Voltage, Stepper Motors,
and Permanent Magnets
TETRA Base Stations
Telecom Towers: Remote Electrical Tilt Units
(RET) and Tower Mounted Amplifiers (TMA)
Weigh Scales
Wireless Repeaters
The SN65176B and SN75176B devices combine a 3state differential line driver and a differential input line
receiver, both of which operate from a single 5-V
power supply. The driver and receiver have activehigh and active-low enables, respectively, that can be
connected together externally to function as a
direction control. The driver differential outputs and
the receiver differential inputs are connected
internally to form differential input/output (I/O) bus
ports that are designed to offer minimum loading to
the bus when the driver is disabled or VCC = 0. These
ports feature wide positive and negative commonmode voltage ranges, making the device suitable for
party-line applications.
The driver is designed for up to 60 mA of sink or
source current. The driver features positive and
negative current limiting and thermal shutdown for
protection from line-fault conditions. Thermal
shutdown is designed to occur at a junction
temperature of approximately 150°C. The receiver
features a minimum input impedance of 12 kΩ, an
input sensitivity of ±200 mV, and a typical input
hysteresis of 50 mV.
Device Information(1)
PART NUMBER
SNx5176
PACKAGE (PIN)
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
SOP (8)
6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
3
DE
4
D
2
RE
6
A
1
R
7
Bus
B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65176B, SN75176B
SLLS101F – JULY 1985 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
6
6
6
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics – Driver .............................
Electrical Characteristics – Receiver ........................
Switching Characteristics – Driver ............................
Switching Characteristics – Receiver........................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ............................................... 14
10.3 System Examples ................................................. 15
11 Power Supply Recommendations ..................... 16
12 Layout................................................................... 16
12.1 Layout Guidelines ................................................. 16
12.2 Layout Example .................................................... 16
13 Device and Documentation Support ................. 16
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
14 Mechanical, Packaging, and Orderable
Information ........................................................... 16
5 Revision History
Changes from Revision E (January 2014) to Revision F
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
•
Moved Typical Characteristics inside of the Specifications section. ...................................................................................... 7
Changes from Revision D (April 2003) to Revision E
Page
•
Updated document to new TI data sheet format - no specification changes. ........................................................................ 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Added ESD warning. ............................................................................................................................................................ 16
2
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Copyright © 1985–2015, Texas Instruments Incorporated
Product Folder Links: SN65176B SN75176B
SN65176B, SN75176B
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SLLS101F – JULY 1985 – REVISED JANUARY 2015
6 Pin Configuration and Functions
Top View
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
R
1
O
Logic Data Output from RS-485 Receiver
RE
2
I
Receive Enable (active low)
DE
3
I
Driver Enable (active high)
D
4
I
Logic Data Input to RS-485 Driver
GND
5
—
Device Ground Pin
A
6
I/O
RS-422 or RS-485 Data Line
B
7
I/O
RS-422 or RS-485 Data Line
VCC
8
—
Power Input. Connect to 5-V Power Source.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply voltage (2)
VCC
Voltage range at any bus terminal
–10
UNIT
7
V
15
V
VI
Enable input voltage
5.5
V
TJ
Operating virtual junction temperature
150
°C
Tstg
Storage temperature range
150
°C
260
°C
–65
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
7.2 Recommended Operating Conditions
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage
D, DE, and RE
VIL
Low-level input voltage
D, DE, and RE
VID
Differential input voltage (1)
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
12
V
-7
2
V
0.8
V
±12
V
–60
mA
–400
µA
Driver
Receiver
Driver
60
Receiver
8
SN65176B
–40
105
SN75176B
0
70
mA
°C
Differential input/output bus voltage is measured at the non-inverting terminal A, with respect to the inverting terminal B.
7.3 Thermal Information
SNx5176
THERMAL METRIC
(1)
BD
BP
BPS
UNIT
95
°C/W
8 PINS
RθJA
(1)
4
Junction-to-ambient thermal resistance
97
85
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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SLLS101F – JULY 1985 – REVISED JANUARY 2015
7.4 Electrical Characteristics – Driver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
VIK
Input clamp voltage
II = –18 mA
VO
Output voltage
IO = 0
0
|VOD1|
Differential output voltage
IO = 0
1.5
RL = 100 Ω, see Figure 10
½ VOD1 or 2
TYP (2)
MAX
UNIT
–1.5
V
6
V
3.6
6
V
2.5
5
(3)
|VOD2|
Differential output voltage
VOD3
Differential output voltage
See
∆|VOD|
Change in magnitude of
differential output voltage (5)
RL = 54 Ω or 100 Ω, see Figure 10
VOC
Common-mode output voltage
RL = 54 Ω or 100 Ω, see Figure 10
∆|VOC|
Change in magnitude of
common-mode output
voltage (5)
RL = 54 Ω or 100 Ω, see Figure 10
IO
Output current
Output disabled (6)
IIH
High-level input current
VI = 2.4 V
20
µA
IIL
Low-level input current
VI = 0.4 V
–400
µA
VO = –7 V
–250
VO = 0
–150
IOS
Short-circuit output current
RL = 54 Ω, see Figure 10
1.5
(4)
1.5
-1
(1)
(2)
(3)
(4)
(5)
(6)
Supply current (total package)
No load
V
±0.2
V
+3
V
±0.2
V
1
VO = –7 V
–0.8
250
VO = 12 V
ICC
5
VO = 12 V
VO = VCC
V
mA
mA
250
Outputs enabled
42
70
Outputs disabled
26
35
mA
The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and
outputs.
All typical values are at VCC = 5 V and TA = 25°C.
The minimum VOD2 with a 100-Ω load is either ½ VOD1 or 2 V, whichever is greater.
See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
Δ|VOD| and Δ|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level
to a low level.
This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not
apply for a combined driver and receiver terminal.
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7.5 Electrical Characteristics – Receiver
over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless
otherwise noted)
PARAMETER
VIT+
Positive-going input threshold voltage
MIN TYP (1)
TEST CONDITIONS
MAX
VO = 2.7 V, IO = –0.4 mA
UNIT
0.2
VIT–
Negative-going input threshold voltage
Vhys
Input hysteresis voltage (VIT+ – VIT–)
VIK
Enable Input clamp voltage
II = –18 mA
VOH
High-level output voltage
VID = 200 mV, IOH = –400 µA, see Figure 11
VOL
Low-level output voltage
VID = –200 mV, IOL = 8 mA, see Figure 11
0.45
V
IOZ
High-impedance-state output current
VO = 0.4 V to 2.4 V
±20
µA
II
Line input current
Other input = 0 V (3)
IIH
High-level enable input current
VIH = 2.7 V
20
µA
IIL
Low-level enable input current
VIL = 0.4 V
–100
µA
rI
Input resistance
VI = 12 V
IOS
Short-circuit output current
–85
mA
ICC
Supply current (total package)
(1)
(2)
(3)
VO = 0.5 V, IO = 8 mA
–0.2
V
(2)
V
50
mV
–1.5
V
VI = 12 V
1
VI = –7 V
–0.8
12
mA
kΩ
–15
No load
V
2.7
Outputs enabled
42
55
Outputs disabled
26
35
mA
All typical values are at VCC = 5 V, TA = 25°C.
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for commonmode input voltage and threshold voltage levels only.
This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.
7.6 Switching Characteristics – Driver
VCC = 5 V, RL = 110 Ω, TA = 25°C (unless otherwise noted)
TYP
MAX
td(OD)
Differential-output delay time
PARAMETER
RL = 54 Ω, see Figure 12
TEST CONDITIONS
MIN
15
22
UNIT
ns
tt(OD)
Differential-output transition time
RL = 54 Ω, see Figure 12
20
30
ns
tPZH
Output enable time to high level
See Figure 13
85
120
ns
tPZL
Output enable time to low level
See Figure 14
40
60
ns
tPHZ
Output disable time from high level
See Figure 13
150
250
ns
tPLZ
Output disable time from low level
See Figure 14
20
30
ns
7.7 Switching Characteristics – Receiver
VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low- to high-level output
tPHL
Propagation delay time, high- to low-level output
tPZH
Output enable time to high level
tPZL
Output enable time to low level
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
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VID = 0 to 3 V, see Figure 15
See Figure 16
See Figure 16
MIN
TYP
MAX
21
35
23
35
10
20
12
20
20
35
17
25
UNIT
ns
ns
ns
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SLLS101F – JULY 1985 – REVISED JANUARY 2015
7.8 Typical Characteristics
5
VCC = 5 V
TA = 25°C
4
3.5
3
2.5
2
1.5
1
4
3.5
3
2.5
2
1.5
1
0.5
0.5
0
0
–20
–40
–60
–80
–100
IOH – High-Level Output Current – mA
0
–120
Figure 1. Driver High-Level Output Voltage
vs
High-Level Output Current
3.5
120
3
2.5
2
1.5
1
0.5
0
10
20
30 40 50 60 70 80
IO – Output Current – mA
3
2.5
VCC = 5.25 V
2
VCC = 5 V
1.5
VCC = 4.75 V
1
0.5
0
–5
–10 –15 –20 –25 –30 –35 –40 –45 –50
IOH – High-Level Output Current – mA
Figure 4. Receiver High-Level Output Voltage
vs
High-Level Output Current
0.6
VCC = 5 V
VID = 200 mV
IOH = –440 µA
VOL – Low-Level Output Voltage – V
VOL
4
4
3.5
0
90 100
5
4.5
VID = 0.2 V
TA = 25°C
4.5
VOH – High-Level Output Voltage – V
VOH
VOD – Differential Output Voltage – V
VOD
20
40
60
80
100
IOL – Low-Level Output Current – mA
5
VCC = 5 V
TA = 25°C
Figure 3. Driver Differential Output Voltage
vs
Output Current
VOH – High-Level Output Voltage – V
VOH
0
Figure 2. Driver Low-Level Output Voltage
vs
Low-Level Output Current
4
0
VCC = 5 V
TA = 25°C
4.5
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VOH
5
4.5
3.5
3
2.5
2
1.5
1
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0.5
0
–40
0
–20
0
20
40
60
80
100
120
0
Only the 0°C to 70°C portion of the curve applies to the
SN75176B device.
Figure 5. Receiver High-Level Output Voltage
vs
Free-Air Temperature
5
10
15
20
25
30
IOL – Low-Level Output Current – mA
TA – Free-Air Temperature – °C
Only the 0°C to 70°C portion of the curve applies to the
SN75176B device.
Figure 6. Receiver Low-Level Output Voltage
vs
Low-Level Output Current
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Typical Characteristics (continued)
5
0.5
VCC = 5 V
VID = –200 mV
IOL = 8 mA
0.4
0.3
0.2
VCC = 5.25 V
VCC = 5 V
3
VCC = 4.75 V
2
1
0.1
0
–40
VID = 0.2 V
Load = 8 kΩ to GND
TA = 25°C
4
VO – Output Voltage – V
VO
VOL – Low-Level Output Voltage – V
VOL
0.6
0
–20
0
20
40
60
80
100
0
120
0.5
1.5
2
2.5
3
Figure 8. Receiver Output Voltage
vs
Enable Voltage
Figure 7. Receiver Low-Level Output Voltage
vs
Free-Air Temperature
6
VID = –0.2 V
Load = 1 kΩ to VCC
TA = 25°C
VCC = 5.25 V
5
VO – Output Voltage – V
VO
1
VI – Enable Voltage – V
TA – Free-Air Temperature – °C
VCC = 4.75 V
VCC = 5 V
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
VI – Enable Voltage – V
Figure 9. Receiver Output Voltage
vs
Enable Voltage
8
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SLLS101F – JULY 1985 – REVISED JANUARY 2015
8 Parameter Measurement Information
RL
2
VOD2
RL
2
VOC
Figure 10. Driver VOD and VOC
ID
VOH
VOL
+IOL
–IOH
Figure 11. Receiver VOH and VOL
3V
Input
Generator
(see Note B)
RL = 54 Ω
CL = 50 pF
(see Note A)
1.5 V
0V
td(OD)
td(OD)
Output
50 Ω
1.5 V
Output
3V
50%
10%
90%
tt(OD)
TEST CIRCUIT
≈2.5 V
50%
10%
≈–2.5 V
tt(OD)
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 12. Driver Test Circuit and Voltage Waveforms
Output
S1
3V
Input
1.5 V
1.5 V
0 V or 3 V
0V
CL = 50 pF
(see Note A)
Generator
(see Note B)
0.5 V
tPZH
RL = 110 Ω
VOH
Output
50 Ω
TEST CIRCUIT
2.3 V
tPHZ
Voff ≈0 V
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 13. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
5V
3V
S1
RL = 110 Ω
Input
1.5 V
1.5 V
Output
0V
3 V or 0 V
CL = 50 pF
(see Note A)
Generator
(see Note B)
tPLZ
tPZL
5V
0.5 V
50 Ω
2.3 V
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 14. Driver Test Circuit and Voltage Waveforms
3V
Input
Generator
(see Note B)
1.5 V
1.5 V
Output
51 Ω
1.5 V
CL = 15 pF
(see Note A)
0V
tPLH
tPHL
VOH
Output
0V
1.3 V
1.3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 15. Receiver Test Circuit and Voltage Waveforms
10
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Parameter Measurement Information (continued)
S1
1.5 V
2 kΩ
–1.5 V
S2
5V
CL = 15 pF
(see Note A)
Generator
(see Note B)
1N916 or Equivalent
5 kΩ
50 Ω
S3
TEST CIRCUIT
3V
Input
3V
Input
1.5 V
0V
tPZH
S1 to 1.5 V
S2 Open
S3 Closed
1.5 V
S1 to –1.5 V
0 V S2 Closed
S3 Open
tPZL
VOH
≈4.5 V
1.5 V
Output
Output
0V
1.5 V
VOL
3V
1.5 V
Input
3V
S1 to 1.5 V
S2 Closed
S3 Closed
Input
S1 to –1.5 V
S2 Closed
S3 Closed
1.5 V
0V
tPHZ
0V
tPLZ
VOH
0.5 V
Output
≈1.3 V
Output
0.5 V
≈1.3 V
VOL
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 16. Receiver Test Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional data
communication on multipoint bus transmission lines. They are designed for balanced transmission lines and meet
ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27.
The SN65176B and SN75176B devices combine a 3-state differential line driver and a differential input line
receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, that can be connected together externally to function as a direction control. The
driver differential outputs and the receiver differential inputs are connected internally to form differential
input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or
VCC = 0. These ports feature wide positive and negative common-mode voltage ranges, making the device
suitable for party-line applications.
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative
current limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to
occur at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12
kΩ, an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B devices can be used in transmission-line applications employing the SN75172
and SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
9.2 Functional Block Diagram
3
DE
4
D
2
RE
6
A
1
7
R
Bus
B
9.3 Feature Description
9.3.1 Driver
The driver converts a TTL logic signal level to RS-422 and RS-485 compliant differential output. The TTL logic
input, DE pin, can be used to turn the driver on and off.
Table 1. Driver Function Table (1)
(1)
12
INPUT
D
ENABLE
DE
H
H
L
X
DIFFERENTIAL OUTPUTS
A
B
H
L
H
L
H
L
Z
Z
H = high level,
L = low level,
X = irrelevant,
Z = high impedance (off)
Submit Documentation Feedback
Copyright © 1985–2015, Texas Instruments Incorporated
Product Folder Links: SN65176B SN75176B
SN65176B, SN75176B
www.ti.com
SLLS101F – JULY 1985 – REVISED JANUARY 2015
9.3.2 Receiver
The receiver converts a RS-422 or RS-485 differential input voltage to a TTL logic level output. The TTL logic
input, RE pin, can be used to turn the receiver logic output on and off.
Table 2. Receiver Function Table (1)
(1)
DIFFERENTIAL INPUTS
A–B
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
L
H
–0.2 V < VID < 0.2 V
L
U
VID ≤ –0.2 V
L
L
X
H
Z
Open
L
U
H = high level,
L = low level,
U = unknown,
Z = high impedance (off)
9.4 Device Functional Modes
9.4.1 Device Powered
Both the driver and receiver can be individually enabled or disabled in any combination. DE and RE can be
connected together for a single port direction control bit.
9.4.2 Device Unpowered
The driver differential outputs and the receiver differential inputs are connected internally to form differential
input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or
VCC = 0.
9.4.3 Symbol Cross Reference
Table 3. Symbol Equivalents
DATA SHEET
PARAMETER
TIA/EIA-422-B
TIA/EIA-485-A
Voa, Vob
VO
Voa, Vob
|VOD1|
Vo
Vo
|VOD2|
Vt ®L = 100 Ω)
Vt ®L = 54 Ω)
Vt (test termination
measurement 2)
|VOD3|
∆|VOD|
| |Vt| – |Vt| |
| |Vt – |Vt| |
VOC
|Vos|
|Vos|
∆|VOC|
|Vos – Vos|
|Vos – Vos|
IOS
|Isa|, |Isb|
IO
|Ixa|, |Ixb|
Iia, Iib
Copyright © 1985–2015, Texas Instruments Incorporated
Product Folder Links: SN65176B SN75176B
Submit Documentation Feedback
13
SN65176B, SN75176B
SLLS101F – JULY 1985 – REVISED JANUARY 2015
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The device can be used in RS-485 and RS-422 physical layer communications.
10.2 Typical Application
SN65176B
SN75176B
SN65176B
SN75176B
RT
RT
Up to 32
Transceivers
The line should be terminated at both ends in its characteristic impedance ®T = ZO). Stub lengths off the main line
should be kept as short as possible.
Figure 17. Typical RS-485 Application Circuit
10.2.1 Design Requirements
• 5-V power source
• RS-485 bus operating at 10 Mbps or less
• Connector that ensures the correct polarity for port pins
• External fail safe implementation
10.2.2 Detailed Design Procedure
• Place the device close to bus connector to keep traces (stub) short to prevent adding reflections to the bus
line
• If desired, add external fail-safe biasing to ensure +200 mV on the A-B port.
14
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Copyright © 1985–2015, Texas Instruments Incorporated
Product Folder Links: SN65176B SN75176B
SN65176B, SN75176B
www.ti.com
SLLS101F – JULY 1985 – REVISED JANUARY 2015
Typical Application (continued)
10.2.3 Application Curves
Figure 18. Eye Diagram for 10-Mbits/s over 100 feet of standard CAT-5E cable
120-Ω Termination at both ends. Scale is 1V per division and 25nS per division
10.3 System Examples
EQUIVALENT OF EACH INPUT
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
VCC
VCC
VCC
85 Ω
NOM
R(eq)
16.8 kΩ
NOM
Input
960 Ω
NOM
960 Ω
NOM
Output
GND
Driver input: R(eq) = 3 kΩ NOM
Enable inputs: R(eq )= 8 kΩ NOM
R(eq) = Equivalent Resistor
Input/Output
Port
Figure 19. Schematics of Inputs and Outputs
Copyright © 1985–2015, Texas Instruments Incorporated
Product Folder Links: SN65176B SN75176B
Submit Documentation Feedback
15
SN65176B, SN75176B
SLLS101F – JULY 1985 – REVISED JANUARY 2015
www.ti.com
11 Power Supply Recommendations
Power supply should be 5V with a tolerance less than 10%
12 Layout
12.1 Layout Guidelines
Traces from device pins A and B to connector must be short and capable of 250 mA maximum current.
12.2 Layout Example
GND
TTL Logic
1 R
TTL Logic
2 RE
1.5 μF
VCC 8
5V
B
B 7
Connector
TTL Logic
3 DE
TTL Logic
4 D
A 6
GND 5
A
GND
Layout Diagram
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65176B
Click here
Click here
Click here
Click here
Click here
SN75176B
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
Submit Documentation Feedback
Copyright © 1985–2015, Texas Instruments Incorporated
Product Folder Links: SN65176B SN75176B
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65176BD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
65176B
SN65176BDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
65176B
SN65176BDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
65176B
SN65176BDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
65176B
SN65176BDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
65176B
SN65176BP
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 105
SN65176BP
SN75176BD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
75176B
SN75176BDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
75176B
SN75176BDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
75176B
SN75176BDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
75176B
SN75176BDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
75176B
SN75176BDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
75176B
SN75176BP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN75176BP
SN75176BPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN75176BP
SN75176BPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
A176B
SN75176BPSRG4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
A176B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65176BDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65176BDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN75176BDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN75176BDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65176BDR
SOIC
D
8
2500
340.5
338.1
20.6
SN65176BDRG4
SOIC
D
8
2500
340.5
338.1
20.6
SN75176BDR
SOIC
D
8
2500
340.5
338.1
20.6
SN75176BDRG4
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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