Texas Instruments | TVB1440 4-Channel Video Re-Driver with Equalization (Rev. A) | Datasheet | Texas Instruments TVB1440 4-Channel Video Re-Driver with Equalization (Rev. A) Datasheet

Texas Instruments TVB1440 4-Channel Video Re-Driver with Equalization (Rev. A) Datasheet
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TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
TVB1440 4-Channel Video Re-Driver with Equalization
ECCN: 3E991
1 Features
3 Description
•
TVB1440 is a 4 channel re-driver signal conditioner
for TV applications allowing signal integrity between
TV chipset and TCON boards. I2C control provides
the wide ranges of flexibility to configure the device
for optimal signal conditioning so that video data link
between a source and sink can achieve high fidelity.
TVB1440 allows larger distance between a video
source and sink device through its excellent jitter
cleaning capability.
Compatible with TV Aggregated Video Signaling
Electricals
Compatible to FPD Link 2 Interface
Suited for Digital TV Chipset and TCON Boards
Quad Channel Re-Driver Supporting Data Rates
from 600 Mbps to 5 Gbps
3.3 V and 1.1 V Supply for Low Power Operation
175 mW Active Power Consumption for 4 Lane
Operation
2 mW Shutdown Power
Highly Configurable Input Equalization with 8
Control Settings
– 0 dB to 15 dB
4 Pre-Emphasis Control Settings
– 0, 3, 6 and 9 dB
4 Output Voltage Swing Control Settings
– 350, 500, 700 and 1000 mV
I2C Control to Configure the Device for Optimum
Performance
Extended Temperature Range of -40°C to 85°C
2 kV HBM and 500 V CDM ESD Protection
48-pin QFN 7 mm x 7 mm package.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
The TVB1440 is optimized for power conscience
applications. Apart from its low active power,
TVB1440 contains activity detection circuitry on the
data link input that transitions to a low-power output
disable mode in the absence of a valid input signal.
This activity detect circuit can be disabled if desired.
The device also has a shutdown mode when
exercised results in 2mW.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
It has selectable control for receive equalization
accessible through I2C to compensate for large trace
or cable loss at its input resulting improved eye at the
output signals. Transmitter in each channel has 4
levels of pre-emphasis and 4 levels of output voltage
swing settings which enable optimum video signal
performance from the TVB1440 to downstream
receiver.
TVB1440
Digital Television
Camera
Video Interfaces Requiring Large Throughputs
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematics
Display Sink
TVB1440
TVB1440
TVB1440
TVB1440
D1
Driver
TVB1440
C1
CH2
TVB1440
B1
EQ
SoC
A1
TVB1440
TVB1440
D1
Driver
TVB1440
C1
CH1
Driver
B1
EQ
CH0
A1
Display Source
EQ
TCON
I2C
EQ
CH3
Driver
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ECCN: 3E991
TVB1440
SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
5
6
7
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3
8.4
8.5
8.6
9
Feature Description................................................... 9
Device Functional Modes.......................................... 9
Programming............................................................. 9
Register Maps ......................................................... 13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
10 Power Supply Recommendations ..................... 19
10.1 Power-Up Sequence ............................................. 19
10.2 Power-Down Sequence ........................................ 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Export Control Notice............................................
Glossary ................................................................
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
5 Revision History
Changes from Original (November 2014) to Revision A
•
2
Page
Changed text in the Package Specific section From: "The TVB1440 package has a 5.6 mm x 5.6 mm thermal pad."
To: "The TVB1440 package has a 4.1 mm x 4.1 mm thermal pad.".................................................................................... 21
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SLASE51A – NOVEMBER 2014 – REVISED NOVEMBER 2014
6 Pin Configuration and Functions
VDD
RSVD3
OUT0n
21
VDD
IN1p
41
20
OUT1p
IN1n
42
19
OUT1n
VDD
43
18
GND
IN2p
44
17
OUT2p
IN2n
45
16
OUT2n
NC
46
15
VDD
IN3p
47
14
OUT3p
IN3n
48
1
3
4
5
6
7
8
9
13
12
OUT3n
2
26 25
24
RSVD2
RSVD1
10 11
GND
VDD
30 29 28 27
EN
22
40
TEST2
RSVD4
39
NC
TEST1
TEST3
IN0n
NC
GND
OUT0p
VDD
TEST4
23
SCL_CTL
VDD
38
SDA_CTL
TEST5
IN0p
ADDR
RSTN
36 35 34 33 32 31
37
VDD
TEST6
VDD
VCC
VCC
VQFN 0.5 mm Pitch
RGZ 48 Pin
Top View
Pin Functions
PIN
SIGNAL
NO.
DESCRIPTION
I/O
DATA LANES PINS
IN0p, IN0n
38, 39
IN1p, IN1n
41, 42
IN2p, IN2n
44, 45
IN3p, IN3n
47, 48
OUT0p, OUT0n
23, 22
OUT1p, OUT1n
20, 19
OUT2p, OUT2n
17, 16
OUT3p, OUT3n
14, 13
Lane 0 Differential Input
Input
(100Ω diff)
Lane 1 Differential Input
Lane 2 Differential Input
Lane 3 Differential Input
Lane 0 Differential Output
Output
(100Ω diff)
Lane 1 Differential Output
Lane 2 Differential Output
Lane 3 Differential Output
CONTROL PINS
ADDR
3
3-level Input
EN
26
I
NC
7, 40, 46
I2C Target Address Select.
Device Enable. This input incorporates internal pullup of 200 kΩ.
No Connect. These terminals may be left un-connected, or connect to GND.
RSTN
35
I
Active Low Device Reset. This is 1.1V input. This input includes a 150kΩ resistor to the VDDD core
supply. An external capacitor to GND is recommended on the RSTN input to provide a power-up delay.
This signal is used to place the TVB1440 into Shutdown mode for the lowest power consumption. When
the RSTN input is asserted, all outputs are high-impedance, and inputs are ignored; all I2C registers are
reset to their default values. At power up, the RSTN input must not be de-asserted until the VCC and VDD
supplies have reached at least the minimum recommended supply voltage level.
RSVD1
10
I
Reserved pins. Please connect the pin to GND through 1K resistor.
RSVD2
11
I
Reserved pins. Please connect the pin to VCC through 1K resistor.
RSVD3
27
I
Reserved pins. Please connect the pin to VCC through 1K resistor.
RSVD4
28
I
Reserved pins. Please connect the pin to GND through 1K resistor.
SCL_CTL
SDA_CTL
4
5
I/O
TEST1-6
8, 9, 29, 30,
33, 34
Bidirectional I2C interface to configure TVB1440. This interface is active independent of EN input but
inactive when RSTN is low.
Test Outputs. Do not connect.
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Pin Functions (continued)
PIN
SIGNAL
NO.
DESCRIPTION
I/O
SUPPLY AND GROUND PINS
GND
18, 24, 31,
PAD
Ground. Reference GND connections include the device package exposed thermal pad.
VDD
2, 6, 12, 15,
21, 25, 32,
37, 43
Low voltage supply for analog and digital core. Nominally 1.1V
VCC
1, 36
3.3V Supply
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Voltage range
(1)
(1)
MIN
MAX
VCC
–0.3
4
VDD
–0.3
1.3
HS Link I/O (OUTx, INx) Differential Voltage
–0.3
1.3
RSTN
–0.3
1.3
SCL_CTL, SDA_CTL, ADDR, EN
–0.3
4
UNIT
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN
MAX
UNIT
-65
150
·C
Human body model (HBM) (1)
–2000
2000
Charged-device model (CDM) (2)
–500
500
TSTG
Storage temperature range
Electrostatic
discharge
(1)
(2)
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
VCC
Supply Voltage, IO
3
3.6
V
VDD
Supply Voltage, CORE
1
1.26
V
VIH
High-level input voltage for ADDR, EN
1.9
3.6
V
VIL
Low-level input voltage for ADDR, EN
0
0.8
V
VIH,RSTN
High-level input voltage for RSTN (typical hysteresis of 80mV)
VIL,RSTN
Low-level input voltage for RSTN (typical hysteresis of 80mV)
TA
Operating free-air temperature
fscl
I2C CK frequency at SCL_CTL (standard I2C mode (1))
(1)
4
0.75
V
0.3
0
V
85
°C
100
kHz
The local interface through SCL_CTL and SDA_CTL should follow standard mode I2C specifications
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7.4 Thermal Information
THERMAL METRIC (1)
TVB1440
RθJA
Junction-to-ambient thermal resistance
35.1
RθJC(top)
Junction-to-case (top) thermal resistance
21.5
RθJB
Junction-to-board thermal resistance
11.7
ψJT
Junction-to-top characterization parameter
1.2
ψJB
Junction-to-board characterization parameter
11.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.7
(1)
UNIT
RGZ (48 Pin)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
(1)
TYP
MAX
UNIT
ICC
Supply current 4 lanes operation
130
230
mA
ISTDN
Shutdown supply current (1)
1.5
3
mA
IOD
Squelch (output disable) supply current
35
50
mA
VOD0
238
340
442
VOD1
357
510
663
484
690
897
700
1000
1300
VOD2
Output differential voltage swing
VOD3
PE0
0
PE1
3
Output pre-emphasis
PE2
dB
6
PE3
9
ROUT
Driver output impedance
I(TXSHORT)
Output pins short circuit current limit
V(SQUELCH)
Squelch threshold voltage for input signals (default)
(1)
mVpp
Ω
50
50
80
mA
mVpp
Values are VDD supply measurements; VCC supply measurements are 5 mA (typical) and 8 mA (max), with zero current in shutdown
mode.
7.6 Timing Requirements
MIN
tramp1
Time VDD must stable before VCC is applied
tramp2
tramp3
TYP
MAX
UNIT
10
µS
Time RSTN must remain asserted until VCC/VDD voltage has reached minimum
recommended operation
100
µS
Time device will be available for operation after a valid reset
400
mS
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7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
300
UNIT
tPD
Propagation delay time
tsk1
Intra-pair output skew (Figure 1)
20
ps
tsk2
Inter-pair output skew (Figure 1)
100
ps
Δtjit
Total peak-to-peak residual jitter
VOD0; PE0; EQ = 8dB; clean source; minimum input and output cabling; PRBS7 data
pattern.
15
ps
tsq_enter
Squelch entry time
Time from a loss of valid input signal to ML output off
120
µS
tsq_exit
Squelch exit time
Time from valid input signal available while in squelch mode to ML outputs on
1
µS
10
ps
Figure 1. Output Skew Definitions
6
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7.8 Typical Characteristics
23
10
22
Total Output Jitter (ps) (pk-pk)
12
8
Gain (Hz)
6
4
2
0
-2
6 dB Setting
10 dB Setting
15 dB Setting
-4
-6
10M
21
20
19
18
17
16
15
14
100M
1G
Frequency (Hz)
10G
0
D001
20
40
60
80
Total Input Jitter (ps) (pk-pk)
100
120
D002
Figure 2. Typical EQ Gain Curves (simulations)
Figure 3. Jitter Performance with Optimal EQ Settings
Figure 4. 3.75-Gbps Input With 20 Inch Trace
Figure 5. 3.75-Gbps Output with 20 Inch Input Trace and
8-dB EQ Setting
Figure 6. 5-Gbps Input with 20 Inches Trace
Figure 7. 5-Gbps Output with 20 Inch Input Trace and
13-dB EQ Setting
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8 Detailed Description
8.1 Overview
TVB1440 is a 4 channel HS re-driver signal conditioner for TV applications. I2C control provides the wide ranges
of flexibility to configure the device for optimal signal conditioning so that video data link between a source and
sink can achieve high fidelity. TVB1440 allows larger distance between a Chipset and TCON boards through its
excellent jitter cleaning capability.
The TVB1440 is optimized for power conscience applications. Apart from its low active power, TVB1440 contains
activity detection circuitry on the data link input that transitions to a low-power output disable mode in the
absence of a valid input signal. This activity detect circuit can be disabled if desired. The device also has a
shutdown mode when exercised results in 2 mW.
The TVB1440 receiver and driver provide input and output common mode voltage bias. It is required that both
receive and transmit end of the device is ac coupled in application use cases. Suggested value for the ac
coupling capacitors is 75-200 nF.
8.2 Functional Block Diagram
VDD
ADDR
ADDR
RRST=150k
VCC
VDD
GND
RSTN
EN
RESET
EN
REN=200k
VIterm
VBIAS
VCC
50
50
50
IN0p
EQ
50
OUT0p
Driver
IN0n
OUT0n
VIterm
50
VBIAS
50
50
50
IN1p
OUT1p
Driver
EQ
IN1n
OUT1n
VIterm
50
VBIAS
50
50
50
IN2p
EQ
IN2n
OUT2p
Driver
VIterm
50
50
50
IN3p
50
OUT3p
EQ
Driver
IN3n
OUT3n
ADDR
SCL_ CTL
SDA_ CTL
OUT2n
VBIAS
EQ_CTL
I2 C
Target
PE_CTL
CTRL
VOD_CTL
EN
8
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8.3 Feature Description
8.3.1 Equalization
TVB1440 provides flexible continuous time linear equalization (CTLE) to compensate for large trace or cable loss
at its input resulting improved eye at the output signals. It has selectable control for receive equalization
accessible through I2C.
8.3.2 Configurable Output
Transmitter in each channel has 4 levels of pre-emphasis and 4 levels of output voltage swing settings which
enable optimum video signal performance from the TVB1440 to downstream receiver.
8.3.3 Squelch
TVB1440 has active Squelch feature that allows automatic shutdown of output drivers when it does not have
valid input signal. The feature can be disabled through I2C if not desired.
8.4 Device Functional Modes
8.4.1 Active Mode
Normal operation mode. The data lanes of TVB1440 work normally.
8.4.2 Shutdown Mode
Device is in lowest power mode. This mode is invoked by de-asserting RSTN or EN low.
8.4.3 Squelch Mode
The device does not have valid input signal. Output drivers are turned off.
8.5 Programming
8.5.1 Local I2C Interface
It is required to use the TVB1440’s local I2C interface to configure the TVB1440’s receivers (IN[3:0]P/N) and
transmitters (OUT[3:0]P/N). The TVB1440’s internal registers are accessed through the SCL_CTL pin and
SDA_CTL pin. The 7-bit I2C slave address of the TVB1440 is determined by the ADDR pin.
Table 1. TVB1440 I2C Slave Address Options
ADDR
7-BIT I2C SLAVE ADDRESS
READ SLAVE ADDRESS
WRITE SLAVE ADDRESS
Low (VIL)
7’b0101100
‘h59
‘h58
VCC/2 (VIM)
7’b0101101
‘h5B
‘h5A
High (VIH)
7’b0101110
‘h5D
‘h5C
Before adjusting the TVB1440’s registers, a writing a zero to bit 2 of address 04h is required to enable the
receiver and transmitter adjustments.
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8.5.2 Receiver (IN[3:0]P/N) Adjustments
8.5.2.1 Equalization Level
It is recommended to use the TVB1440 local I2C interface to configure the TVB1440 receiver equalization level.
Software should then enable equalization control by writing a one to EQ_I2C_ENABLE bit (bit 7 at address 05h).
After EQ_I2C_ENABLE is set, then software can program the equalization for each lane (IN[3:0]) to the
appropriate value. Refer to Table 2 for details on equalization settings for each lane.
Table 2. TVB1440 Equalization Levels
Address
Bits(s)
04h
2
Description
Access
Receiver and transmitter adjustment.
0 – configure receiver and transmitter using I2C (required)
1 – reserved (default)
RW
EQ_LEVEL_LANE0. This field selects the EQ gain level for Lane 0 (IN0P/N).
000 – 0 dB
001 – 2 dB (3.75Gbps); 2.5 dB (5Gbps)
010 – 3.5 dB (3.75Gbps); 5 dB (5Gbps)
011 – 5 dB (3.75Gbps); 6 dB (5Gbps)
100 – 6.5 dB (3.75Gbps); 8 dB (5Gbps)
101 – 8 dB (3.75Gbps); 11 dB (5Gbps)
110 – 9.5 dB (3.75Gbps); 13 dB (5Gbps)
111 – 12 dB (3.75Gbps); 15 dB (5Gbps)
RW
EQ_I2C_ENABLE. This field allows EQ control through I2C
0 – reserved (default)
1 – EQ level is set by I2C (required)
RW
05h
2:0
05h
7
07h
2:0
EQ_LEVEL_LANE1. This field selects the EQ gain level for Lane 1 (IN1P/N. Bit definition identical to
that of EQ_LEVEL_LANE0.
RW
09h
2:0
EQ_LEVEL_LANE2. This field selects the EQ gain level for Lane 2 (IN2P/N). Bit definition identical
to that of EQ_LEVEL_LANE0.
RW
0Bh
2:0
EQ_LEVEL_LANE3. This field selects the EQ gain level for Lane 3 (IN3P/N. Bit definition identical to
that of EQ_LEVEL_LANE0.
RW
8.5.2.2 Squelch Level
The TVB1440 squelch level defaults to 80mVpp. If it is necessary to adjust the squelch level, it can be done by
changing the SQUELCH_SENSITIVITY register located in the TVB1440’s Local I2C register space.
Table 3. Squelch Sensitivity Levels
Address
Bits(s)
5:4
03h
3
10
Description
Access
SQUELCH_SENSITIVITY. Main link squelch sensitivity is selected by this field, and determines the
transitions to and from the Output Disable mode.
00 – Main Link IN0P/N squelch detection threshold is set to 40mVpp.
01 – Main Link IN0P/N squelch detection threshold is set to 80mVpp. (Default)
10 – Main Link IN0P/N squelch detection threshold is set to 160mVpp.
11 – Main Link IN0P/N squelch detection threshold is set to 250mVpp.
RW
SQUELCH_ENABLE.
0 – Main Link IN0P/N squelch detection is enabled (default)
1 – Main Link IN0P/N squelch detection is disabled.
RW
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8.5.3 Main Link Output [OUT[3:0]P/N] Adjustments
The TVB1440 Main link outputs (OUT[3:0]) must be set in link address space by following specified I2C access
method.
8.5.3.1 LINK Address Space
Access to and from the TVB1440 LINK address space is indirectly addressable through the local I2C registers as
illustrated in the Figure 8.
TVB1440's Local I2C
Address Space
1Ch
Local I2C
Acceses
TVB1440's Link
Address Space
LINK_ADDR_HIGH
1Dh
LINK_ADDR_MID
1Eh
LINK_ADDR_LOW
1Fh
LINK_DATA
20-bit LINK Register
Data Read/Write
Figure 8. Accessing TVB1440 LINK Registers
The configuration of these registers can be performed through the local I2C interface, where three registers (from
1Ch to 1Eh) are used as the address to the LINK register and another one (1Fh) as a data to be read/written.
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8.5.4 Example Script
The script below is for a Total Phase Aardvark I2C controller. Details on the Total Phase Aardvark I2C controller
can be obtained from the Total Phase website. This example is for a 5.0 Gbps data rate with 4 active lanes.
space
<aardvark>
<configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0"/>
<i2c_bitrate khz="100"/>
space
======Program the device=====
<i2c_write addr="0x2D" count="1" radix="16">04 00</i2c_write> />
space
======Program Link Bandwidth Settings to 5Gbps======LINK 00100h=====
<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1E 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1F 14</i2c_write> />
space
space
======Program Num of Lanes to 4.s======LINK 00101h=====
<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1E 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1F 04</i2c_write> />
space
======Program VOD L1 and Pre-Emphasis L0 for Lane 0======LINK 00103h=====
<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1E 03</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />
space
======Program VOD L1 and Pre-Emphasis L0 for Lane 1======LINK 00104h=====
<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1E 04</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />
space
======Program VOD L1 and Pre-Emphasis L0 for Lane 2======LINK 00105h=====
<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1E 05</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />
space
======Program VOD L1 and Pre-Emphasis L0 for Lane 3======LINK 00106h=====
<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1E 06</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />
space
======Set Power Mode to Normal======LINK 00600h=====
<i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1D 06</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1E 00</i2c_write> />
<i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> />
space
=====May want to adjust Squelch Level===
<i2c_write addr="0x2D" count="1" radix="16">03 10</i2c_write> />
space
=====Enable EQ===
<i2c_write addr="0x2D" count="1" radix="16">05 80</i2c_write> />
space
=====Set EQ level to 11dB(5Gbps) for lane 0===
<i2c_write addr="0x2D" count="1" radix="16">05 85</i2c_write> />
space
=====Set EQ level to 11dB(5Gbps) for lane 1===
<i2c_write addr="0x2D" count="1" radix="16">07 05</i2c_write> />
space
=====Set EQ level to 11dB(5Gbps) for lane 2===
<i2c_write addr="0x2D" count="1" radix="16">09 05</i2c_write> />
space
=====Set EQ level to 11dB(5Gbps) for lane 3===
<i2c_write addr="0x2D" count="1" radix="16">0B 05</i2c_write> />
</aardvark>
12
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8.6 Register Maps
Table 4. TVB1440 LINK Registers
LINK Address
00100h
00101h
00103h
00104h
00105h
00106h
00600h
NAME
LINK_BW_SET
LANE_COUNT_SET
LANE0_SET
LANE1_SET
LANE2_SET
LANE3_SET
SET_POWER
Value Written
Value Read
06h
00h
<1.6Gbps per lane
Description
0Ah
01h
1.6-2.7Gbps per lane
14h
02h
2.7-5.0Gbps per lane
00h
00h
All Lanes disabled
01h
01h
One lane enabled (OUT0).
02h
03h
Two lanes enabled (OUT[1:0]).
04h
0Fh
Four lanes enabled (OUT[3:0]).
00h
00h
VOD Level 0 and Pre-emphasis Level 0 for OUT0.
08h
04h
VOD Level 0 and Pre-emphasis Level 1 for OUT0.
10h
08h
VOD Level 0 and Pre-emphasis Level 2 for OUT0.
18h
0Ch
VOD Level 0 and Pre-emphasis Level 3 for OUT0.
01h
01h
VOD Level 1 and Pre-emphasis Level 0 for OUT0.
09h
05h
VOD Level 1 and Pre-emphasis Level 1 for OUT0.
11h
09h
VOD Level 1 and Pre-emphasis Level 2 for OUT0.
02h
02h
VOD Level 2 and Pre-emphasis Level 0 for OUT0.
0Ah
06h
VOD Level 2 and Pre-emphasis Level 1 for OUT0.
03h
03h
VOD Level 3 and Pre-emphasis Level 0 for OUT0
00h
00h
VOD Level 0 and Pre-emphasis Level 0 for OUT1.
08h
04h
VOD Level 0 and Pre-emphasis Level 1 for OUT1.
10h
08h
VOD Level 0 and Pre-emphasis Level 2 for OUT1.
18h
0Ch
VOD Level 0 and Pre-emphasis Level 3 for OUT1.
01h
01h
VOD Level 1 and Pre-emphasis Level 0 for OUT1.
09h
05h
VOD Level 1 and Pre-emphasis Level 1 for OUT1.
11h
09h
VOD Level 1 and Pre-emphasis Level 2 for OUT1.
02h
02h
VOD Level 2 and Pre-emphasis Level 0 for OUT1.
0Ah
06h
VOD Level 2 and Pre-emphasis Level 1 for OUT1.
03h
03h
VOD Level 3 and Pre-emphasis Level 0 for OUT1
00h
00h
VOD Level 0 and Pre-emphasis Level 0 for OUT2.
08h
04h
VOD Level 0 and Pre-emphasis Level 1 for OUT2.
10h
08h
VOD Level 0 and Pre-emphasis Level 2 for OUT2.
18h
0Ch
VOD Level 0 and Pre-emphasis Level 3 for OUT2.
01h
01h
VOD Level 1 and Pre-emphasis Level 0 for OUT2.
09h
05h
VOD Level 1 and Pre-emphasis Level 1 for OUT2.
11h
09h
VOD Level 1 and Pre-emphasis Level 2 for OUT2.
02h
02h
VOD Level 2 and Pre-emphasis Level 0 for OUT2.
0Ah
06h
VOD Level 2 and Pre-emphasis Level 1 for OUT2.
03h
03h
VOD Level 3 and Pre-emphasis Level 0 for OUT2
00h
00h
VOD Level 0 and Pre-emphasis Level 0 for OUT3.
08h
04h
VOD Level 0 and Pre-emphasis Level 1 for OUT3.
10h
08h
VOD Level 0 and Pre-emphasis Level 2 for OUT3.
18h
0Ch
VOD Level 0 and Pre-emphasis Level 3 for OUT3.
01h
01h
VOD Level 1 and Pre-emphasis Level 0 for OUT3.
09h
05h
VOD Level 1 and Pre-emphasis Level 1 for OUT3.
11h
09h
VOD Level 1 and Pre-emphasis Level 2 for OUT3.
02h
02h
VOD Level 2 and Pre-emphasis Level 0 for OUT3.
0Ah
06h
VOD Level 2 and Pre-emphasis Level 1 for OUT3.
03h
03h
VOD Level 3 and Pre-emphasis Level 0 for OUT3
01h
00h
Normal Mode
02h
01h
Power-Down mode.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
TVB1440 is a signal conditioner especially suited for equalizing channel loss due to traces and flexible cable
between digital TV chipset and TCON receiver.
9.1.1 Typical Application
TVB
1440
TVB
1440
TVB
1440
FPC Cable
TVB
1440
TVB
1440
TVB
1440
TVB
1440
TCON SOC
TVB
1440
TV Int - LVDS
De-aggregator
LVDS - TV
Interface
Aggregator
TV SOC
The device can be helpful improving eye diagram by placing it either end of the flexible cable in digital TV chipset
or TCON board or at the both. Figure 9 shows a typical application for TV interface.
Figure 9. Typical Application of TVB1440 in 4K2K Digital TV Interface
9.1.1.1 Design Requirements
Table 5. Design Parameters
PARAMETER
VALUE
VDD Supply
1.1 V
VCC Supply
3.3 V
TV Max Resolution Requirement
Pixel Clock (MHz)
1194
Horizontal Active (pixels)
3840
Vertical Active
2160
Color bit Depth (6bpc, 8bpc, 10bpc)
10 (30 bpp)
Refresh Rate
120 Hz
Panel Configuration (A or B)
B
Channel Requirements
Input Channel Insertion Loss
Up to 12 dB at 3.75 Gbps
Output Channel Insertion Loss
Up to 12 dB at 3.75 Gbps
Number of Lanes (1, 2, or 4)
4
TVB1440 Settings
14
Link Rate (Gbps)
3.75
RX EQ Setting (dB)
6.5 dB
TX VOD Setting (Level 0, 1, 2, or 3)
Level 3 (1000 mVpp)
TX Pre-Emphasis Setting (Level 0, 1, 2, or 3)
Level 0 (0 dB)
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9.1.1.2 Detailed Design Procedure
9.1.1.2.1 Common 4k2k TV Panel Configuration
A common 4k2k TV is broken into four 1920 x 1080 panels or four 960 x 2160 panels. For this particular
implementation, panel configuration B is assumed. It is also assumed that two TVB1440 are used for each panel
(one near SOC and one near TCON) for a total of eight TVB1440.
Configuration
ConfigurationAA
Configuration B
Figure 10. Common Panel Configurations
9.1.1.2.2 1Max Stream Rate
The maximum stream rate can be derived from the maximum TV resolutions pixel clock and color depth. For this
example, the maximum pixel clock is 1194 MHz. Because the TV is broken into 4 panels, the actual pixel clock
for each panel is 298.5 MHz.
Stream Bit Rate = PixelClock x bpp
Stream Bit Rate = 298.5 x 30
Stream Bit Rate = 8.955 Gbps.
9.1.1.2.3 Encoded Stream Rate
Most high-speed video standards are 8b10b encoded. Because of 8b10b encoding overhead, an additional 20%
must be added to the stream bit rate. On top of the 8b10b, there are some additional overhead due to
packetization before the 8b10b encode that also must be added to the stream bit rate. For example, a particular
video standard may define the actual coded stream rate by the following equation.
Encoded_Stream_Rate = #_of_Bytes_for_bpp x 8 x 1.25 x PixelClock
Encoded_Stream_Rate = #_of_Bytes_for_bpp x 8 x 1.25 x PixelClock
Encoded_Stream_Rate = 11.94Gbps.
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9.1.1.2.4 TVB1440 Configuration
The TVB1440 must be configured by the SOC using I2C. Because of the limited number of I2C address available
on the TVB1440, an I2C switch needs to be incorporated in order to configure each of the TVB1440. Figure 11
shows an example implement using the Texas Instruments TCA9546A 4-channel I2C switch.
TVB1440
I2C Address 0x58/59
TVB1440
I2C Address 0x5C/5D
TVB1440
I2C Address 0x58/59
TVB1440
I2C Address 0x5C/5D
TVB1440
I2C Address 0x58/59
TVB1440
I2C Address 0x5C/5D
TVB1440
I2C Address 0x58/59
TVB1440
I2C Address 0x5C/5D
I2C_BUS1
SCL
I2C_BUS2
SOC
SDA
I2C Switch
(TCA9546A)
I2C_BUS3
I2C_BUS4
TCA9546A I2C address options:
7'b1110XYZ where X = A2, Y= A1, Z = A0
Figure 11. Example I2C Switch Implementation
9.1.1.2.5 Receiver Equalization Setting
The TVB1440 has a receiver equalizer that is adjustable from 0dB to 15 dB at 5 Gbps. The common approach to
determine the proper equalizer setting is to measure the insertion loss of the channel at the input of the TVB1440
at the Nyquist frequency of the data rate (1.875 GHz for 3.75 Gbps and 2.5 GHz for 5 Gbps). For example, if the
input channel is 20 inches of trace with 4 mil width over FR4, the insertion loss at 3.75 Gbps would be -7.3 dB
and at 5 Gbps would be -9.1 dB. The register EQ_LEVEL_LANEx, where X = 0, 1, 2, or 3 should be
programmed to 3’b100 for a 3.75 Gbps data rate and should be programmed to 3’b101. The actual setting may
need to be adjusted based on the additional channel parasitics from package, vias, and connectors.
0
m1
Insertion Loss (dB)
-5
m2
-10
-15
-20
-25
-30
-35
0
1
2
3
4
5
6
Frequency (GHz)
7
8
9
10
m1 frequency = 1.876 GHz
IL = –7.346
m2 frequency = 2.500 GHz
IL = –9.185
Figure 12. Insertion Loss of 20 Inch FR4 Trace With 4-mil Width
16
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9.1.1.2.6 Transmitter Settings
The TVB1440’s transmitter controls have four settings for voltage swing and four settings for pre-emphasis. The
best transmitter setting to use is a function of the output channel insertion loss and the inputs eye requirement of
the device at end of the channel. For the case in which a TVB1440 is at the end of the channel, the output
channel’s insertion loss should not be greater than the receiver equalization of the TVB1440.
To specify the largest eye opening at the end of the channel, the best voltage swing setting should be either level
2 or level 3. It is also recommended to use either a pre-emphasis level of 0 dB or 3dB. The pre-emphasis setting
can be thought of as a way to reduce the amount receiver equalizer required by the device at end channel. For
example, a 3.5dB setting could allow for the receive equalization setting for the TVB1440 to be reduced from
12dB to 10dB. If necessary, these settings can be adjusted up or down in order to improve the eye opening at
the end of the channel.
9.1.1.2.7 RESET
The TVB1440 RSTN input gives control over the device reset and to place the device into shut-down mode.
When RSTN is low, all registers are reset to their default values, which means all HS Link ports are disable.
When the RSTN pin is released back to high, the device comes out of the shut-down mode. To turn on the HS
Link, it is necessary to provision the device registers through the local I2C_CTL interface.
It is critical to transition the RSTN input from a low to a high level after both VCC and VDD supply voltages have
reached the minimum recommended operating voltage. This is achieved by a control signal to the RSTN input, or
by an external capacitor connected between RSTN and GND. To insure that the TVB1440 is properly reset, the
RSTN pin must be de-asserted for at least 100 μs before being asserted.
The RSTN input includes a 150k resistor from the input to the VDD supply. An external capacitor connected
between RSTN and GND allows delaying the RSTN signal during power up. When implementing the external
capacitor the size of the external capacitor depends on the power up ramp of the VCC and VDD supplies; a
slower ramp-up results in a larger value external capacitor. Approximately 200 nF capacitor is a reasonable first
estimate for the size of the external capacitor for most applications.
Both RSTN implementations are shown in Figure 13.
VDD
GPO
RSTN
RSTN
C
150K
C
TVB1440
controller
TVB1440
Figure 13. (a) Reset Implementation Using a Capacitor, (b) Microprocessor Drives the Pin
Figure 14 shows a typical schematic implementation either in TV chipset or TCONS receiver board.
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VCC_3P3V
VCC_3P3V
R1
1K
r0402
5%
IN1P
IN1N
IN2P
IN2N
TVB1440_EN
36
35
34
33
32
31
30
29
28
27
26
25
VCC
RSTN
TEST6
TEST5
VDD
GND
TEST4
TEST3
RSVD4
RSVD3
EN
VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
VDD
IN0P
IN0N
NC2
IN1P
IN1N
VDD
IN2P
IN2N
NC3
IN3P
IN3N
TP
R3
10K (DNI)
r0402
5%
U1
TVB1440RGZ
GND
OUT0P
OUT0N
VDD
OUT1P
OUT1N
GND
OUT2P
OUT2N
VDD
OUT3P
OUT3N
24
23
22
21
20
19
18
17
16
15
14
13
OUT0P
OUT0N
OUT1P
OUT1N
VDD_1P1V
C2
0.1uF
OUT2P
OUT2N
OUT3P
OUT3N
C3
0.1uF
C4
0.1uF
C5
10uF
C6
0.1uF
C8
C7
0.01uF 0.01uF
VCC_3P3V
C9
10uF
C10
0.1uF
C11
0.1uF
1
2
3
4
5
6
7
8
9
10
11
12
IN3P
IN3N
TVB1440_RSTN
C1
0.2uF
TVB1440
IN0P
IN0N
R2
1K
r0402
5%
VCC
VDD
ADDR
SCL_CTL
SDA_CTL
VDD
NC1
TEST1
TEST2
RSVD1
RSVD2
VDD
RSTN must be
held low until
VCC and VDD are
active and
stable.
VCC_3P3V
VDD_1P1V
ADDR
SCL_CTL
SDA_CTL
C12
1uF
R4
1K
r0402
5%
R5
VCC_3P3V
1K
r0402
5%
Figure 14. Schematic Implementation of TVB1440
18
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10 Power Supply Recommendations
The following power-up and power-down sequences describe how the RSTN signal is applied to the TVB1440.
10.1 Power-Up Sequence
1. Apply VDD then VCC (recommended both less than 10-ms ramp time). VDD must be asserted first and
stable for greater than 10 μs before VCC is applied.
2. RSTN must remain asserted until VCC/VDD voltage has reached minimum recommended operation for more
than 100 μs.
3. De-assert RSTN (Note: This RSTN is a 1.1V interface and is internally connected to VDD through a 150-kΩ
resistor).
4. Device will be available for operation approximately 400 ms after a valid reset.
VCC
VDD
VCC/VDD
T > 10 µs
RSTN
T > 100 µs
Device
Available
T > 400 ms
Figure 15. Power-up Sequence
10.2 Power-Down Sequence
There is no power-down sequence required.
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11 Layout
11.1 Layout Guidelines
11.1.1 Differential Pairs
This section describes the layout recommendations for all the TVB1440 differential pairs: IN[3:0] and OUT[3:0].
• Must be designed with a differential impedance of 100 Ω ± 10% or 50-Ω single-ended impedance.
• In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each
pair should be separated by at least 5 times the signal trace width.
• Route all differential pairs on the same layer adjacent to a solid ground plane.
• Do not route differential pairs over any plane split.
• Adding test points causes impedance discontinuity and; therefore, negative impacts signal performance. If
test points are used, they should be placed in series and symmetrically. They must not be placed in a manner
that causes stub on the differential pair.
• Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥ 135 degrees. This minimizes any length mismatch causes by the bends; and therefore,
minimizes the impact bends have on EMI.
• Minimize the trace lengths of the differential pair traces. Longer trace lengths require very careful routing to
assure proper signal integrity.
• Keep intra-pair skew to a minimum in order to minimize EMI. There should be less than 5 mils difference
between a differential pair signal and its complement.
• Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. It is recommended to keep the vias
count to 2 or less.
11.1.2 Layout Example
Figure 16. TBV1440 Layout
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Layout Guidelines (continued)
11.1.3 Placement
• A 100-nF should be placed as close as possible on each VDD and VCC power pin.
• The 100-nF capacitors on the IN[3:0] and OUT[3:0] nets should be placed close to the connector.
• The ESD and EMI protection devices (if used) should also be placed as possible to the connector.
11.1.4 Package Specific
•
•
•
The TVB1440 package as a 0.5 mm pin pitch
The TVB1440 package has a 4.1 mm x 4.1 mm thermal pad. This thermal pad must be connected to ground
through a system of vias.
All vias under device, except for those connected to thermal pad, should be solder masked to avoid any
potential issues with thermal pad layouts.
11.1.5 Ground
It is recommended that only one board plane be used in the design. This provides the best image plane for
signal traces running above the plane. The thermal pad of the TVB1440 should be connected to this plane
through a system of vias.
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Dec-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
TVB1440RGZR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGZ
48
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
0 to 85
TVB1440
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TVB1440RGZR
Package Package Pins
Type Drawing
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
7.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.3
1.1
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TVB1440RGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
7 x 7, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048B
VQFN - 1 mm max height
SCALE 2.000
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
B
A
PIN 1 INDEX AREA
7.15
6.85
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
4.1 0.1
(0.2) TYP
44X 0.5
12
25
49
2X
5.5
SYMM
36
1
37
48
PIN 1 ID
(OPTIONAL)
EXPOSED
THERMAL PAD
24
13
SYMM
48X
0.30
0.18
0.1
C B A
0.05
48X
0.5
0.3
4218795/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGZ0048B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 4.1)
(1.115) TYP
(0.685)
TYP
48
48X (0.6)
37
1
36
48X (0.24)
(1.115)
TYP
44X (0.5)
SYMM
(0.685)
TYP
49
( 0.2) TYP
VIA
(6.8)
(R0.05)
TYP
25
12
13
24
SYMM
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218795/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.37)
TYP
48
37
48X (0.6)
1
36
48X (0.24)
44X (0.5)
(1.37)
TYP
SYMM
49
(R0.05) TYP
(6.8)
9X
( 1.17)
METAL
TYP
25
12
13
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4218795/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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