Texas Instruments | SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer (Rev. B) | Datasheet | Texas Instruments SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer (Rev. B) Datasheet

Texas Instruments SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer (Rev. B) Datasheet
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SN65EPT22
SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014
SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer
1 Features
3 Description
•
•
The SN65EPT22 is a low power dual LVTTL to
LVPECL translator device. The device includes
circuitry to maintain known logic HIGH level when
inputs are in open condition. The SN65EPT22 is
housed in an industry standard SOIC-8 package and
is also available in TSSOP-8 package option.
1
•
•
•
•
•
•
Dual 3.3V LVTTL to LVPECL Buffer
Operating Range
– LVPECL VCC = 3.0 V to 3.6 V With
GND = 0 V
Support for Clock Frequencies to 2.0 GHz (typ)
420 ps Typical Propagation Delay
Deterministic HIGH Output Value for Open Input
Conditions
Built-in Temperature Compensation
Drop in Compatible to MC100ELT23
PNP Single Ended Inputs for Minimal Loading
Device Information(1)
PART NUMBER
SN65EPT22
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90mm x 3.91mm
VSSOP (8)
3.00mm x 3.00mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
Data and Clock Transmission Over Backplane
Signaling Level Conversion
4 Simplified Schematic
VTERM = VCC - 2 V
Transmission Line
ZO
Rt ~
~ ZO
LVPECL
SN65EPT22
Transmission Line
ZO
Rt ~
~ ZO
VTERM = VCC - 2 V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65EPT22
SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
7.1 Absolute Maximum Ratings ....................................
7.2 Handling Ratings ......................................................
7.3 Power Dissipation Ratings ........................................
7.4 Thermal Information ..................................................
3
3
4
4
7.5
7.6
7.7
7.8
7.9
8
Key Attributes............................................................
TTL Input DC Characteristics ...................................
PECL Output DC Characteristics .............................
AC Characteristics ...................................................
Typical Characteristics ..............................................
4
4
5
5
7
Device and Documentation Support.................... 8
8.1 Trademarks ............................................................... 8
8.2 Electrostatic Discharge Caution ................................ 8
8.3 Glossary .................................................................... 8
9
Mechanical, Packaging, and Orderable
Information ............................................................. 8
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2010) to Revision B
Page
•
Deleted the Ordering Information table .................................................................................................................................. 1
•
Added the Device Information table ....................................................................................................................................... 1
•
Added the Simplified Schematic............................................................................................................................................. 1
•
Added the Handling Ratings .................................................................................................................................................. 3
•
Added the Device and Documentation Support and Mechanical, Packaging, and Orderable Information............................ 8
Changes from Original (November 2010) to Revision A
•
2
Page
Changed SN65EPT22 to EPT22 (2 places) in Ordering Information Table under Part Marking column ............................. 1
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SN65EPT22
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SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014
6 Pin Configuration and Functions
Top View
Q0 1
8 VCC
Q0 2
7 D0
LVPECL
LVTTL
Q1 3
6 D1
Q1 4
5 GND
Pin Functions
PIN
FUNCTION
D0, D1
LVTTL data inputs
Q0, Q 0, Q1, Q 1
LVPECL outputs
VCC
Positive supply
GND
Ground
7 Specifications
Absolute Maximum Ratings (1)
7.1
PARAMETER
CONDITION
MIN
Absolute supply voltage, VCC
GND = 0 and VI ≤ VCC
Absolute input voltage, VI
0
Supply voltage LVPEL
Output current
UNIT
6
V
6
V
3.3
V
Continuous
50
Surge
100
Operating temperature range
(1)
MAX
–40
mA
85
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
–4
4
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–2
2
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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3
SN65EPT22
SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014
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7.3 Power Dissipation Ratings
PACKAGE
CIRCUIT BOARD
MODEL
POWER RATING
TA < 25°C
(mW)
THERMAL RESISTANCE,
JUNCTION TO AMBIENT
NO AIRFLOW
DERATING FACTOR
TA > 25°C
(mW/°C)
POWER RATING
TA = 85°C
(mW)
D
DGK
Low-K
719
139
7
288
High-K
840
119
8
336
Low-K
469
213
5
188
High-K
527
189
5
211
7.4 Thermal Information
THERMAL METRIC (1)
D
DGK
8 PINS
8 PINS
RθJB
Junction-to-board thermal resistance
79
120
RθJC
Junction-to-case thermal resistance
98
74
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Key Attributes
CHARACTERISTICS
VALUE
Moisture sensitivity level
Lead free package
SOIC-8
Level 1
VSSOP-8
Flammability rating (Oxygen Index: 28 to 34)
Level 3
UL 94 V-0 at 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 latchup test
7.6 TTL Input DC Characteristics (1)
(VCC = 3.3 V, GND = 0, TA = –40°C to 85°C)
CHARACTERISTIC
CONDITION
UNIT
μA
100
μA
Input LOW current
VIN = 0.5 V
–0.6
mA
Input clamp voltage
IIN = –18 mA
VIN = 2.7 V
IIHH
Input HIGH current max
IIL
VIK
VIH
Input high voltage
VIL
Input low voltage
4
TYP MAX
VIN = VCC
Input HIGH current
(1)
MIN
20
IIH
–1
2.0
V
V
0.8
V
Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
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SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014
7.7 PECL Output DC Characteristics (1)
(VCC = 3.3 V; GND = 0.0V)
(2)
–40°C
CHARACTERISTIC
ICC
Power supply current
VOH
Output HIGH voltage
VOL
Output LOW voltage (3)
(1)
(2)
(3)
(3)
25°C
MIN
TYP
MAX
39
45
2155
2224
1355
1441
85°C
MIN
TYP
MAX
42
47
2405
2155
2224
1605
1355
1438
MAX
UNIT
MIN
TYP
45
50
mA
2405
2155
2224
2405
mV
1605
1355
1435
1605
mV
Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
Output parameters vary 1:1 with VCC
All loading with 50Ω to VCC –2.0V
7.8 AC Characteristics
(1)
(VCC = 3.0 V to 3.6 V; GND = 0 V) (2)
–40°C
CHARACTERISTIC
MIN
fMAX
Max switching frequency (3), see Figure 5
tPLH / tPHL
Propagation delay to differential output
TYP MAX
MIN
TYP
2.1
230
(4)
85°C
MAX
MIN
550
230
2.0
550
230
TYP
MAX
2.0
UNIT
GHz
550
ps
25
50
25
50
25
50
ps
Device to device skew (5)
100
200
100
200
100
200
ps
tJITTER
Random clock jitter (RMS)
0.2
0.8
0.2
0.8
0.2
0.8
ps
tr / tf
Output rise/fall times (20%–80%)
300
ps
tSKEW
(1)
(2)
(3)
(4)
(5)
Within device skew
25°C
150
300
150
300
150
Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board
with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 Ω to VCC – 2.0 V.
Maximum switching frequency measured at output amplitude of 300 mVpp.
Skew is measured between outputs under identical transitions and conditions on any one device.
Device−to−Device Skew for identical transitions at identical VCC levels.
ZO = 50 W
P
P
Receiver
Driver
N
N
ZO = 50 W
50 W
50 W
VTT
VTT = VCC - 2 V
Figure 1. Termination for Output Driver
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5
SN65EPT22
SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014
www.ti.com
1.5 V
1.5 V
IN
OUT
OUT
tPLH
tPHL
Figure 2. Output Propagation Delay
80%
20%
tr
tf
Figure 3. Output Rise and Fall Times
1.5 V
1.5 V
IN
QO
QO
tPLH0
tPHL0
Q1
Q1
tPLH1
tPHL0
Device Skew =
Higher [(tPLH1 - tPLH0), (tPHL1 - tPHL0)]
Figure 4. Device Skew
6
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7.9 Typical Characteristics
1000
VCC = 3 V,
GND = 0 V,
Vswing = 0.8 V - 2 V
900
Output Amplitude - mV
800
TA = -40°C
700
TA = 25°C
600
500
TA = 85°C
400
300
200
100
0
0
500
1000
1500
f - Frequency - MHz
2000
2500
Figure 5. Output Amplitude versus Frequency
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SN65EPT22
SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014
www.ti.com
8 Device and Documentation Support
8.1 Trademarks
All trademarks are the property of their respective owners.
8.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
8
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65EPT22D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
EPT22
SN65EPT22DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SIQI
SN65EPT22DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SIQI
SN65EPT22DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
EPT22
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65EPT22DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65EPT22DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65EPT22DGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
SN65EPT22DR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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