Texas Instruments | SN65HVD01 3.3V RS-485 with Flexible I/O Supply and Selectable Speed (Rev. F) | Datasheet | Texas Instruments SN65HVD01 3.3V RS-485 with Flexible I/O Supply and Selectable Speed (Rev. F) Datasheet

Texas Instruments SN65HVD01 3.3V RS-485 with Flexible I/O Supply and Selectable Speed (Rev. F) Datasheet
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SN65HVD01
SLLSEH0F – JULY 2013 – REVISED AUGUST 2014
SN65HVD01 3.3V RS-485 with Flexible I/O Supply and Selectable Speed
1 Features
3 Description
•
•
The SN65HVD01 is a low-power, 250 kbps or 20
Mbps data rate selectable RS-485 transceiver,
utilizing a 1.65-V to 3.6-V supply for data and enable
signals, and a 3.3 V ± 10% supply for bus signals.
The device is designed for applications requiring
synchronous (parallel transceiver) signal timing. Onchip transient suppression protects the device against
destructive IEC 61000 ESD and EFT transients.
1
•
•
•
•
•
•
•
Exceeds Requirements of TIA-485 Standard
1.65-V to 3.6-V Supply for Data and Enable
Signals
3-V to 3.6-V Supply for Bus Signals
SLR Pin Selectable Data Rates: 250 kbps or 20
Mbps
1/8th Unit Load to Support up to 256 Nodes on a
Bus
Small 3 mm x 3 mm SON Package
Failsafe Receiver (Bus Open, Bus Shorted, Bus
Idle)
Operating Temperature Range: –40°C to 125°C
Bus-Pin Protection More Than:
– ± 15kV HBM Protection
– ± 16kV IEC61000-4-2 Contact Discharge
– ± 16kV IEC61000-4-2 Air Discharge
– 4kV IEC61000-4-4 Fast Transient Burst
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
SN65HVD01DRC
SON (10)
3mm x 3mm
spacer
2 Applications
•
•
•
The device combines a differential driver and a
differential receiver, connected internally to form a
bus port suitable for half-duplex (two-wire bus)
communication. The device features a wide commonmode voltage range making it suitable for multi-point
applications over long cable runs. The SN65HVD01 is
available in a tiny, 3 mm x 3 mm, SON package with
operation characterized from -40°C to 125°C.
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Typical Application
1.8V
VL
SLR
1.8V
3.3V
3.3V
V CC
V CC SLR
VL
R
D
A
DE
B
A
120Ÿ
120Ÿ
RE
B
D
R
DE
RE
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD01
SLLSEH0F – JULY 2013 – REVISED AUGUST 2014
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
5
5
5
6
7
8
9
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Dissipation Ratings ...................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
15
Applications and Implementation ...................... 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1 Trademarks ........................................................... 22
12.2 Electrostatic Discharge Caution ............................ 22
12.3 Glossary ................................................................ 22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2014) to Revision F
Page
•
Changed Figure 22 image and CH3 scale from: 100 V/div To 2 V/div ................................................................................ 20
•
Changed Figure 23 CH3 scale from: 100 V/div To 2 V/div .................................................................................................. 20
Changes from Revision D (November 2013) to Revision E
Page
•
Changed the data sheet to the new TI standard layout ........................................................................................................ 1
•
Added the Device Information Table ..................................................................................................................................... 1
•
Added the Handling Ratings table .......................................................................................................................................... 5
•
Added the Detailed Description section................................................................................................................................ 15
•
Changed Figure 17............................................................................................................................................................... 17
•
Added the Applications and Implementation section............................................................................................................ 18
•
Deleted the Application Information section ......................................................................................................................... 18
•
Added the Power Supply Recommendations ....................................................................................................................... 21
•
Added the Layout section .................................................................................................................................................... 21
2
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SLLSEH0F – JULY 2013 – REVISED AUGUST 2014
Changes from Revision C (November 2013) to Revision D
Page
•
Changed Feature From: Small 3 mm x 3 mm VQFN Package To: Small 3 mm x 3 mm SON Package .............................. 1
•
Changed Feature From: Bus-Pin Protection: To: Bus-Pin Protection More Than: ............................................................... 1
•
Changed Feature From: ≤ 15kV To: ±15 kV HBM Protection ................................................................................................ 1
•
Changed Feature From: ≤ 15kV To: ±16 kV Contact Discharge............................................................................................ 1
•
Changed Feature From: ≤ 15kV To: ±16 kV Air Discharge.................................................................................................... 1
•
Changed DESCRIPTION text From: 3 mm x 3 mm, VQFN package To: 3 mm x 3 mm, SON package .............................. 1
•
Changed the ABSOLUTE MAXIMUM RATINGS for IEC 61000-4-2 ESD (Air-Gap Discharge) From MAX = ±15 To:
MAX = ±16.............................................................................................................................................................................. 5
•
Changed the ABSOLUTE MAXIMUM RATINGS for IEC 61000-4-2 ESD (Contact Discharge) From MAX = ±15 To:
MAX = ±16.............................................................................................................................................................................. 5
•
Changed the Thermal Information table package From VQFN (DRC) To; SON (DRC) ........................................................ 5
Changes from Revision B (October 2013) to Revision C
•
Page
Changed from Product Preview to Production Data............................................................................................................... 1
Changes from Revision A (October 2013) to Revision B
•
Page
Added 8 Typical Characteristics curves ................................................................................................................................. 9
Changes from Original (July 2013) to Revision A
Page
•
Changed Feature From: 1.8-V to 3.3-V Supply for Data and Enable Signals To: 1.65-V to 3.6-V Supply for Data and
Enable Signals........................................................................................................................................................................ 1
•
Changed Feature From: 3.3 V Supply for Bus Signals To: 3-V to 3.6-V Supply for Bus Signals .......................................... 1
•
Changed Feature From: Selectable Data Rates: 250 kbps or 20 Mbps To: SLR Pin Selectable Data Rates: 250
kbps or 20 Mbps ..................................................................................................................................................................... 1
•
Changed the list of APPLICATIONS ...................................................................................................................................... 1
•
Changed the DESCRIPTION ................................................................................................................................................. 1
•
Changed From: 100 Ω resistors To: 120 Ω resistors in the Typical Application circuit.......................................................... 1
•
Changed the ELECTRICAL CHARACTERISTICS table values ............................................................................................ 7
•
Changed the SWITCHING CHARACTERISTICS table values .............................................................................................. 8
•
Changed VCC and 3 V to VL in Figure 9 through Figure 16.................................................................................................. 11
•
Changed Figure 17............................................................................................................................................................... 17
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5 Pin Configuration and Functions
DRC 10 PIN
(TOP VIEW)
VL
R
DE
RE
D
1
10
2
9
3
8
4
7
5
6
VCC
B
A
SLR
GND
Pin Functions
NAME
NO.
I/O
DESCRIPTION
VL
1
Logic Supply 1.65 V to 3.6 V supply for logic I/O signals R, RE, D, DE, and SLR)
R
2
Digital Output Receive data output
DE
3
Digital Input
Driver enable input
RE
4
Digital Input
Receiver enable input
D
5
Digital Input
Transmission data input
GND
6
Reference
Potential
SLR
7
Digital Input
A
8
Bus I/O
Digital bus I/O, A
B
9
Bus I/O
Digital bus I/O, B
VCC
10
Bus Supply
Local device ground
Slew rate select: Low = 20 Mbps, High = 250 kbps. Defaults to 20 Mbps if SLR is left floating
3 V to 3.6 V supply for A and B bus lines
6 Specifications
6.1 Absolute Maximum Ratings (1)
VALUE
MIN
MAX
UNIT
Control supply voltage, VL
–0.5
4
V
Bus supply voltage, VCC
–0.5
5.5
V
Voltage range at A or B Inputs
–13
16.5
V
V
Input voltage range at any logic terminal
–0.3
5.7
Voltage input range, transient pulse, A and B, through 100Ω
–100
100
V
Receiver output current
–12
12
mA
170
°C
Junction temperature, TJ
Continuous total power dissipation
(1)
4
See the Thermal Information table
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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6.2 Handling Ratings
TSTG
MIN
MAX
–65
150
°C
±15
kV
±16
kV
IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND
±16
kV
IEC 61000-4-4 EFT (Fast transient or burst) bus terminals and GND
±4
kV
JEDEC Standard 22, Test Method A114 (Human Body Model), all
terminals
±8
kV
±1.5
kV
Storage temperature range
IEC 60749-26 ESD (Human Body Model), bus terminals and GND
IEC 61000-4-2 ESD (Air-Gap Discharge), bus terminals and GND
VESD
(1)
JEDEC Standard 22, Test Method C101 (Charged Device Model), all
terminals
(1)
UNIT
As stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method. Although IEC air-gap
testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results.
6.3 Recommended Operating Conditions
MIN
VL
Control supply voltage
VCC
Bus supply voltage
VI
Input voltage at any bus terminal (separately or common mode)
VIH
NOM
1.65
V
3.6
V
12
V
High-level input voltage (Driver, driver enable, receiver enable inputs, and slew rate
select)
0.7×VL
VL
V
VIL
Low-level input voltage (Driver, driver enable, receiver enable inputs, and slew rate
select)
0
0.3×VL
V
VID
Differential input voltage
–12
12
V
IO
Output current
Driver
–80
80
mA
–2
2
mA
RL
Differential load resistance
CL
Differential load capacitance
TA
Signaling rate
(2)
(1)
(2)
(1)
Receiver
54
3.3
UNIT
3.6
–7
1/tUI
3
MAX
Ω
60
50
pF
SLR = '0'
20
Mbps
SLR = '1'
250
kbps
125
°C
Operating free-air temperature Thermal Information
–40
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which
disables the driver outputs when the junction temperature reaches 170°C.
6.4 Thermal Information
PARAMETER (1)
SON (DRC)
ΘJA
Junction-to-Ambient Thermal Resistance
41.4
ΘJC(top)
Junction-to-Case(top) Thermal Resistance
48.7
ΘJB
Junction-to-Board Thermal Resistance
18.8
ΨJT
Junction-to-Top characterization parameter
0.6
ΨJB
Junction-to-Board characterization parameter
19
ΘJC(bottom)
Junction-to-Case(bottom) Thermal Resistance
3.7
TTSD
Thermal Shut-down junction temperature
170
(1)
UNIT
°C/ W
°C
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
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6.5 Dissipation Ratings
PARAMETER
PD
6
Power Dissipation driver and receiver
enabled,
VCC = VL = 3.6 V, TJ = 150°C,
50% duty cycle square-wave signal at
signaling rate
TEST CONDITIONS
VALUE
Unterminated
RL = 300 Ω,
CL = 50 pF (driver)
250 kbps
125
20 Mbps
175
RS-422 load
RL = 100 Ω,
CL = 50 pF (driver)
250 kbps
165
20 Mbps
215
RS-485 load
RL = 54 Ω,
CL = 50 pF (driver)
250 kbps
200
20 Mbps
250
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UNIT
mW
mW
mW
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6.6 Electrical Characteristics
over recommended operating range (unless otherwise specified)
PARAMETER
TEST CONDITIONS
RL = 60 Ω, 375 Ω on each output
to –7 V to 12 V
|VOD|
Driver differential output voltage
magnitude
See Figure 9
RL = 54 Ω (RS-485)
MIN
TYP
1.5
2
V
1.5
2
V
RL = 100 Ω (RS-422) TJ ≥ 0°C,
VCC ≥ 3.2V
Δ|VOD|
Change in magnitude of driver
differential output voltage
VOC(SS)
Steady-state common-mode output
voltage
ΔVOC
Change in differential driver output
common-mode voltage
VOC(PP)
Peak-to-peak driver common-mode
output voltage
COD
Differential output capacitance
VIT+
Positive-going receiver differential
input voltage threshold
VIT–
Negative-going receiver differential
input voltage threshold
VHYS
Receiver differential input voltage
threshold hysteresis
(VIT+ – VIT–)
VOH
Receiver high-level output voltage
VOL
Receiver low-level output voltage
II
Driver input, driver enable, and
receiver enable input current
IOZ
Receiver output high-impedance
current
IOS
Driver short-circuit output current
II
ICC
Bus input current (disabled driver)
Supply current (quiescent)
Supply current (dynamic)
(1)
MAX
2
RL = 54 Ω, CL = 50 pF
V
–50
0
50
mV
1
VCC/2
3
V
–50
0
50
mV
See Figure 10
Center of two 27-Ω load resistors
500
mV
15
pF
(1)
–60
–200
–130
40
70
VL = 1.65 V, IOH = -2 mA
1.3
1.45
VL = 3 V, IOH = -2 mA
2.8
2.9
See
–20
mV
(1)
mV
See
mV
V
VL = 1.65 V, IOL = 2 mA
0.2
0.35
VL = 3 V, IOL = 2 mA
0.1
0.2
VO = 0 V or VL, RE at VL
2
µA
–1
1
µA
150
mA
125
µA
VI = 12 V
85
VI = –7 V
V
–2
–150
VL = 1.8 V,
VCC = 3.3 V, DE at 0 V
UNIT
–100
–60
750
µA
1100
µA
1000
µA
Driver and Receiver
enabled
DE=VL, RE =
GND, No load
Driver enabled, receiver
disabled
DE=VCC, RE = VL, No load
350
650
µA
Driver disabled, receiver
enabled
DE=GND, RE = GND, No load
650
800
µA
Driver and receiver
disabled
DE=GND, RE = VL, No load
0.1
5
µA
TJ ≤ 85°C
See the Typical Characteristics section
Under any specific conditions, VIT+ is specified to be at least VHYS higher than VIT–.
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6.7 Switching Characteristics
over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.4
0.8
1.2
µs
0.4
0.8
1.2
µs
0.2
µs
0.025
0.1
µs
0.6
1
µs
3.5
8
µs
5
10
15
ns
6
15
25
ns
4
ns
20
35
ns
14
30
ns
3
7
µs
5
15
ns
60
90
ns
DRIVER, SLR = '1', 250 kbps, bit time ≥ 4 µs
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
RL = 54 Ω, CL = 50 pF
Receiver enabled
Driver enable time
See Figure 11
See Figure 12 and
Figure 13
Receiver disabled
DRIVER, SLR = '0', 20 Mbps, bit time ≥ 50 ns
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
Driver enable time
RL = 54 Ω,
CL = 50 pF
Receiver enabled
See Figure 11
See Figure 12 and
Figure 13
Receiver disabled
RECEIVER, SLR = 'X'
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
8
Receiver enable time
CL = 15 pF
See Figure 14
30
15
ns
10
20
ns
Driver enabled
See Figure 15
15
80
ns
Driver disabled
See Figure 16
3
8
µs
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6.8 Typical Characteristics
2.2
3
Differential Driver Output Voltage (V)
Differential Driver Output Voltage (V)
3.5
60:
100:
2.5
2
1.5
1
VCC = VL = 3.3V,
25oC,
TA =
DE = High
0.5
0
2.15
2.1
2.05
2
VCC = VL = 3.3V,
TA = 25oC,
See Figure 1
1.95
1.9
0
10
20
30
40
50
60
70
80
-7
-5
Driver Output Current (mA)
Figure 1. Differential Driver Output Voltage vs Driver Output
Current
-1
3
5
7
9
11
845
18
835
VCC = VL = 3.3V,
825
TA = 25oC,
SLR = High
Transition Time (ns)
16
14
12
10
8
6
VCC = VL = 3.3V,
4
25oC,
TA =
SLR = Low
2
815
805
795
785
0
775
-40
-20
0
20
40
60
80
100
120
-40
-20
0
Temperature (oC)
14
845
Propagation Delay (ns)
850
12
10
8
6
VCC = VL = 3.3V,
25oC,
TA =
SLR = Low
2
40
60
80
100
120
Figure 4. Transition Time vs Temperature
16
4
20
Temperature (oC)
Figure 3. Transition Time vs Temperature
Propagation Delay (ns)
1
Figure 2. Differential Driver Output Voltage vs Driver
Common Mode Load Voltage
20
Transition Time (ns)
-3
Driver Common Mode Load Voltage (V)
VCC = VL = 3.3V,
840
TA = 25oC,
SLR = High
835
830
825
820
815
810
805
0
800
-40
-20
0
20
40
60
80
100
120
-40
Temperature (oC)
-20
0
20
40
60
80
100
120
Temperature (oC)
Figure 5. Propagation Delay vs Temperature
Figure 6. Propagation Delay vs Temperature
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70
60
60
50
ICC - Supply Current (mA)
ICC - Supply Current (mA)
Typical Characteristics (continued)
50
40
30
VCC = VL = 3.3V,
20
25oC,
TA =
SLR = Low,
10
40
30
VCC = VL = 3.3V,
20
TA = 25oC,
SLR = High,
10
RL = 54:
RL = 54:
0
0
0
5
10
15
20
0
50
Signaling Rate (Mbps)
Figure 7. Supply Current vs Signaling Rate
10
100
150
200
250
Signaling Rate (kbps)
Figure 8. Supply Current vs Signaling Rate
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7 Parameter Measurement Information
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec.
375 W ±1%
VL
DE
0 V or VL
D
A
VOD
60 W ±1%
B
+
_
–7 V < V(test) < 12 V
375 W ±1%
Figure 9. Measurement of Driver Differential Output Voltage with Common-Mode Load
VL
DE
0 V or VL
A
VA
B
VB
RL/2
A
D
VOD
VOC(PP)
B
RL/2
CL
DVOC(SS)
VOC
VOC
Figure 10. Measurement of Driver Differential and Common-Mode Output with RS-485 Load
VL
VL
50%
50%
A
W
»
W
B
»
Figure 11. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
VL
D
DE
Input
Generator
VI
50 W
A
VL
S1
B
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VO
VI
RL = 110 W
± 1%
50%
50%
VO
0V
0.5 V
tPZH
VOH
90%
50%
tPHZ
»0V
D at VL to test non-inverting output, D at 0 V to test inverting output.
Figure 12. Measurement of Driver Enable and Disable Times with Active High Output and Pull-Down
Load
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Parameter Measurement Information (continued)
VL
A
VL
D
S1
VO
» VL
VI
50%
50%
0V
B
DE
Input
Generator
RL = 110 W
±1%
tPZL
tPLZ
CL = 50 pF ±20%
VI
50 W
»3V
CL Includes Fixture
and Instrumentation
Capacitance
VO
50%
10%
VOL
D at 0V to test non-inverting output, D at VL to test inverting output.
Figure 13. Measurement of Driver Enable and Disable Times with Active Low Output and Pull-Up Load
VL
A
Input
Generator
R
VI
50 W
1.5 V
0V
VI
VO
50%
50%
0V
B
RE
tPLH
CL = 15 pF ±20%
VO
CL Includes Fixture
and Instrumentation
Capacitance
tPHL
90% 90%
50%
10%
50%
10%
tr
VOH
VOL
tf
Figure 14. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
12
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Parameter Measurement Information (continued)
VL
VL
DE
0 V or VL
A
B
RE
Input
Generator
VI
1 kW ± 1%
R VO
D
S1
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
VL
VI
50%
50%
0V
tPZH(1)
tPHZ
VOH
90%
VO
50%
D at VL
S1 to GND
»0V
tPZL(1)
tPLZ
VL
VO
50%
D at 0 V
S1 to VL
10%
VOL
Figure 15. Measurement of Receiver Enable/Disable Times with Driver Enabled
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Parameter Measurement Information (continued)
VL
A
0 V or 1.5 V
R VO
S1
B
1.5 V or 0 V
RE
Input
Generator
VI
1 kW ± 1%
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
VL
VI
50%
0V
tPZH(2)
VOH
VO
A at 1.5 V
B at 0 V
S1 to GND
50%
GND
tPZL(2)
VL
VO
50%
VOL
A at 0 V
B at 1.5 V
S1 to VL
Figure 16. Measurement of Receiver Enable Times with Driver Disabled
14
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8 Detailed Description
8.1 Overview
The SN65HVD01 is a low-power, half-duplex RS-485 transceiver whose maximum data rate can be set to either
250 kbps or 20 Mbps via a selection terminal, SLR.
The device possesses two power supply inputs, one for logic control functions, VL, and the other for the bus
supply, VCC. VL can range from 1.65 V minimum up to 3.6 V maximum and allows for the direct interface to lowvoltage FPGAs and micro controllers. VCC requires a supply between 3 V to 3.6 V to assure sufficient output
drive capability across a wide common-mode range.
8.2 Functional Block Diagram
VL SLR VCC
D
DE
A
R
B
RE
GND
8.3 Feature Description
Internal ESD protection circuits protect the transceiver against Electrostatic discharges (ESD) according to
IEC61000-4-2 of up to ±16 kV, and against electrical fast transients (EFT) according to IEC61000-4-4 of up to ±4
kV.
The SN65HVD01 provides internal biasing of the receiver input thresholds in combination with large inputthreshold hysteresis. At a positive input threshold of VIT+ = –60 mV and an input hysteresis of VHYS = 70 mV,
the receiver output remains logic high even in the presence of 130 mVPK differential noise without the need for
external failsafe biasing resistors.
Device operation is specified over a wide temperature range from –40°C to 125°C.
8.4 Device Functional Modes
When driver enable terminal, DE, is logic high, the differential outputs A and B follow the logic states at data
input D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage
defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and
VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE
terminal has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance)
by default. The D terminal has an internal pull-up resistor to VL, thus, when left open while the driver is enabled,
output A turns high and B turns low.
Table 1. Driver Function Table
INPUT
ENABLE
D
DE
A
OUTPUTS
FUNCTION
H
H
H
L
Actively drive bus High
L
H
L
H
Actively drive bus Low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus High by default
B
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When the receiver enable terminal, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT-, the
receiver output, R, turns low. If VID is between VIT+ and VIT- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 2. Receiver Function Table
DIFFERENTIAL INPUT
ENABLE
OUTPUT
FUNCTION
VID = VA – VB
RE
R
VIT+ < VID
L
H
Receive valid bus High
VIT– < VID < VIT+
L
?
Indeterminate bus state
Receive valid bus Low
VID < VIT–
L
L
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
Connecting SLR to VL limits the maximum data rate to 250 kbps and increases the driver rise and fall times to
800 ns. Connecting SLR to GND increases the upper data rate limit to 20 Mbps and reduces the driver rise and
fall times to 10 ns.
Table 3. SLR-Terminal Configuration
16
SLR-INPUT
DATA RATE
TYP tr / tf
VL
250 kbps
800 ns
GND or OPEN
20 Mbps
10 ns
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8.4.1 Equivalent Input and Output Schematic Diagrams
D and RE Inputs
DE Input
Vcc
Vcc
Vcc
R Output
100k
1k
1k
D,RE
1k
DE
9V
R
9V
100k
9V
Vcc
Receiver Inputs
Driver Outputs
Vcc
16V
16V
R2
R2
R1
A
A
R
R1
B
B
16V
R3
R3
16V
Figure 17. Equivalent Input and Output Schematic Diagrams
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9 Applications and Implementation
9.1 Application Information
The SN65HVD01 is a half-duplex RS-485 transceiver commonly used for asynchronous data transmissions. The
driver and receiver enable terminals allow for the configuration of different operating modes.
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
D
D
D
a) Independent driver and
b) Combined enable signals for
receiver enable signals
use as directional control pin
D
c) Receiver always on
Figure 18. SN65HVD01 Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single, direction-control signal.
Thus, when the direction- control line is high, the transceiver is configured as a driver, while for a low the device
operates as a receiver.
Tying the receiver-enable to ground and controlling only the driver-enable input, also uses one control line only.
In this configuration, a node not only receives the data from the bus but also the data it sends and thus can verify
that the correct data have been transmitted.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
R
RE
B
DE
D
B
D
D
R RE DE D
Figure 19. Typical RS-485 Network with SN65HVD01 Transceivers
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
18
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Typical Application (continued)
9.2.1.1
Data Rate and Bus Length
The maximum bus length is limited by the transmission line losses and the signal jitter at a given data rate.
Because data reliability sharply decreases for a jitter of 10% or more of the baud period, Figure 20 shows the
cable length versus data rate characteristic of a conventional RS-485 cable for signal jitter of 10%.
Cable Length (m)
10000
1000
100
10
0.1
1
10
Data Rate (Mbps)
100
Figure 20. Cable Length vs Data Rate
9.2.1.2 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a load impedance of approximately 12kΩ. Because the SN65HVD01 is a 1/8 UL transceiver, it is
possible to connect up to 256 devices to the bus.
9.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is therefore necessary. Figure 21 suggests a protection circuit against 10 kV ESD, 4 kV EFT, and 1 kV
surge transients.
1.8V
3.3V
100nF
100nF
10k
VL
SLR
V CC
R1
R
RxD
MCU/
UART
RE
DE
DIR
A
HVD01
TVS
B
D
TxD
R2
10k
GND
Figure 21. Transient Protection Against ESD, EFT, and Surge Transients
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Typical Application (continued)
Table 4. Recommended Materials
Device
Function
XCVR
3.3V, 250kbps RS-485 Transceiver
Order Number
SN65HVD01D
R1,R2
10Ω, Pulse-Proof Thick-Film Resistor
CRCW0603010RJNEAHP
TVS
Bidirectional 400W Transient Suppressor
CDSOT23-SM712
9.2.3 Application Performance Curves
2 V/div
2 V/div
CH1 - D
CH1 - D
2 V/div
2 V/div
CH2 - VOD
CH2 - VOD
2 V/div
2 V/div
CH3 - R
CH3 - R
Time = 25 ns/div
VCC = 3.3 V
VL = 1.8 V
Time = 2 ms/div
SLR = GND
Figure 22. VOD and R Transient Response - 20 Mbps
20
VCC = 3.3 V
VL = 1.8 V
SLR = VL
Figure 23. VOD and R Transient Response - 250 kbps
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10 Power Supply Recommendations
To assure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100 nF
ceramic capacitor located as close to the supply terminals as possible. Linear voltage regulators for the 1.8 V
logic and 3.3 V bus supplies are TPS76318 and TPS76333 respectively.
11 Layout
On-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and surge
transients occurring in industrial environments. Therefore robust and reliable bus node design requires the use of
external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design.
In order for your PCB design to be successful start with the design of the protection circuit in mind.
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
Apply 100 nF to 220 nF bypass capacitors as close as possible to the VCC terminals of transceiver, UART,
controller ICs on the board.
Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
Use 1k to 10k pull-up/down resistors for enable lines to limit noise currents in theses lines during transient
events.
Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
While pure TVS protection is sufficient for surge transients up to 1kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
11.2 Layout Example
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65HVD01DRCR
ACTIVE
VSON
DRC
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD01
SN65HVD01DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD01
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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30-Sep-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD01DRCR
VSON
DRC
10
2500
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
SN65HVD01DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD01DRCR
VSON
DRC
10
2500
367.0
367.0
35.0
SN65HVD01DRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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