Texas Instruments | SNx5LVDS32, SN65LVDS3486, SN65LVDS9637 High-Speed Differential Line Receivers (Rev. R) | Datasheet | Texas Instruments SNx5LVDS32, SN65LVDS3486, SN65LVDS9637 High-Speed Differential Line Receivers (Rev. R) Datasheet

Texas Instruments SNx5LVDS32, SN65LVDS3486, SN65LVDS9637 High-Speed Differential Line Receivers (Rev. R) Datasheet
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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
SLLS262R – JULY 1997 – REVISED DECEMBER 2014
SNx5LVDS3xxxx High-Speed Differential Line Receivers
1 Features
3 Description
•
The SN55LVDS32, SN65LVDS32, SN65LVDS3486,
and SN65LVDS9637 devices are differential line
receivers that implement the electrical characteristics
of low-voltage differential signaling (LVDS). This
signaling technique lowers the output voltage levels
of 5-V differential standard levels (such as EIA/TIA422B) to reduce the power, increase the switching
speeds, and allow operation with a 3.3-V supply rail.
Any of the differential receivers provides a valid
logical output state with a ±100-mV differential input
voltage within the input common-mode voltage range.
The input common-mode voltage range allows 1 V of
ground potential difference between two LVDS
nodes.
1
•
•
•
•
•
•
•
•
•
•
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
Operate With a Single 3.3-V Supply
Designed for Signaling Rates of up to 150 Mbps
(See )
Differential Input Thresholds ±100 mV Max
Typical Propagation Delay Time of 2.1 ns
Power Dissipation 60 mW Typical Per Receiver at
Maximum Data Rate
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Output Levels
Pin Compatible With AM26LS32, MC3486, and
μA9637
Open-Circuit Fail-Safe
Cold Sparing for Space and High-Reliability
Applications Requiring Redundancy
Device Information(1)
PART NUMBER
SN55LVDS32
2 Applications
•
•
•
Wireless Infrastructure
Telecom Infrastructure
Printer
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
PACKAGE
BODY SIZE (NOM)
LCCC (20)
8.89 mm × 8.89 mm
CDIP (16)
19.56 mm × 6.92 mm
CFP (16)
10.30 mm × 6.73 mm
SOIC (16)
9.90 mm × 3.91 mm
SOP (16)
10.30 mm × 5.30 mm
TSSOP (16)
5.50 mm × 4.40 mm
SOIC (16)
9.90 mm × 3.91 mm
TSSOP (16)
5.50 mm × 4.40 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Equivalent Input and Output Schematic Diagrams
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G, G, 1,2EN OR
3,4EN INPUTS
VCC
VCC
300 kΩ
TYPICAL OF ALL OUTPUTS
VCC
300 kΩ
50 Ω
Input
5Ω
Y Output
A Input
7V
B Input
7V
7V
7V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
SLLS262R – JULY 1997 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
1
1
1
2
3
3
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics: SN55LVDS32 .................. 9
Electrical Characteristics: SN65LVDSxxxx ............... 9
Switching Characteristics: SN55LVDS32 ............... 10
Switching Characteristics: SN65LVDSxxxx ............ 10
Typical Characteristics ............................................ 11
9 Parameter Measurement Information ................ 12
10 Detailed Description ........................................... 15
10.1
10.2
10.3
10.4
Overview ...............................................................
Functional Block Diagram .....................................
Feature Description...............................................
Device Functional Modes......................................
15
15
15
17
11 Application and Implementation........................ 18
11.1 Application Information.......................................... 18
11.2 Typical Application ................................................ 18
12 Power Supply Recommendations ..................... 23
13 Layout................................................................... 23
13.1 Layout Guidelines ................................................. 23
13.2 Layout Example .................................................... 25
14 Device and Documentation Support ................. 27
14.1
14.2
14.3
14.4
14.5
14.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
15 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Revision Q (July 2007) to Revision R
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLLS262R – JULY 1997 – REVISED DECEMBER 2014
5 Description (Continued)
The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver
and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of
data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are characterized for operation from –40°C to
85°C. The SN55LVDS32 device is characterized for operation from –55°C to 125°C.
6 Device Options
Maximum Recommended Operating Speeds
PART NUMBER
ALL Rx ACTIVE
SN65LVDS32
100 Mbps
SN65LVDS3486
100 Mbps
SN65LVDS9637
150 Mbps
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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
SLLS262R – JULY 1997 – REVISED DECEMBER 2014
www.ti.com
7 Pin Configuration and Functions
SN55LVDS32 . . . J OR W
SN65LVDS32 . . . D OR PW
(Marked as LVDS32 or 65LVDS32)
(TOP VIEW)
1B
1A
1Y
G
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
1B
NC
VCC
3
2
1
20 19
4B
1A
SN55LVDS32FK
(TOP VIEW)
1Y
4
G
5
18 4A
17 4Y
NC
6
16 NC
2Y
7
15 G
2A
8
3A
3B
2B
NC
10 11 12 13
GND
14 3Y
9
SN65LVDS3486D (Marked as LVDS3486)
(TOP VIEW)
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
3,4EN
3Y
3A
3B
SN65LVDS9637D (Marked as DK637 or LVDS37)
SN65LVDS9637DGN (Marked as L37)
SN65LVDS9637DGK (Marked as AXF)
(TOP VIEW)
VCC
1Y
2Y
GND
4
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1
8
2
7
3
6
4
5
1A
1B
2A
2B
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SLLS262R – JULY 1997 – REVISED DECEMBER 2014
Pin Functions: SNx5LVDS32xx
PIN
NAME
NUMBER
I/O
DESCRIPTION
VCC
16
–
Supply voltage
GND
8
–
Ground
1A
2
I
Differential (LVDS) non-inverting input
1B
1
I
Differential (LVDS) inverting input
1Y
3
O
LVTTL output signal
2A
6
I
Differential (LVDS) non-inverting input
2B
7
I
Differential (LVDS) inverting input
2Y
5
O
LVTTL output signal
3A
10
I
Differential (LVDS) non-inverting input
3B
9
I
Differential (LVDS) inverting input
3Y
11
O
LVTTL output signal
4A
14
I
Differential (LVDS) non-inverting input
4B
15
I
Differential (LVDS) inverting input
4Y
13
O
LVTTL output signal
G
4
I
Enable (HI = ENABLE)
G/
12
I
Enable (LO = ENABLE)
Pin Functions: SN55LVDS32FK
PIN
NAME
NUMBER
I/O
DESCRIPTION
VCC
20
–
Supply voltage
GND
10
–
Ground
1A
3
I
Differential (LVDS) non-inverting input
1B
2
I
Differential (LVDS) inverting input
1Y
4
O
LVTTL output signal
2A
8
I
Differential (LVDS) non-inverting input
2B
9
I
Differential (LVDS) inverting input
2Y
7
O
LVTTL output signal
3A
13
I
Differential (LVDS) non-inverting input
3B
12
I
Differential (LVDS) inverting input
3Y
14
O
LVTTL output signal
4A
18
I
Differential (LVDS) non-inverting input
4B
19
I
Differential (LVDS) inverting input
4Y
17
O
LVTTL output signal
G
5
I
Enable (HI = ENABLE)
G/
15
I
Enable (LO = ENABLE)
NC
1, 6, 11, 16
–
No connection
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Pin Functions: SN65LVDS3486D
PIN
NAME
NUMBER
I/O
DESCRIPTION
VCC
16
–
Supply voltage
GND
8
–
Ground
1A
2
I
Differential (LVDS) non-inverting input
1B
1
I
Differential (LVDS) inverting input
1Y
3
O
LVTTL output signal
2A
6
I
Differential (LVDS) non-inverting input
2B
7
I
Differential (LVDS) inverting input
2Y
5
O
LVTTL output signal
3A
10
I
Differential (LVDS) non-inverting input
3B
9
I
Differential (LVDS) inverting input
3Y
11
O
LVTTL output signal
4A
14
I
Differential (LVDS) non-inverting input
4B
15
I
Differential (LVDS) inverting input
4Y
13
O
LVTTL output signal
1,2EN
4
I
Enable for channels 1 and 2
3,4EN
12
I
Enable for channels 3 and 4
Pin Functions: SN65LVDS9637Dxx
PIN
NAME
NUMBER
I/O
DESCRIPTION
VCC
1
–
Supply voltage
GND
4
–
Ground
1A
8
I
Differential (LVDS) non-inverting input
1B
7
I
Differential (LVDS) inverting input
1Y
2
O
LVTTL output signal
2A
6
I
Differential (LVDS) non-inverting input
2B
5
I
Differential (LVDS) inverting input
2Y
3
O
LVTTL output signal
6
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SLLS262R – JULY 1997 – REVISED DECEMBER 2014
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage range (2)
VI
Input voltage range
MIN
MAX
UNIT
–0.5
4
V
Enables and output
–0.5
VCC + 0.5
V
A or B
–0.5
4
V
See Thermal
Information
Continuous total power dissipation
Tstg
(1)
(2)
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
8.2 ESD Ratings
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, bus
pins (1)
VALUE
UNIT
±8000
V
260
°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
VCC
Supply voltage
VIH
High-level input voltage
G, G, 1, 2EN, or 3, 4EN
VIL
Low-level input voltage
G, G, 1, 2EN, or 3, 4EN
|VID|
Magnitude of differential input voltage
VIC
Common-mode input voltage (see Figure 1)
MIN
NOM
MAX
3
3.3
3.6
UNIT
2
0.8
0.1
|
ID
2
0.6
|V
V
|V
2.4 *
|
ID
2
VCC – 0.8
TA
Operating free-air temperature
Copyright © 1997–2014, Texas Instruments Incorporated
SN65 prefix
–40
85
SN55 prefix
–55
125
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°C
7
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VIC - Common-Mode Input Voltage Range - V
2.5
2
Max at VCC > 3.15 V
Max at VCC = 3 V
1.5
1
0.5
Min
0
0
0.1
0.2
0.3
0.4
0.5
VID - Differential Input Voltage - V
0.6
Figure 1. VIC vs VID and VCC
8.4 Thermal Information
SN55LVDS32
THERMAL METRIC
SN65LVDS32,
SN65LVDS3486
(1)
FK
20 PINS
J
W
D
16 PINS
NS
SN65LVDS9637
PW
D
16 PINS
DGK
8 PINS
RθJA
Junction-to-ambient thermal
resistance
76.4
88.7
111.5
177.5
RθJC(top)
Junction-to-case (top) thermal
resistance
38.0
46.8
46.4
65.6
RθJB
Junction-to-board thermal
resistance
33.7
49.1
56.6
97.3
ψJT
Junction-to-top characterization
parameter
7.6
12.5
5.5
8.9
ψJB
Junction-to-board characterization
parameter
33.5
48.8
56.1
95.8
Power
Rating
(1)
8
UNIT
Derating Factor Above TA = 25°C
11.0
11.0
8.0
7.6
–
6.2
5.8
3.4
TA ≤ 25°C
1375
1375
1000
950
–
774
725
425
TA ≤ 70°C
880
880
640
608
–
496
464
272
TA ≤ 85°C
715
715
520
494
–
402
377
221
TA ≤ 125°C
275
275
200
–
–
–
–
–
°C/W
mW/°C
mW
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLLS262R – JULY 1997 – REVISED DECEMBER 2014
8.5 Electrical Characteristics: SN55LVDS32
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VITH+
Positive-going differential input voltage
threshold
See Figure 7, Table 1, and
(2)
VITH–
Negative-going differential input voltage
threshold (3)
See Figure 7, Table 1, and
(2)
VOH
High-level output voltage
IOH = –8 mA
VOL
Low-level output voltage
IOL = 8 mA
Supply current
II
Input current (A or B input)
II(OFF)
Power-off input current (A or B input)
VCC = 0, VI = 2.4 V
IIH
High-level input current (EN, G, or G input)
IIL
Low-level input current (EN, G, or G input)
IOZ
High-impedance output current
VO = 0 or VCC
VI = 2.4 V
UNIT
100
mV
mV
2.4
V
0.4
10
18
0.25
0.5
–2
–10
–20
–1.2
–3
Disabled
VI = 0
MAX
–100
Enabled, No load
ICC
(1)
(2)
(3)
TYP (1)
V
mA
μA
20
μA
VIH = 2 V
10
μA
VIL = 0.8 V
10
μA
±12
μA
6
All typical values are at TA = 25°C and with VCC = 3.3 V.
|VITH| = 200 mV for operation at –55°C
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going differential input voltage threshold only.
8.6 Electrical Characteristics: SN65LVDSxxxx
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
MIN
VIT+
Positive-going differential input voltage
threshold
See Figure 7 and Table 1
VIT–
Negative-going differential input voltage
threshold (2)
See Figure 7 and Table 1
VOH
High-level output voltage
VOL
Low-level output voltage
ICC
Supply current
2.4
2.8
SN65LVDS9637
No load
V
0.4
Disabled
VI = 0
Input current (A or B inputs)
II(OFF)
Power-off input current (A or B input)
VCC = 0, VI = 3.6 V
IIH
High-level input current (EN, G, or G input)
IIL
Low-level input current (EN, G, or G input)
IOZ
High-impedance output current
VO = 0 or VCC
VI = 2.4 V
mV
mV
IOL = 8 mA
SN65LVDS32,
SN65LVDS3486
MAX
–100
IOH = –4 mA
Enabled, No load
UNIT
100
IOH = –8 mA
II
(1)
(2)
TYP
(1)
10
18
0.25
0.5
5.5
10
–2
–10
–20
–1.2
–3
V
mA
μA
20
μA
VIH = 2 V
10
μA
VIL = 0.8 V
10
μA
±10
μA
6
All typical values are at TA = 25°C and with VCC = 3.3 V.
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going differential input voltage threshold only.
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8.7 Switching Characteristics: SN55LVDS32
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tsk(o)
Channel-to-channel output skew (1)
tr
TEST CONDITIONS
MIN
TYP
MAX
1.3
2.3
6
ns
1.4
2.2
6.1
ns
CL = 10 pF,
See Figure 8
UNIT
0.1
ns
Output signal rise time, 20% to 80%
0.6
ns
tf
Output signal fall time, 80% to 20%
0.7
tPHZ
Propagation delay time, high-level-to-highimpedance output
6.5
12
ns
tPLZ
Propagation delay time, low-level-to-highimpedance output
5.5
12
ns
8
14
ns
3
12
ns
tPZH
Propagation delay time, high-impedance-to-highlevel output
tPZL
Propagation delay time, high-impedance-to-lowlevel output
(1)
See Figure 9
ns
tsk(o) is the maximum delay time difference between drivers on the same device.
8.8 Switching Characteristics: SN65LVDSxxxx
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
UNIT
MIN
TYP
MAX
tPLH
Propagation delay time, low-to-high-level output
1.5
2.1
3
ns
tPHL
Propagation delay time, high-to-low-level output
1.5
2.1
3
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
0
0.4
ns
tsk(o)
Channel-to-channel output skew (1)
0.1
0.3
ns
tsk(pp)
Part-to-part skew (2)
1
ns
tr
Output signal rise time, 20% to 80%
0.6
tf
Output signal fall time, 80% to 20%
0.7
tPHZ
Propagation delay time, high-level-to-highimpedance output
6.5
12
ns
tPLZ
Propagation delay time, low-level-to-highimpedance output
5.5
12
ns
tPZH
Propagation delay time, high-impedance-to-highlevel output
8
12
ns
tPZL
Propagation delay time, high-impedance-to-lowlevel output
3
12
ns
(1)
(2)
10
CL = 10 pF,
See Figure 8
See Figure 9
ns
ns
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
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8.9 Typical Characteristics
Four Receivers, Loaded
Per Figure 3, Switching
Simultaneously
I CC − Supply Current − mA (rms)
75
t PLH(D) − Low-to-High Propagation Delay Time − ns
85
VCC = 3.6 V
VCC = 3.3 V
65
VCC = 3 V
55
45
35
25
15
50
150
100
200
2.7
2.5
VCC = 3 V
VCC = 3.3 V
2.3
VCC = 3.6 V
2.1
1.9
1.7
1.5
−50
0
50
TA − Free-Air Temperature − °C
Figure 2. SN55LVDS32, SN65LVDS32 Supply Current vs
Frequency
Figure 3. Low-to-High Propagation Delay Time vs Free-Air
Temperature
2.5
2.3
VCC = 3 V
2.1
VCC = 3.3 V
1.9
VCC = 3.6 V
1.7
1.5
−50
100
3.5
2.7
VOH − High-Level Output Voltage − V
t PHL(D) − High-to-Low Propagation Delay Time − ns
f − Frequency − MHz
2.5
2.0
1.5
1.0
0.5
0.0
−60
100
0
50
TA − Free-Air Temperature − °C
3.0
−50
−40
−30
−20
−10
0
IOH − High-Level Output Current − mA
Figure 4. High-to-Low Propagation Delay Time vs Free-Air
Temperature
Figure 5. High-Level Output Voltage vs High-Level Output
Current
5.0
VOL − Low-Level Output Voltage − V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
60
70
80
IOL − Low-Level Output Current − mA
Figure 6. High-Level Output Voltage vs Low-Level Output Current
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9 Parameter Measurement Information
A
Y
VID
B
(VIA + VIB)/2
VIA
VIC
VO
VIB
Figure 7. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
12
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-MODE
INPUT VOLTAGE
VIA (V)
VIB (V)
VID (mV)
VIC (V)
1.25
1.15
100
1.2
1.15
1.25
–100
1.2
2.4
2.3
100
2.35
2.3
2.4
–100
2.35
0.1
0
100
0.05
0
0.1
–100
0.05
1.5
0.9
600
1.2
0.9
1.5
–600
1.2
2.4
1.8
600
2.1
1.8
2.4
–600
2.1
0.6
0
600
0.3
0
0.6
–600
0.3
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VID
VIA
CL = 10 pF
VIB
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0
-0.4 V
tPHL
tPLH
80%
VO
20%
tf
VOH
80%
1.4 V
VOL
20%
tr
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns.
B.
CL includes instrumentation and fixture capacitance within 6 mm of the device under test.
Figure 8. Timing Test Circuit and Waveforms
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B
1.2 V
500 Ω
A
Inputs
(see Note A)
G
10 pF
(see Note B)
±
VO
VTEST
G
1,2EN or 3,4EN
VTEST
2.5 V
A
1V
2V
1.4 V
0.8 V
G, 1,2EN,
or 3,4EN
2V
1.4 V
0.8 V
G
tPLZ
tPLZ
tPZL
tPZL
2.5 V
1.4 V
VOL + 0.5 V
VOL
Y
VTEST
0
1.4 V
A
2V
1.4 V
0.8 V
2V
1.4 V
0.8 V
G, 1,2EN,
or 3,4EN
G
tPHZ
tPHZ
tPZH
tPZH
VOH
VOH - 0.5 V
1.4 V
0
Y
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns.
B.
CL includes instrumentation and fixture capacitance within 6 mm of the device under test.
Figure 9. Enable or Disable Time Test Circuit and Waveforms
14
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10 Detailed Description
10.1 Overview
The SNx5LVDSxx devices are LVDS line receivers. They operate from a single supply that is nominally 3.3 V,
but can be as low as 3.0 V and as high as 3.6 V. The input signals to the SNx5LVDSxx device are differential
LVDS signals. The output of the device is an LVTTL digital signal. This LVDS receiver requires a ±100-mV input
signal to determine the correct state of the received signal. Compliant LVDS receivers can accept input signals
with a common-mode range between 0.05 V and 2.35 V. As the common-mode output voltage of an LVDS driver
is 1.2 V, the SNx5LVDSxx correctly determines the line state when operated with a 1-V ground shift between
driver and receiver.
10.2 Functional Block Diagram
’LVDS32 logic diagram
(positive logic)
G
G
1A
1B
SN65LVDS3486D logic diagram
(positive logic)
4
1A
12
2
1B
1,2EN
3
1Y
1
2
3
1Y
1
2A
4
6
6
3B
4A
4B
5
5
2Y
2
1Y
7
3
2Y
2B
2B
5
2Y
2B
3A
8
2A
2A
7
10
1A
1B
7
6
SN65LVDS9637D logic diagram
(positive logic)
3A
11
9
3B
3Y
10
11
9
3Y
12
3,4EN
14
15
13
4Y
4A
4B
14
15
13
4Y
10.3 Feature Description
10.3.1 Receiver Output States
When the receiver differential input signal is greater than 100 mV, the receiver output is high; and when the
differential input voltage is below –100 mV, the receiver output is low. When the input voltage is between these
thresholds (for example, between –100 mV and 100 mV), the receiver output is indeterminate. It may be high or
low. A special case occurs when the input to the receiver is open-circuited, which is covered in Receiver OpenCircuit Fail-Safe. When the receiver is disabled, the receiver outputs will be high-impedance.
10.3.2 Receiver Open-Circuit Fail-Safe
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV
and within its recommended input common-mode voltage range. However, the SNx5LVDSxx receiver is different
in how it handles the open-input circuit situation.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal to VCC through a 300-kΩ resistor as shown in Figure 10. The fail-safe feature uses
an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high
level regardless of the differential input voltage.
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Feature Description (continued)
VCC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
VIT ≈ 2.3 V
Figure 10. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt does not affect the fail-safe function as long as it
is connected as shown in Figure 10. Other termination circuits may allow a dc-current to ground that could defeat
the pullup currents from the receiver and the fail-safe feature.
10.3.3 Common-Mode Range vs Supply Voltage
The SNx5LVDSxx receivers operate over an input common-mode range of ½ × VID V to 2.4 – ½ × VID V. If the
input signal is anywhere within this range and has a differential magnitude greater than or equal to 100 mV, the
receivers correctly output the LVDS bus state.
10.3.4 General Purpose Comparator
While the SNx5LVDSxx receivers are LVDS standard-compliant receivers, their utility and applications extend to
a wider range of signals. As long as the input signals are within the required differential and common-mode
voltage ranges mentioned above, the receiver output will be a faithful representation of the input signal.
10.3.5 Receiver Equivalent Schematics
The receiver equivalent input and output schematic diagrams are shown in Figure 11. The receiver input is a
high-impedance differential pair. 7-V Zener diodes are included on each input to provide ESD protection. The
receiver output structure shown is a CMOS inverter with an additional Zener diode, again for ESD protection.
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G, G, 1,2EN OR
3,4EN INPUTS
VCC
VCC
300 kΩ
TYPICAL OF ALL OUTPUTS
VCC
300 kΩ
50 Ω
5Ω
Input
Y Output
A Input
B Input
7V
7V
7V
7V
Figure 11. Equivalent Input and Output Schematic Diagrams
16
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10.4 Device Functional Modes
SN55LVDS32, SN65LVDS32 (1)
(1)
SN65LVDS3486 (1)
ENABLES
DIFFERENTIAL INPUT
A, B
G
G
OUTPUT
Y
DIFFERENTIAL INPUT
A, B
ENABLE
EN
OUTPUT
Y
VID ≥ 100 mV
H
X
X
L
H
H
VID ≥ 100 mV
H
H
–100 mV < VID < 100 mV
H
X
X
L
?
?
–100 mV < VID < 100 mV
H
?
VID ≤ –100 mV
H
X
X
L
L
L
VID ≤ –100 mV
H
L
X
L
H
Z
X
L
Z
Open
H
X
X
L
H
H
Open
H
H
H = high level, L = low level, X = irrelevant, Z = high-impedance (off), ? = indeterminate
SN55LVDS32, SN65LVDS32
G
G
4
12
SN65LVDS3486
4
1, 2EN
≥1
EN
EN
2
3
1A
1
1Y
1B
6
1A
1B
2A
2B
3A
3B
4A
4B
5
2A
2
7
3
1Y
1
12
5
6
2Y
7
2Y
2B
3, 4EN
EN
10
10
11
3A
3Y
9
11
9
3Y
3B
14
4A
14
13
15
13
15
4Y
4Y
4B
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Figure 12. SN55LVDS32, SN65LVDS32, and SN65LVDS3486 Logic Symbols
Table 2. Function Table SN65LVDS9637 (1)
(1)
DIFFERENTIAL INPUT
A, B
OUTPUT
Y
VID ≥ 100 mV
H
–100 mV < VID < 100 mV
?
VID ≤ –100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
SN65LVDS9637
8
1A
2
7
1Y
1B
6
2A
3
5
2Y
2B
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
Figure 13. SN65LVDS9637 Logic Symbol
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The SNx5LVDSxx devices are LVDS receivers. These devices are generally used as building blocks for highspeed, point-to-point, data transmission where ground differences are less than 1 V. LVDS drivers and receivers
provide high-speed signaling rates that are often implemented with ECL class devices without the ECL power
and dual-supply requirements.
11.2 Typical Application
11.2.1 Point-to-Point Communications
The most basic application for LVDS buffers, as found in this data sheet, is for point-to-point communications of
digital data, as shown in Figure 14.
Figure 14. Point-to-Point Topology
A point-to-point communications channel has a single transmitter (driver) and a single receiver. This
communications topology is often referred to as simplex. In Figure 14 the driver receives a single-ended input
signal and the receiver outputs a single-ended recovered signal. The LVDS driver converts the single-ended
input to a differential signal for transmission over a balanced interconnecting media of 100-Ω characteristic
impedance. The conversion from a single-ended signal to an LVDS signal retains the digital data payload while
translating to a signal whose features are more appropriate for communication over extended distances or in a
noisy environment.
11.2.1.1 Design Requirements
18
DESIGN PARAMETERS
EXAMPLE VALUE
Driver Supply Voltage (VCCD)
3.0 to 3.6 V
Driver Input Voltage
0.8 to 3.3 V
Driver Signaling Rate
DC to 100 Mbps
Interconnect Characteristic Impedance
100 Ω
Termination Resistance
100 Ω
Number of Receiver Nodes
1
Receiver Supply Voltage (VCCR)
3.0 to 3.6 V
Receiver Input Voltage
0 to 24 V
Receiver Signaling Rate
DC to 100 Mbps
Ground shift between driver and receiver
±1 V
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11.2.1.2 Detailed Design Procedure
11.2.1.2.1 Equipment
•
•
•
Hewlett Packard HP6624A DC power supply
Tektronix TDS7404 Real Time Scope
Agilent ParBERT E4832A
Hewlett Packard HP6624A
DC Power Supply
Agilent ParBERT
(E4832A)
Bench Test Board
Tektronix TDS7404
Real Time Scope
Figure 15. Equipment Setup
11.2.1.2.2 Driver Supply Voltage
An LVDS driver is operated from a single supply. The device can support operation with a supply as low as 3 V
and as high as 3.6 V. The differential output voltage is nominally 340 mV over the complete output range. The
minimum output voltage stays within the specified LVDS limits (247 mV to 454 mV) for a 3.3-V supply.
11.2.1.2.3 Driver Bypass Capacitance
Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths
between power and ground. At low frequencies, a good digital power supply offers very-low-impedance paths
between its terminals. However, as higher frequency currents propagate through power traces, the source is
quite often incapable of maintaining a low-impedance path to ground. Bypass capacitors are used to address this
shortcoming. Usually, large bypass capacitors (10 µF to 1000 μF) at the board-level do a good job up into the
kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching
frequencies of modern digital circuitry. To solve this problem, one should resort to the use of smaller capacitors
(nF to μF range) installed locally next to the integrated circuit.
Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass
capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes,
a typical capacitor with leads has a lead inductance around 5 nH.
The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula
according to Johnson, equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in
supply current of 1 A covers the whole range of LVDS devices offered by Texas Instruments. In this example, the
maximum power supply noise tolerated is 200 mV; however, this figure varies depending on the noise budget
available in your design. (1)
æ DIMaximum Step Change Supply Current ö
Cchip = ç
÷ ´ TRise Time
è DVMaximum Power Supply Noise ø
(1)
(1)
Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
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æ 1A ö
CLVDS = ç
÷ ´ 200 ps = 0.001 mF
è 0.2V ø
(2)
The following example lowers lead inductance and covers intermediate frequencies between the board-level
capacitor (>10 µF) and the value of capacitance found above (0.001 µF). You should place the smallest value of
capacitance as close as possible to the chip.
Figure 16. Recommended LVDS Bypass Capacitor Layout
11.2.1.2.4 Driver Output Voltage
A standard-compliant LVDS driver output is a 1.2-V common-mode voltage, with a nominal differential output
signal of 340 mV. This 340 mV is the absolute value of the differential swing (VOD = |V+ – V–|). The peak-to-peak
differential voltage is twice this value, or 680 mV.
11.2.1.2.5 Interconnecting Media
The physical communication channel between the driver and the receiver may be any balanced paired metal
conductors meeting the requirements of the LVDS standard, the key points which will be included here. This
media may be a twisted pair, twinax, flat ribbon cable, or PCB traces. The nominal characteristic impedance of
the interconnect should be between 100 Ω and 120 Ω with a variation of no more than 10% (90 Ω to 132 Ω).
11.2.1.2.6 PCB Transmission Lines
As per SNLA187, Figure 17 depicts several transmission line structures commonly used in printed-circuit boards
(PCBs). Each structure consists of a signal line and a return path with uniform cross-section along its length. A
microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a
ground or power plane. A stripline is a signal trace in the inner layer, with a dielectric layer in between a ground
plane above and below the signal trace. The dimensions of the structure along with the dielectric material
properties determine the characteristic impedance of the transmission line (also called controlled-impedance
transmission line).
When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 17 shows
examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. When excited by
differential signals, the coupled transmission line is referred to as a differential pair. The characteristic impedance
of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is the differential
impedance of the differential pair. In addition to the trace dimensions and dielectric material properties, the
spacing between the two traces determines the mutual coupling and impacts the differential impedance. When
the two lines are immediately adjacent; for example, S is less than 2W, the differential pair is called a tightlycoupled differential pair. To maintain constant differential impedance along the length, it is important to keep the
trace width and spacing uniform along the length, as well as maintain good symmetry between the two lines.
20
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Figure 17. Controlled-Impedance Transmission Lines
11.2.1.2.7 Termination Resistor
An LVDS communication channel employs a current source driving a transmission line which is terminated with a
resistive load. This load serves to convert the transmitted current into a voltage at the receiver input. To ensure
incident wave switching (which is necessary to operate the channel at the highest signaling rate), the termination
resistance should be matched to the characteristic impedance of the transmission line. The designer should
ensure that the termination resistance is within 10% of the nominal media characteristic impedance. If the
transmission line is targeted for 100-Ω impedance, the termination resistance should be between 90 and 110 Ω.
The line termination resistance should be located as close as possible to the receiver, thereby minimizing the
stub length from the resistor to the receiver. The limiting case would be to incorporate the termination resistor
into the receiver, which is exactly what is offered with a device like the SN65LVDT386.
While we talk in this section about point-to-point communications, a word of caution is useful when a multidrop
topology is used. In such topologies, line termination resistors are to be located only at the end(s) of the
transmission line. In such an environment, LVDS receivers could be used for loads branching off the main bus
with an LVDT receiver used only at the bus end.
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11.2.1.3 Application Curves
All Rx running at 100 Mbps;
Channel 1: 1Y
Channel 2: 2Y
Channel 3: 3Y
Channel 4: 4Y
T = 25°C
VCC = 3.6 V
PRBS = 223 – 1
Figure 18. Typical Eye Patterns SN65LVDS32
All Rx running at 150 Mbps;
Channel 1: 1Y
Channel 2: 2Y
All Rx running at 100 Mbps;
Channel 1: 1Y
Channel 2: 2Y
Channel 3: 3Y
Channel 4: 4Y
T = 25°C
VCC = 3.6 V
PRBS = 223 – 1
Figure 19. Typical Eye Patterns SN65LVDS3486
T = 25°C
VCC = 3.6 V
PRBS = 223 – 1
Figure 20. Typical Eye Patterns SN65LVDS9637
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12 Power Supply Recommendations
The LVDS driver and receivers in this data sheet are designed to operate from a single power supply. Both
drivers and receivers operate with supply voltages in the range of 2.4 V to 3.6 V. In a typical application, a driver
and a receiver may be on separate boards, or even separate equipment. In these cases, separate supplies
would be used at each location. The expected ground potential difference between the driver power supply and
the receiver power supply would be less than |±1 V|. Board-level and local device-level bypass capacitance
should be used and are covered in Driver Bypass Capacitance.
13 Layout
13.1 Layout Guidelines
13.1.1 Microstrip vs. Stripline Topologies
As per SLLD009, printed-circuit boards usually offer designers two transmission line options: Microstrip and
stripline. Microstrips are traces on the outer layer of a PCB, as shown in Figure 21.
Figure 21. Microstrip Topology
On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and
susceptibility problems because the reference planes effectively shield the embedded traces. However, from the
standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends
routing LVDS signals on microstrip transmission lines, if possible. The PCB traces allow designers to specify the
necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 2, 3, and 4
provide formulas for ZO and tPD for differential and single-ended traces. (1) (2) (3)
Figure 22. Stripline Topology
(1)
(2)
(3)
Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310.
Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.
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Layout Guidelines (continued)
13.1.2 Dielectric Type and Board Construction
The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually
provides adequate performance for use with LVDS signals. If rise or fall times of TTL/CMOS signals are less
than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350
or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters
pertaining to the board construction that can affect performance. The following set of guidelines were developed
experimentally through several designs involving LVDS devices:
• Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz.
• All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
• Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
• Solder mask over bare copper with solder hot-air leveling
13.1.3 Recommended Stack Layout
Following the choice of dielectrics and design specifications, you should decide how many levels to use in the
stack. To reduce the TTL/CMOS to LVDS crosstalk, it is a good practice to have at least two separate signal
planes as shown in Figure 23.
Figure 23. Four-Layer PCB Board
NOTE
The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the
power and ground planes tightly coupled, the increased capacitance acts as a bypass for
transients.
One of the most common stack configurations is the six-layer board, as shown in Figure 24.
Figure 24. Six-Layer PCB Board
In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one
ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer
board is preferable, because it offers the layout designer more flexibility in varying the distance between signal
layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.
24
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262R – JULY 1997 – REVISED DECEMBER 2014
Layout Guidelines (continued)
13.1.4 Separation Between Traces
The separation between traces depends on several factors; however, the amount of coupling that can be
tolerated usually dictates the actual separation. Low-noise coupling requires close coupling between the
differential pair of an LVDS link to benefit from the electromagnetic field cancellation. The traces should be 100-Ω
differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs should
have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal
reflection.
In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance
between two traces should be greater than two times the width of a single trace, or three times its width
measured from trace center to trace center. This increased separation effectively reduces the potential for
crosstalk. The same rule should be applied to the separation between adjacent LVDS differential pairs, whether
the traces are edge-coupled or broad-side-coupled.
Figure 25. 3-W Rule for Single-Ended and Differential Traces (Top View)
You should exercise caution when using autorouters, because they do not always account for all factors affecting
crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the
signal path. Using successive 45° turns tends to minimize reflections.
13.1.5 Crosstalk and Ground Bounce Minimization
To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible
to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the
path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing
crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as
possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic
field strength. Discontinuities in the ground plane increase the return path inductance and should be avoided.
13.2 Layout Example
At least two or three times the width of an individual trace should separate single-ended traces and differential
pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength
of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long
parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as
shown in Figure 26.
Copyright © 1997–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637
25
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
SLLS262R – JULY 1997 – REVISED DECEMBER 2014
www.ti.com
Layout Example (continued)
Figure 26. Staggered Trace Layout
This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between
traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path,
TI recommends having an adjacent ground via for every signal via, as shown in Figure 27. Note that vias create
additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in FR4.
Figure 27. Ground Via Location (Side View)
Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground
bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create
discontinuities that increase returning current loop areas.
To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and
so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the
same area, as opposed to mixing them together, helps reduce susceptibility issues.
26
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262R – JULY 1997 – REVISED DECEMBER 2014
14 Device and Documentation Support
14.1 Device Support
14.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
14.1.2 Other LVDS Products
For other products and application notes in the LVDS and LVDM product families visit our Web site at
http://www.ti.com/sc/datatran.
14.2 Documentation Support
14.2.1 Related Information
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
• Low-Voltage Differential Signaling Design Notes (SLLA014)
• Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
• Reducing EMI With LVDS (SLLA030)
• Slew Rate Control of LVDS Circuits (SLLA034)
• Using an LVDS Receiver With RS-422 Data (SLLA031)
• Evaluating the LVDS EVM (SLLA033)
14.3 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN55LVDS32
Click here
Click here
Click here
Click here
Click here
SN65LVDS32
Click here
Click here
Click here
Click here
Click here
SN65LVDS3486
Click here
Click here
Click here
Click here
Click here
SN65LVDS9637
Click here
Click here
Click here
Click here
Click here
14.4 Trademarks
Rogers is a trademark of Rogers Corporation.
All other trademarks are the property of their respective owners.
14.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 1997–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637
27
SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637
SLLS262R – JULY 1997 – REVISED DECEMBER 2014
www.ti.com
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN55LVDS32 SN65LVDS32 SN65LVDS3486 SN65LVDS9637
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9762201Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629762201Q2A
SNJ55
LVDS32FK
5962-9762201QEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9762201QE
A
SNJ55LVDS32J
5962-9762201QFA
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9762201QF
A
SNJ55LVDS32W
SN55LVDS32W
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN55LVDS32W
SN65LVDS32D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS32
SN65LVDS32DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS32
SN65LVDS32DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS32
SN65LVDS32DRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS32
SN65LVDS32NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS32
SN65LVDS32PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS32
SN65LVDS32PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS32
SN65LVDS32PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS32
SN65LVDS3486D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS3486
SN65LVDS3486DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS3486
SN65LVDS3486DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS3486
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
6-Sep-2019
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65LVDS3486DRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVDS3486
SN65LVDS9637D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
DK637
SN65LVDS9637DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXF
SN65LVDS9637DGKG4
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXF
SN65LVDS9637DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXF
SN65LVDS9637DGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AXF
SN65LVDS9637DGN
ACTIVE
HVSSOP
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
L37
SN65LVDS9637DGNR
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
L37
SN65LVDS9637DGNRG4
ACTIVE
HVSSOP
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
L37
SN65LVDS9637DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
DK637
SN65LVDS9637DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
DK637
SNJ55LVDS32FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629762201Q2A
SNJ55
LVDS32FK
SNJ55LVDS32J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9762201QE
A
SNJ55LVDS32J
SNJ55LVDS32W
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9762201QF
A
SNJ55LVDS32W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2019
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55LVDS32 :
• Catalog: SN75LVDS32
• Space: SN55LVDS32-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65LVDS32DR
Package Package Pins
Type Drawing
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN65LVDS32NSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN65LVDS32PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN65LVDS3486DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN65LVDS9637DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65LVDS9637DGNR
HVSSOP
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65LVDS9637DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65LVDS32DR
SOIC
D
16
2500
333.2
345.9
28.6
SN65LVDS32NSR
SO
NS
16
2000
367.0
367.0
38.0
SN65LVDS32PWR
TSSOP
PW
16
2000
350.0
350.0
43.0
SN65LVDS3486DR
SOIC
D
16
2500
350.0
350.0
43.0
SN65LVDS9637DGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
SN65LVDS9637DGNR
HVSSOP
DGN
8
2500
358.0
335.0
35.0
SN65LVDS9637DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.57
1.28
TYPICAL
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(1.89)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(1.89)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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