Texas Instruments | TPD4E1B06 4-Channel Ultra Low Leakage ESD Protection Device (Rev. C) | Datasheet | Texas Instruments TPD4E1B06 4-Channel Ultra Low Leakage ESD Protection Device (Rev. C) Datasheet

Texas Instruments TPD4E1B06 4-Channel Ultra Low Leakage ESD Protection Device (Rev. C) Datasheet
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TPD4E1B06
SLVSBQ8C – DECEMBER 2012 – REVISED JULY 2014
TPD4E1B06 4-Channel Ultra Low Leakage ESD Protection Device
1 Features
3 Description
•
•
The TPD4E1B06 is a 4-channel bi-directional
Transient Voltage Suppressor (TVS) diode array. This
device features ultra low leakage current (0.5 nA) for
precision analog measurements. The ±12 kV contact
and ±15 kV air gap ESD protection exceeds IEC
61000-4-2 level 4 requirements. The TPD4E1B06's
0.7 pF line capacitance makes it suitable for precision
analog, USB2.0, Ethernet, SATA, LVDS, and 1394
interfaces.
Ultra Low Leakage Current 0.5 nA (Max)
Transient Protection for 4 I/O Lines
– IEC 61000-4-2 Contact Discharge ±12 kV
– IEC 61000-4-2 Air-Gap Discharge ±15 kV
– IEC 61000-4-5 Surge 3.0 A (8/20 µs)
I/O Capacitance 0.7 pF (Typ)
Bi-directional TVS Diode Array
Low ESD Clamping Voltage
Industrial Temperature Range: –40°C to 125°C
Small, Easy-to-Route DRL and DCK Packages
1
•
•
•
•
•
Device Information(1)
PART NUMBER
TPD4E1B06
2 Applications
•
•
•
•
•
•
PACKAGE
BODY SIZE (NOM)
SC70 (6)
2.00 mm × 2.10 mm
SOT (6)
1.60 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Glucose Meter
Tablets
GPS
Portable Media Players
TV
Set-top Box
4 Simplified Schematic
Functional Block Diagram
IO1
IO4
IO2
GND
IO3
IO3
System
Connector
IO1
IO2
IO4
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD4E1B06
SLVSBQ8C – DECEMBER 2012 – REVISED JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
4
5
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 7
9
Application and Implementation .......................... 8
9.1 Application Information.............................................. 8
9.2 Typical Application ................................................... 8
10 Layout................................................................... 10
10.1 Layout Guidelines ................................................. 10
10.2 Layout Examples................................................... 10
11 Device and Documentation Support ................. 11
11.1 Trademarks ........................................................... 11
11.2 Electrostatic Discharge Caution ............................ 11
11.3 Glossary ................................................................ 11
12 Mechanical, Packaging, and Orderable
Information ........................................................... 11
5 Revision History
Changes from Revision B (May 2014) to Revision C
•
Page
Changed 2 device names from TPD4E6B06 to TPD4E1B06 ............................................................................................... 8
Changes from Revision A (January 2013) to Revision B
Page
•
Added DRL package to datasheet.......................................................................................................................................... 1
•
Changed IPP, peak pulse current from 3.5 A to 3.0 A............................................................................................................. 4
•
Added Handling Ratings table. .............................................................................................................................................. 4
•
Added Recommended Operating Conditions table. ............................................................................................................... 4
•
Changed Electrical Characteristics table to reflect operating conditions at 25 °C. ................................................................ 4
•
Added MIN VRWM value of –5.5 V. .......................................................................................................................................... 4
•
Changed VCLAMP at IPP = 1 A from 10.5 V to 10.9 V. ............................................................................................................. 4
•
Changed Line Capacitance TYP value from 1 pF to 0.7 pF. ................................................................................................. 4
•
Added Line Capacitance MAX value of 0.95 pF. .................................................................................................................. 4
•
Changed ILEAK from MAX of 10 nA to 0.5 nA ......................................................................................................................... 4
Changes from Original (December 2012) to Revision A
•
2
Page
Fixed "f" units typo from GHz to MHz for CL parameter in ELECTRICAL CHARACTERISTICS table. ................................. 4
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SLVSBQ8C – DECEMBER 2012 – REVISED JULY 2014
6 Pin Configuration and Functions
DCK PACKAGE
2 mm × 2.1 mm × 0.95 mm
(0.65 mm PITCH)
DRL PACKAGE
1.6 mm × 1.6 mm × 0.6 mm
(0.5 mm PITCH)
IO1
NC
IO2
GND
IO1
IO4
IO4
GND
NC
IO3
IO2
IO3
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
DCK
DRL
IO1
1
1
I/O
ESD protected channel. Connect to data line as close to the
connector as possible.
IO2
2
3
I/O
ESD protected channel. Connect to data line as close to the
connector as possible.
IO3
4
4
I/O
ESD protected channel. Connect to data line as close to the
connector as possible.
IO4
5
6
I/O
ESD protected channel. Connect to data line as close to the
connector as possible.
GND
3
2
GND
NC
6
5
NC
Ground
Not internally connected
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SLVSBQ8C – DECEMBER 2012 – REVISED JULY 2014
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Operating temperature range
MIN
MAX
UNIT
–40
125
°C
IPP, peak pulse current (tp = 8/20 μs), IO pin to GND
3.0
A
PPP, peak pulse power (tp = 8/20 μs)
45
W
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
MIN
MAX
UNIT
–65
155
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
–4.0
4.0
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–1.5
1.5
IEC 61000-4-2 contact ESD
–12
12
IEC 61000-4-2 air-gap ESD
–15
15
Storage temperature range
Electrostatic discharge
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 4 kV
may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 1.5 kV
may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIO
The voltage between any two device pins should not exceed 5.5 V
–5.5
5.5
UNIT
V
TA
Operating free-air temperature
–40
125
°C
7.4 Thermal Information
TPD4E1B06
THERMAL METRIC (1)
DCK
DRL
UNIT
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
227.3
233.4
RθJC(top)
Junction-to-case (top) thermal resistance
79.5
95.5
RθJB
Junction-to-board thermal resistance
72.1
68.1
ψJT
Junction-to-top characterization parameter
3.6
7.6
ψJB
Junction-to-board characterization parameter
70.4
67.9
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
TA = 25°C
PARAMETER
VRWM
Reverse stand-off voltage
VCLAMP
Clamp voltage with ESD strike,
IO to GND
TEST CONDITION
TYP MAX
5.5
UNIT
V
IPP = 1 A, tp = 8/20 μSec, from I/O to GND or GND to I/O
10.9
V
IPP = 3 A, tp = 8/20 μSec, from I/O to GND or GND to I/O
14.5
V
ITLP = 10 A to 20 A, I/O to GND
1
ITLP = 10 A to 20 A, GND to I/O
0.8
RDYN
Dynamic resistance
CL
Line capacitance
f = 1 MHz, VBIAS = 2.5 V
VBR
Break-down voltage
IIO = 1 mA, from I/O to GND or GND to I/O
ILEAK
Leakage current
VIO = 2.5 V
4
MIN
–5.5
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0.7
7
Ω
0.95
pF
9.5
V
0.5
nA
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SLVSBQ8C – DECEMBER 2012 – REVISED JULY 2014
7.6 Typical Characteristics
3.5
1.0
0.8
50
Current
Power
3.0
45
40
0.6
2.5
0.2
0.0
±0.2
±0.4
35
Power (W)
Current (A)
Current (mA)
0.4
30
2.0
25
1.5
20
15
1.0
10
±0.6
0.5
±0.8
5
0.0
±1.0
±10
±8
±6
±4
±2
0
2
4
6
8
10
Voltage (V)
0
0
±5
5
10
15
20
25
30
35
40
45
50
Time (s)
C001
C002
Figure 2. Surge Curve (tp = 8/20 μs), Pin IO to GND
Figure 1. DC Voltage Sweep I-V Curve
300
10
8
250
6
Current (pA)
Current (A)
4
2
0
±2
200
150
100
±4
±6
50
±8
±10
±24 ±20 ±16 ±12 ±8
±4
0
4
8
12
16
20
Voltage (V)
24
0
-40
-20
Figure 3. TLP Plot IO to GND
20
40
60
Temperature (°C)
80
100
120
D004
Figure 4. Leakage vs Temperature
110
10
100
0
90
±10
80
±20
70
±30
Voltage (V)
Voltage (V)
0
C003
60
50
40
±40
±50
±60
30
±70
20
±80
10
±90
0
±100
±10
±110
0
25
50
75
100
125
150
Time (s)
175
200
0
C005
Figure 5. +8 kV IEC Waveform
25
50
75
100
125
150
175
Time (s)
Product Folder Links: TPD4E1B06
C006
Figure 6. –8 kV IEC Waveform
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5
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Typical Characteristics (continued)
0
Capacitance (pF)
Insertion Loss (dB)
-1
-2
-3
-4
1E+5
1E+6
1E+7
1E+8
Frequency (Hz)
1E+9
1E+10
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
D007
Figure 7. Insertion Loss
6
1
2
3
4
Vbias (V)
5
D008
Figure 8. Capacitance vs VBIAS
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8 Detailed Description
8.1 Overview
The TPD4E1B06 is a 4-channel bi-directional Transient Voltage Suppressor (TVS) diode array. This device
features ultra low leakage current (0.5 nA) for precision analog measurements. The ±12 kV contact and ±15 kV
air gap ESD protection exceeds IEC 61000-4-2 level 4 requirements. The TPD4E1B06's 0.7 pF line capacitance
makes it suitable for precision analog, USB2.0, Ethernet, SATA, LVDS, and 1394 interfaces.
8.2 Functional Block Diagram
IO1
IO2
IO3
IO4
GND
8.3 Feature Description
The TPD4E1B06 is a 4-channel bi-directional Transient Voltage Suppressor (TVS) diode array. This device
features ultra low leakage current (0.5 nA) for precision analog measurements. The ±12 kV contact and ±15 kV
air gap ESD protection exceeds IEC 61000-4-2 level 4 requirements. The TPD4E1B06's 0.7 pF line capacitance
makes it suitable for precision analog, USB2.0, Ethernet, SATA, LVDS, and 1394 interfaces.
8.3.1 Ultra low Leakage Current 0.5 nA (Max)
TPD4E1B06 ultra-low leakage current supports long battery life and allows for precision analog measurements.
8.3.2 Transient Protection for 4 I/O Lines
The four I/O pins of TPD4E1B06 can withstand ESD events up to ±12 kV contact and ±15 kV air gap per
IEC61000-4-2.
8.3.3 I/O Capacitance 0.7 pF (Typ)
TPD4E1B06 I/O pins present an ultra-low 0.7 pF capacitance to the protected signal lines, making it suitable for
a wide range of applications.
8.3.4 Bi-directional TVS diode array
TPD4E1B06 diode array structure uses back to back diode topology to accommodate bi-directional signaling
between –5.5 V and 5.5 V.
8.3.5 Low ESD Clamping Voltage
TPD4E1B06 clamps ESD events to a safe level to protect system components.
8.4 Device Functional Modes
TPD4E1B06 is a passive integrated circuit that activates whenever fast transient voltages above VBR or below
–VBR are present on the circuit being protected. During ESD events, voltages as high as ±12 kV can be directed
to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of
TPD4E1B06 (usually within 10’s of nano-seconds) the device reverts to passive.
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9 Application and Implementation
9.1 Application Information
TPD4E1B06 is a TVS diode array which is typically used to provide a path to ground for dissipating ESD events
on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes
through the TVS diode, only a small voltage drop is present across the diode. This is the voltage presented to
the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level to the protected
IC.
9.2 Typical Application
System
IO2
Connector
IO1
GND
IO3
IO4
Figure 9. Protecting a Pair of Bi-Directional Differential Data Lines
The typical application of the TBD4E1B06 is to be placed in between the connector and the system. The low
capacitance of the TBD4E1B06 gives flexibility in the end application, as it can be used on many different high
speed interfaces.
9.2.1 Design Requirements
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Signal range on IO1, IO2, IO3, IO4
Pins
–5.5 V to 5.5 V
Operating frequency
1.7 GHz
9.2.2 Detailed Design Procedure
The designer needs to know the following:
• Signal range on all the protected lines
• Operating frequency
9.2.2.1 Signal Range on IO1, IO2, IO3, and IO4 Pins
TPD4E1B06 has 4 protection channels for signal lines. Any I/O will support a signal range of –5.5 V to 5.5 V.
9.2.2.2 Operating Frequency
The 0.7 pF capacitance of each I/O channel supports data rates up to 3.4 Gbps.
8
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9.2.3 Application Curves
Figure 10. 3.4 Gbps HDMI 1.4 Eye Diagram in DCK Package
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TPD4E1B06
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10 Layout
10.1 Layout Guidelines
•
•
•
Place the device as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer should minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Examples
Figure 11 shows a layout example for theTPD4E1B06DCK. Pins 1 & 2 and 4 & 5 are routed differentially. Pin 3 is
routed to the ground plane. Pin 6 does not have an internal connection in the device and does not need to be
routed anywhere on the board. It is also acceptable to connect pin 6 to the ground plane.
Legend
VIA to Ground Plane
1
D0
D1
Figure 11. DCK Layout Example Showing Two Data Pairs, D0 and D1
Figure 12 shows a layout example for theTPD4E1B06DRL. Pins 1 & 6 and 3 & 4 are routed differentially. Pin 2 is
routed to the ground plane. Pin 5 does not have an internal connection in the device and does not need to be
routed anywhere on the board. It is also acceptable to connect pin 5 to the ground plane.
Legend
VIA to Ground Plane
Signal VIA
Top Layer
Bottom Layer
D0
1
D1
Figure 12. DRL Layout Example Showing Two Data Pairs, D0 and D1
10
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPD4E1B06DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BYP
TPD4E1B06DRLR
ACTIVE
SOT-5X3
DRL
6
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(BYG, BYH)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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7-Sep-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPD4E1B06DCKR
SC70
DCK
6
3000
178.0
8.4
2.4
2.5
1.2
4.0
8.0
Q3
TPD4E1B06DRLR
SOT-5X3
DRL
6
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD4E1B06DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
TPD4E1B06DRLR
SOT-5X3
DRL
6
4000
183.0
183.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
SCALE 8.000
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
1
A
6
4X 0.5
1.7
1.5
NOTE 3
2X 1
4
3
B
1.3
1.1
6X
0.3
0.1
0.6 MAX
0.05
TYP
0.00
C
SEATING PLANE
6X
0.18
0.08
0.05 C
SYMM
SYMM
6X
6X
0.4
0.2
0.27
0.15
0.1
0.05
C A B
4223266/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4223266/A 09/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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