Texas Instruments | SN75DP119 DisplayPort 1:1 Signal Repeater and Signal Conditioner (Rev. A) | Datasheet | Texas Instruments SN75DP119 DisplayPort 1:1 Signal Repeater and Signal Conditioner (Rev. A) Datasheet

Texas Instruments SN75DP119 DisplayPort 1:1 Signal Repeater and Signal Conditioner (Rev. A) Datasheet
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SN75DP119
SLLSE12A – NOVEMBER 2009 – REVISED JULY 2014
SN75DP119 DisplayPort 1:1 Signal Repeater and Signal Conditioner
1 Features
3 Description
•
•
•
•
•
•
The SN75DP119 is a 1-lane or 2-lane embedded
DisplayPort (eDP) repeater that regenerates the DP
high speed digital link. The device compensates for
pcb related frequency loss and signal reflections. This
is especially helpful in designs with long pcb traces or
when there is a FET switch in the signal path.
1
DP signal repeater
Supports Data Rates up to 2.7Gbps
Fixed Equalizer With 3 Selectable Settings
12kV ESD HBM
Temperature Range: –40 to 85°C
14 Pin 3.50 x 3.50mm RGY Package or 36-Pin
6.00 x 6.00mm RHH Package
2 Applications
•
•
•
•
•
eDP
Desktop PC
Notebook PC
PC Docking Station
PC Standalone Video Card
Four levels of differential output voltage swing (VOD)
and any combination of pre-emphasis using these
VOD levels are supported. The output swing and preemphasis are configured through device control
inputs. The available output swing levels are
300mVPP, 400mVPP, 600mVPP or 750mVPP.
Therefore, the output pre-emphasis level can be
configured to 0dB, 2.0dB, 2,5dB, 3.5dB, 5.5dB, 6dB,
or 8dB. This is a good solution for embedded link
applications, such as the connection from the GPU to
the notebook internal panel. To adjust the output
signal level adaptively during link training, the
implementation needs to control the device control
inputs.
The SN75DP119 supports programmable integrated
receiver equalization circuitry. This equalization
circuitry can be used to help improve signal integrity
in applications where the input link has a high level of
insertion loss. The equalizer can be set to 3dB or 6dB
equalization. The equalizer can also be turned off.
Device Information(1)
PART NUMBER
SN75DP119
PACKAGE
BODY SIZE (NOM)
VQFN (14)
3.50mm x 3.50mm
VQFN (36)
6.00mm x 6.00mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
SPACER
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75DP119
SLLSE12A – NOVEMBER 2009 – REVISED JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
6
6
7
8
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ............................................... 14
11 Power Supply Recommendations ..................... 16
12 Layout................................................................... 16
12.1 Layout Guidelines ................................................. 16
12.2 Layout Example .................................................... 16
13 Device and Documentation Support ................. 17
13.1 Trademarks ........................................................... 17
13.2 Electrostatic Discharge Caution ............................ 17
13.3 Glossary ................................................................ 17
14 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2009) to Revision A
Page
•
Changed the data sheet to the new TI standard format ........................................................................................................ 1
•
Changed Feature From: Temperature Range: 0..85°C To: Temperature Range: –40 to 85°C ............................................. 1
•
Changed the Description text From: "extended operational temperature range from 0°C to 85°C." To: "extended
operational temperature range from –40°C to 85°C." ............................................................................................................ 2
•
Added the Handling Ratings table .......................................................................................................................................... 5
•
Changed the Operating free-air temperature MIN value in the ROC table From: 0 To –40 .................................................. 5
•
Added the Thermal Information table ..................................................................................................................................... 6
5 Description (continued)
The device is characterized for an extended operational temperature range from –40°C to 85°C.
The SN75DP119 consumes between 64mW and 175mW depending on the selected mode of operation. The
device also supports an ultra low power standby mode. In this mode, the outputs are disabled and the device
draws less then 700µW of power.
2
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SLLSE12A – NOVEMBER 2009 – REVISED JULY 2014
VCC
OUT1p
OUT1n
EQ_CTL
DP119
RGY package
(Top View)
7
1
4
5
EN
6
GND pad
NC
GND
NC
VCC
OUT1p
OUT1n
NC
NC
VOD_CTL
GND
30
16
PRECTL
NC
33
13
NC
EQ_CTL
EN
NC
34
12
NC
NC
35
11
NC
NC
36
10
NC
DP119
RHH package
(Top View)
31
32
1
2
GND
IN0p
IN0p
3
IN0n
VCC
IN1p
2
IN1n
PRE_CTL
17
3
4
5
15
14
6
7
8
9
NC
8
14
NC
NC
NC
9
18
29
IN1n
VOD_CTL
10
NC
GND
13 12 11
27 26 25 24 23 22 21 20 19
28
IN0n
VCC
IN1p
OUT0p
OUT0n
NC
OUT0p
OUT0n
6 Pin Configuration and Functions
thermal Pad.
connect this
pad to GND.
Pin Functions, RGY Package
PIN
NAME
NUMBER
DESCRIPTION
I/O
MAIN LINK INPUT PINS
IN0p
2
IN0n
3
IN1p
5
IN1n
6
DisplayPort Main Link Channel 0 Differential Input
I [100Ω diff]
DisplayPort Main Link Channel 1 Differential Input
MAIN LINK OUTPUT PINS
OUT0p
13
OUT0n
12
OUT1p
10
OUT1n
9
DisplayPort Main Link Channel 0 Differential Output
O [100Ω diff]
DisplayPort Main Link Channel 1 Differential Output
CONTROL PINS
Enable. This input is a 3-level input. If the input is left open, the internal input biasing pulls the input level to
VCC/2. The input can also be pulled high or low externally. This allows to configure the device for 1-channel
mode, 2-channel mode or power down mode.
EN
7
3-level Input
[CMOS]
PRE_CTL
1
3-level Input
[CMOS]
Configures the output pre-emphasis level. This input is a 3-level input. If the input is left open, the internal input
biasing pulls the input level to VCC/2. The input can also be pulled high or low externally. This allows to configure
the pre-emphasis for 3 different levels. See Table 1 for configuration details.
VOD_CTL
14
3-level Input
[CMOS]
Configures the output amplitude VOD level. This input is a 3-level input. If the input is left open, the internal input
biasing pulls the input level to VCC/2. The input can also be pulled high or low externally. This allows to configure
3 different output swing amplitudes. See Table 1 for configuration details.
EN = HIGH: Device in Normal Mode, both outputs OUT1 and OUT2 are enabled;
EN = VCC/2 (input left floating): Device in Normal mode, 2nd output is disabled;
EN = LOW: Device in Power Down mode. All outputs are high-impedance; Inputs are ignored
Configures the EQ input setting for both differential inputs. This input is a 3-level input. If the input is left open, the
internal input biasing pulls the input level to VCC/2. The input can also be pulled high or low externally. This allows
to configure the pre-emphasis for 3 different levels.
8
3-level Input
[CMOS]
VCC
4, 11
pwr
3.3V Supply
GND
thermal pad
pwr
Ground
EQ_CTL
EQ_CTL = LOW: 0dB (EQ turned off)
EQ_CTL = VCC/2 (input left floating): 3dB fixed
EQ EQ_CTL = HIGH (input tied to VCC): 6dB fixed EQ
SUPPLY AND GROUND PINS
Note: (H) Logic High: (L) Logic Low
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Pin Functions, RHH Package
PIN
NAME
NUMBER
DESCRIPTION
I/O
MAIN LINK INPUT PINS
IN0p
2
IN0n
3
IN1p
5
IN1n
6
OUT0p
26
OUT0n
25
OUT1p
23
OUT1n
22
DisplayPort Main Link Channel 0 Differential Input
I [100Ω diff]
DisplayPort Main Link Channel 1 Differential Input
MAIN LINK OUTPUT PINS
DisplayPort Main Link Channel 0 Differential Output
O [100Ω diff]
DisplayPort Main Link Channel 1 Differential Output
CONTROL PINS
Enable. This input is a 3-level input. If the input is left open, the internal input biasing pulls the input level to
VCC/2. The input can also be pulled high or low externally. This allows to configure the device for 1-channel
mode, 2-channel mode or power down mode.
EN
14
3-level Input
[CMOS]
PRECTL
33
3-level Input
[CMOS]
Configures the output pre-emphasis level. This input is a 3-level input. If the input is left open, the internal
input biasing pulls the input level to VCC/2. The input can also be pulled high or low externally. This allows to
configure the pre-emphasis for 3 different levels. See Table 1 for configuration details.
VOD_CTL
31
3-level Input
[CMOS]
Configures the output amplitude VOD level. This input is a 3-level input. If the input is left open, the internal
input biasing pulls the input level to VCC/2. The input can also be pulled high or low externally. This allows to
configure 3 different output swing amplitudes. See Table 1 for configuration details.
EN = HIGH: Device in Normal Mode, both outputs OUT1 and OUT2 are enabled;
EN = VCC/2 (input left floating): Device in Normal mode, 2nd output is disabled;
EN = LOW: Device in Power Down mode. All outputs are high-impedance; Inputs are ignored
Configures the EQ input setting for both differential inputs. This input is a 3-level input. If the input is left
open, the internal input biasing pulls the input level to VCC/2. The input can also be pulled high or low
externally. This allows to configure the pre-emphasis for 3 different levels.
15
3-level Input
[CMOS]
VCC
4, 24
pwr
3.3V Supply
GND
1, 7, 21, 32
thermal pad
pwr
Ground
NC
8-13,16-20,
27-30, 34-36
EQ_CTL
EQ_CTL = LOW: 0dB (EQ turned off)
EQ_CTL = VCC/2 (input left floating): 3dB fixed
EQ EQ_CTL = HIGH (input tied to VCC): 6dB fixed EQ
SUPPLY AND GROUND PINS
Not Connected
Note: (H) Logic High: (L) Logic Low
4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage Range (2)
Voltage Range
MIN
MAX
UNIT
VCC
–0.3
4
V
Main Link I/O (OUTx, INx) Differential Voltage
–0.3
VCC + 0.3
V
Control Inputs
–0.3
5.5
V
Continuous power dissipation
(1)
(2)
See the Thermal Information Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
MIN
MAX
UNIT
–65
150
°C
–12
12
kV
–1000
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
VCC
Supply Voltage
TA
Operating free-air temperature
3
3.3
-40
MAX
UNIT
3.6
V
85
°C
3-LEVEL CONTROL PINS (EN, VOD_CTL, PRE_CTL, EQ_CTL)
VIH
High-level input voltage
VIM
Mid-level input voltage
VIL
Low-level input voltage
VCC–0.5
V
VCC/2–0.3
VCC/2+0.3
V
0.5
V
MAIN LINK DIFFERENTIAL INPUT AND OUTPUT PINS IN[4:1] AND OUT[4:1]
VID
Peak-to-peak input differential voltage – HBR (high bit rate)
0.15
1.4
VPP
VID
Peak-to-peak input differential voltage – LBR (low bit rate)
0.15
1.4
VPP
dR
Data rate
2.7
Gbps
CAC
AC coupling capacitance (each input and each output line)
1×75
2×200
nF
Rtdiff
Differential output termination resistance
80
120
Ω
VOter
Output termination voltage (AC coupled)
0
2
V
Intra-pair skew at the input package pins using 2.7 Gbps input data rate
100
ps
Intra-pair skew at the input package pins using 1.62 Gbps input data rate
300
ps
Input rise and fall time
160
ps
100
m
tSK(in
HBR)
tSK(in
LBR)
tR/F
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7.4 Thermal Information
THERMAL METRIC (1)
RGY
RHH
14 PINS
36 PINS
RθJA
Junction-to-ambient thermal resistance
45
34
RθJC(top)
Junction-to-case (top) thermal resistance
20
20
RθJB
Junction-to-board thermal resistance
16
17
ψJT
Junction-to-top characterization parameter
n/a
n/a
ψJB
Junction-to-board characterization parameter
n/a
n/a
RθJC(bot)
Junction-to-case (bottom) thermal resistance
12
12
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICCDP1max
Supply current 1 DP lane selected
ICCDP2max
Supply current 2 DP lanes selected
ICCDP3max
Supply current 1 DP lane selected
ICCDP4max
Supply current 2 DP lanes selected
ICCDP1typ
Supply current 1 DP lane selected
ICCDP2typ
Supply current 2 DP lanes selected
ICCDP3typ
Supply current 1 DP lane selected
ICCDP4typ
Supply current 2 DP lanes selected
IPWRDN
Shutdown current (PWRDN mode)
TYP
MAX
UNIT
WorstCase:
EN = VCC/2 (1-lane) or VCC (2-lane selected);
2.7Gbps PRBS; VID = 400 mVPP; VOD = 300 mVpp,
8.5 dB pre-emp (PRE_CTL=VCC; VOD_CTL=GND);
EQ_CTL = VCC (6 dB); VCC = 3.3 V (for typ) and
VCC = 3.6 V (for max), (1)
TEST CONDITIONS
MIN
16.2
21.3
mA
31.7
41.4
mA
EN = VCC/2 (1-lane) or VCC (2-lane selected);
2.7Gbps PRBS; VID = 400 mVPP; VOD = 300 mVPP,
0 dB pre-emp (PRE_CTL = GND); VOD_CTL = VCC/2);
EQ_CTL=GND (0 dB); VCC = 3.3 V (for typ) and
VCC = 3.6 V (for max),
12.9
17.6
mA
24.9
34.1
mA
EN = VCC/2 (1-lane) or VCC (2-lane selected);
2.7Gbps PRBS; IN/OUT; VID = 600 mVPP; (PRE_CTL=GND);
VOD_CTL = VCC); VCC = 3.3 V, EQ_CTL = GND (no EQ) (2)
14.5
mA
28.2
mA
EN = VCC/2 (1-lane) or VCC (2-lane selected);
2.7Gbps PRBS; no pre-emp; IN/OUT; VID = 800 mVPP;
(PRE_CTL= VOD_CTL = VCC); VCC = 3.3 V, EQ_CT L =
GND (no EQ) (3)
14.5
mA
28.2
mA
EN = GND;
25
100
µA
3-LEVEL CONTROL PINS (EN, VOD_CTL, PRE_CTL, EQ_CTL)
IL
Low-level input current
VI = 0.5 V; VCC = 3.6 V
–30
30
µA
IH
High-level input current
VI = VCC – 0.5 V; Vcc = 3.6V
–30
30
µA
IM
Mid-level input current
VI = VCC /2 – 0.3V and VI = VCC /2 + 0.3 V; VCC = 3.6 V
–30
30
µA
Rbias
Input bias resistance
See Figure 6
105
125
145
kΩ
RESD
input series resistance to biasing network
See Figure 6
2
2.4
kΩ
(1)
(2)
(3)
6
This current consumption also applies to VOD = 400mV with 5.5 dB pre-emphasis or VOD = 600mV output swing and 2dB preemphasis
This current consumption also applies to VOD = 300mV with 2 dB pre-emphasis
This current consumption also applies to VOD = 300mV with 6dB pre-emphasis or VOD = 400mV output swing and 3.5dB pre-emphasis
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Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
IN[1:0], OUT[1:0]
TEST CONDITIONS
MIN
MAX
UNIT
300mV setting only used
with pre-emphasis
[VOD(0.3)]
VOD(0.4)
TYP
(4)
Output differential voltage swing
[300]
VPRE = VPRE(0.0); 675 Mbps D10.2 test pattern;
VID = 300 mVpp; EQ = 3 dB
mVpp
400
mVpp
VOD(0.6)
600
mVpp
VOD(0.75)
800
mVpp
VEyemask
Eyemask compliance
VOD = 800 mVpp test pattern measured in compliance with
PHY CTS1.1 section 3.1 at test point TP2; VID= 300mVPP ;
EQ=3dB
VPRE(0.0)
VOD = VOD(0.4), VOD(0.6), or VOD(0.8) at 2.7Gbps only
VPRE(2.5)
VOD = VOD(0.3) or VOD(0.6) at 2.7Gbps only
VPRE(3.5)
Driver output pre-emphasis
pass
0
dB
2.7
dB
VOD = VOD(0.4) at 2.7Gbps only; EQ=3dB
0.9
3.5
dB
VPRE(6.0)
VOD = VOD(0.3) or VOD(0.4) at 2.7Gbps only; EQ=3dB
3.3
6.0
dB
VPRE(8.5)
VOD = VOD(0.3) at 2.7Gbps only; EQ=3dB
7
8.5
dB
ROUT
Driver output impedance (single ended)
RIN
Differential input termination impedance
VItem
Input termination voltage (AC coupled)
VOCM
Output common mode voltage
Ω
100
Self-biased
80
100
120
Ω
0
1.7
2
V
0
1.55
2
V
20
mVrms
VTXACCM
Output AC common mode voltage
Verified through statistical measurements only using
1.62Gbps and 2.7Gbps PRBS7 data pattern measured at
TP2; EQ = 3dB
ITXSHORT
Output short circuit current limit
OUT[1:0] shorted to GND; single-ended current
50
mA
IRXSHORT
Input short circuit current limit
IN[1:0] shorted to GND (single ended)
50
mA
(4)
The SN75DP119 is designed to support the DisplayPort high speed differential main link with three levels of output voltage swing and
three levels of pre-emphasis. The main link I/Os of the SN75DP119 are designed to be compliant with the DisplayPort 1.1a specification
7.6 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tR/F(DP)
Differential output edge rate
(20%–80%)
tPD
Propagation delay time
tskpp
Part-to-Part skew
tSK(1)
Intra-pair output skew
tSK(2)
Inter-pair output skew
ΔtDPJIT(PP)
Peak-to-peak output residual jitter
at package pins
TEST CONDITIONS
MIN
All VOD options, Measured at TP1, PRBS7;
VID = 300 mVPP; EQ = 3dB; CLOAD = 1 pF
TYP
MAX
UNIT
155
ps
325
550
ps
0
160
ps
20
ps
100
ps
15
ps
50
With identical voltage and temperature
Signal input skew = 0ps; dR = 2.7Gbps, No Preemphasis, 800 mVp-p , D10.2 pattern
VOD(0.4); VPRE(0.0); Δtjit = tjit(output) – tjit(input);
verified through design simulation and statistical
measurements only using 1.62Gbps and 2.7Gbps
PRBS7 data pattern.
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7.7 Typical Characteristics
Deterministic Output Jitter - (ps) (peak-to-peak)
90
80
70
60
EQ = 0 dB
50
40
EQ = 3 dB
30
20
EQ = 6 dB
10
0
0
5
10
15
20
Input Trace Length (inches) [width = 4 mil]
25
Figure 1. Deterministic Output Jitter vs Input Trace Length
8 Parameter Measurement Information
tf
tr
100%
80 %
0V
VOCM
20 %
V TXACCM
0%
D+
VIterm
0 V to2 V
D-
50 W
50 W
50 W
50 W
0.5 pF
D+
Receiver
V
VD+ ID
D-
Driver
Y
100 pF
VY
Z
100 pF
VD-
VZ
VID = VD+ - VDVICM (VD+ + VD-)
VOD = VY - VZ
VOCM = (VY + VZ)
2
2
Figure 2. Main Link Test Circuit
8
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Parameter Measurement Information (continued)
INxp
INxn
Main Link 0 V
Input
tPD(ML)
tPD(ML)
Main Link
Output 0 V
Figure 3. Main Link Delay Measurments
OUT0p
50%
OUT0n
Tsk1
Tsk2
OUT1p
50%
OUT1n
Tsk1
Figure 4. Main Link Skew Measurements
4 inch
FR4-6mil
trace
TP1
TP2
DP Part
Signal
Analyzer
8 inch
FR4-6mil
trace
Figure 5. Display Port Compliance Setup
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Parameter Measurement Information (continued)
VCC
ESD
RBIAS
RESD
IN
RBIAS
Figure 6. 3-Level Input Biasing Network
10
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9 Detailed Description
9.1 Overview
The SN75DP119 is a 1-lane or 2-lane embedded DisplayPort (eDP) repeater that regenerates the DP high speed
digital link. The device compensates for pcb related frequency loss and signal reflections. This is especially
helpful in designs with long pcb traces or when there is a FET switch in the signal path.
9.2 Functional Block Diagram
3-level
input
EQ_CTL
VIterm
50
3-level
input
PRE_CTL
3-level
input
VOD_CTL
VBIAS
50
50
IN0p
EQ
IN0n
50
OUT0p
DP
Driver
OUT0n
VIterm
50
VBIAS
50
50
IN1p
EQ
IN1n
50
OUT1p
DP
Driver
OUT1n
VCC
3-level
input
PWR
GND
EN
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Functional Block Diagram (continued)
2:1 FET
GPU1
DP119
1 or 2 diff
MAIN[1:0]
1 or 2 diff
MLA[1:0]
OUT[1:0]
HPD
IN[1:0]
OUT[1:0]
MLB[1:0]
AUX+
AUX-
GPU2
AUX_A+
AUX_A-
2:1 FET
LCD panel
connector
MAIN[1:0]
1 or 2 diff
AUXSNKp
AUXSNKn
HPD
AUX+
AUX-
AUX_B+
AUX_B-
Figure 7. Typical Implementation Showing Two GPU Sources, a 2:1 FET Switch, and the DP119 as Signal
Conditioner
9.3 Feature Description
9.3.1 Pre-Emphasis and VOD Output Swing Setings
The SN75DP119 allows configuring output pre-emphasis and output swing through the external control inputs.
The following options are valid:
Table 1. Pre-Emphasis and VOD Output Swing Configuration
12
PRE_CTL = LOW
PRE_CTL = VCC/2
(INPUT LEFT FLOATING)
PRE_CTL = HIGH
VOD_CTL = LOW
VOD = 300 mVPP;
2.5 dB pre-emphasis
(lowest power consumption)
VOD = 300 mVPP;
6 dB pre-emphasis
VOD = 300 mVPP;
8.5 dB pre-emphasis
VOD_CTL = VCC/2
(input left floating)
VOD = 400 mVPP;
no pre-emphasis
VOD = 400 mVPP;
3.5 dB pre-emphasis
VOD = 400 mVPP;
5.5 dB pre-emphasis
VOD_CTL = HIGH
VOD = 600 mVPP;
no pre-emphasis
VOD = 600 mVPP;
2.5 dB pre-emphasis
VOD = 800 mVPP,
no pre-emphasis
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9.4 Device Functional Modes
9.4.1 Status Detect and Operating Modes Flow Diagram
The SN75DP119 switches between the power saving and the active modes in the following way:
Power up
EN=low
Power up
EN=high
EN=low
EN=high
ShutDown
Mode
EN=low
2-channel
Active
Mode
EN=Vcc/2
EN=Vcc/2
EN=high
1-channel
Active
Mode
Power up
EN=Vcc/2
Figure 8. SN75DP119 Operational Modes Flow Chart
Table 2. Description of SN75DP119 Modes
MODE
ShutDown Mode
CHARACTERISTICS
CONDITIONS
Least amount of power consumption (all circuitry turned off); outputs are highimpedance
EN is low
2- channel Active
Mode
Data transfer (normal operation); The device outputs OUTx represents the data
EN is high
received on the input INx. The input EQ and output pre-emphasis and output swing (both main link outputs
voltage level are controlled through the external control pins.
enabled)
1-channel Active
Mode
Data transfer (normal operation); The device output OUT0 represents the data
EN is VCC/2
received on the input IN0. The 2nd channel (IN1 and OUT1) are disabled. The input (only main link channel 0
EQ and output pre-emphasis and output swing voltage level are controlled through enabled)
the external control pins.
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10 Application and Implementation
10.1 Application Information
Figure 9 provides a simple schematic reference for the 14-pin package. In addition to this schematic sufficient
VCC decoupling for the 3.3V power supply is necessary.
10.2 Typical Application
DPRX
(panel)
100n
100n
3.3V
100n
3.3V
100n
R3H
3.3V
R2H
OUT1p
13 12 11
10
OUT1n
R2L
OUT0n
OUT0p
R3L
9
8
14
VOD_CTL
3.3V
EQ_CTL
DP119
RGY package
3.3V
4
5
EN
R4L
6
IN1p
R1L
3
7
IN1n
IN0p
2
VCC
R1H
IN0n
PRE_CTL
R4H
(Top view)
1
3.3V
100n
100n
Component installation notes
100n
100n
DPTX
R1x-R4x resistor value: 20kW or less each
To set the input high , install RxH and do not install
RxL; To set the input low , install RxL and do not
install RxH; To set input to Vcc /2 (3rd possible
input level), do not install any resistor; instead
leave input floating, which will self-bias the input to
Vcc/2
Figure 9. Simplified Schematic drawing
10.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
14
EXAMPLE VALUE
VCC
3.3 V
Main Link Input Voltage
VID = 0.15 to 1.4 Vpp
Control Pin Max Voltage for Low
0.5 V
Control Pin Voltage Range Mid
Min (VCC/2) - 0.3 V to Max of (VCC/2) + 0.3 V
Control Pin Min Voltage for High
Min VCC - 0.5 V
Main Link AC Decoupling Cap
75 nF to 200 nF Recommend 100 nF
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10.2.2 Detailed Design Procedure
• Determine the output swing of the Graphic Processing Unit (GPU) .
• Determine the loss profile between the GPU and the LCD display connector.
• Determine the loss profile between the mother board LCD display connector and the DisplayPort receiver.
• Determine the DisplayPort receiver capabilities, acceptable VID along with its receive equalizer capability.
• Based upon this loss profile and signal swing determine optimal location for the SN75DP119, close to the
connector, midway, or close to GPU.
• Use the typical application drawing, Figure 9, for information on using the AC coupling caps and control pin
resistors.
• Set the DP119 Input equalizer appropriately to support the loss profile and signal swing for the link between
the GPU and connector by using the EQ_CTL control pin.
• Set the DP119 VOD and Pre-emphasis level appropriately to support the Connector to DisplayPort receiver
link by using the PRE_CTL and VOC_CTL control pins.
• The thermal pad must be connected to ground.
• Use a 1 µF and 0.1 µF decouple caps from VCC pins to Ground.
10.2.3 Application Curves
Trace Length = 16 (inches) [width = 4 mil]
DR = 2.7 Gbps
VOD = 400 mVpp
PRE = 0 dB
Trace Length = 16 (inches) [width = 4 mil]
DR = 2.7 Gbps
VOD = 400 mVpp
PRE = 0 dB
Figure 10. Eye Pattern Output To DP119
Figure 11. Eye Pattern Output To DP119
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11 Power Supply Recommendations
SN75DP119 is designed to run from a single supply voltage of 3.3V.
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
Data rates of 2.7Gbps require fast edge rate, which can cause EMI radiation if the pcb is not designed
carefully.
Decoupling with small current loops is recommended.
It is recommended to place the de-coupling cap as close as possible to the device and on the same side of
the pcb (see Figure 12).
Choose the capacitor such that the resonant frequency of the capacitor does not align closely with 2.7GHz.
Also provide several GND vias to the thermal pad to minimize the area of current loops.
12.2 Layout Example
Figure 12. De-Coupling Layout Recommendation
16
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13 Device and Documentation Support
13.1 Trademarks
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN75DP119RGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DP119
SN75DP119RGYT
ACTIVE
VQFN
RGY
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DP119
SN75DP119RHHR
ACTIVE
VQFN
RHH
36
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DP119
SN75DP119RHHT
ACTIVE
VQFN
RHH
36
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DP119
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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13-May-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN75DP119RGYR
VQFN
RGY
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
8.0
12.0
Q1
3000
330.0
12.4
3.75
3.75
1.15
W
Pin1
(mm) Quadrant
SN75DP119RGYT
VQFN
RGY
14
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
SN75DP119RHHR
VQFN
RHH
36
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
SN75DP119RHHT
VQFN
RHH
36
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN75DP119RGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
SN75DP119RGYT
VQFN
RGY
14
250
210.0
185.0
35.0
SN75DP119RHHR
VQFN
RHH
36
2500
367.0
367.0
38.0
SN75DP119RHHT
VQFN
RHH
36
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHH 36
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6 x 6, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225440/A
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PACKAGE OUTLINE
RHH0036B
VQFN - 1 mm max height
SCALE 2.300
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
4.1 0.1
2X 4
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
18
10
9
19
SYMM
37
2X 4
32X 0.5
1
PIN 1 ID
27
36
28
36X
0.65
0.45
36X
0.30
0.18
0.1
0.05
C A B
4225414/A 10/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHH0036B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 4.1)
SYMM
28
36
SEE SOLDER MASK
DETAIL
36X (0.75)
36X (0.24)
27
1
(1.8)
TYP
32X (0.5)
(0.68)
TYP
37
SYMM
(5.65)
(R0.05) TYP
( 0.2) TYP
VIA
19
9
10
18
(0.68)
TYP
(1.8) TYP
(5.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK DEFINED
MASK DETAILS
4225414/A 10/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHH0036B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9X ( 1.16)
(1.36)
TYP
36
28
36X (0.75)
27
1
36X (0.24)
32X (0.5)
(1.36) TYP
37
SYMM
(5.65)
(R0.05) TYP
19
9
10
SYMM
18
(5.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 15X
EXPOSED PAD 37
72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4225414/A 10/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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