Texas Instruments | DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer (Rev. C) | Datasheet | Texas Instruments DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer (Rev. C) Datasheet

Texas Instruments DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer (Rev. C) Datasheet
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DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
DS90UR903Q/DS90UR904Q 10 - 43MHz
18 Bit Color FPD-Link II Serializer and Deserializer
1 Features
3 Description
•
•
•
•
The DS90UR903Q/DS90UR904Q chipset offers a
FPD-Link II interface with a high-speed forward
channel for data transmission over a single
differential pair. The Serializer/ Deserializer pair is
targeted for direct connections between graphics host
controller and displays modules. This chipset is
ideally suited for driving video data to displays
requiring 18-bit color depth (RGB666 + HS, VS, and
DE). The serializer converts 21 bit data over a single
high-speed serial stream. This single serial stream
simplifies transferring a wide data bus over PCB
traces and cable by eliminating the skew problems
between parallel data and clock paths. This
significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width,
and connector size and pins.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
10 MHz to 43 MHz Input PCLK Support
210 Mbps to 903 Mbps Data Throughput
Single Differential Pair Interconnect
Embedded Clock with DC Balanced Coding to
Support AC-coupled Interconnects
Capable to Drive up to 10 meters Shielded
Twisted-Pair
I2C Compatible Serial Interface for Device
Configuration
Single Hardware Device Addressing Pin
LOCK Output Reporting Pin to Validate Link
Integrity
Integrated Termination Resistors
1.8V- or 3.3V-compatible Parallel Bus Interface
Single Power Supply at 1.8V
ISO 10605 ESD and IEC 61000-4-2 ESD
Compliant
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
Temperature Range −40°C to +105°C
No Reference Clock Required on Deserializer
Programmable Receive Equalization
EMI/EMC Mitigation
– DES Programmable Spread Spectrum (SSCG)
outputs
– DES Receiver Staggered Outputs
The Deserializer inputs provide equalization control to
compensate for loss from the media over longer
distances. Internal DC balanced encoding/decoding is
used to support AC-Coupled interconnects.
The Serializer is offered in a 40-pin WQFN package
and the Deserializer is offered in a 48-pin WQFN
package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UR903Q-Q1
WQFN RTA (40)
6.00 mm × 6.00 mm
DS90UR904Q-Q1
WQFN RHS (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
Automotive Display Systems
– Central Information Displays
– Navigation Displays
– Rear Seat Entertainment
Typical Eye Diagram
Simplified Schematic
DS90UR903Q
Serializer
FPD-Link II
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
PLL
PDB
MODE
PDB
MODE
Config.
PC
SDA
SCL
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
Timing
Controller
LCD
Display
Config.
SDA
SCL
Magnitude (80 mV/DIV)
Graphics
Controller
--Video
Processor
DS90UR904Q
Deserializer
PC
Time (200 ps/DIV)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ..................................... 6
Handling Ratings ...................................................... 6
Recommended Operating Conditions....................... 6
Thermal Information ................................................ 7
Electrical Characteristics
................................................................................... 7
6.6 Recommended Serializer Timing for PCLK ............. 9
6.7 Serial Control Bus AC Timing Specifications (SCL,
SDA) - I2C Compliant (See Figure 1)....................... 10
6.8 Serial Control Bus DC Characteristics (SCL, SDA) I2C Compliant........................................................... 11
6.9 Serializer Switching Characteristics........................ 15
6.10 Deserializer Switching Characteristics.................. 16
6.11 Typical Characteristics .......................................... 17
7
Detailed Description ............................................ 18
7.1
7.2
7.3
7.4
7.5
7.6
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
18
18
19
20
20
22
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
Page
•
Added data sheet flow and layout to conform with new TI standards. Added the following sections: Application and
Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
•
Added additional thermal charateristics.................................................................................................................................. 7
•
Changed test condition Vin to Vddio ........................................................................................................................................ 7
•
Added power up sequencing information and timing diagram. ............................................................................................ 29
•
Added application graphics of the serializer CML output. .................................................................................................... 30
Changes from Revision A (April 2013) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 30
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Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
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SNLS346C – AUGUST 2011 – REVISED JUNE 2014
5 Pin Configuration and Functions
VDDIO
31
DIN[8]
32
DIN[9]
33
VDDD
34
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
NC
NC
30
29
28
27
26
25
24
23
22
21
40 Pin Serializer – DS90UR903Q
Package RTA
Top View
DAP = GND
DS90UR903Q
Serializer
40-Pin WQFN
(Top View)
20
NC
19
NC
18
VDDCML
17
DOUT+
16
DOUT-
15
VDDT
10
RES
RES
11
9
40
ID[x]
DIN[15]
8
MODE
SDA
12
7
39
SCL
DIN[14]
6
PDB
PCLK
13
5
38
DIN[20]
DIN[13]
4
VDDPLL
DIN[19]
14
3
37
DIN[18]
DIN[12]
2
36
DIN[17]
DIN[11]
1
35
DIN[16]
DIN[10]
DS90UR903Q Serializer Pin Functions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
DIN[20:0]
PCLK
5, 4, 3, 2, 1, 40,
39, 38, 37, 36, 35,
33, 32, 30, 29, 28,
27, 26, 25, 24, 23
Inputs, LVCMOS
w/ pull down
Parallel data inputs.
6
Input, LVCMOS
w/ pull down
Pixel Clock Input Pin. Strobe edge set by TRFB control register.
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
7
Input,
Open Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
8
Input/Output,
Open Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE
12
Input, LVCMOS
w/ pull down
ID[x]
9
Input, analog
I2C Mode select
MODE = H, -REQUIRED. The MODE pin must be set HIGH to allow I2C
configuration of the serializer.
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 1
CONTROL AND CONFIGURATION
PDB
13
Input, LVCMOS
w/ pull down
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power
Down, the PLL is shutdown, and IDD is minimized. Programmed control
register data are NOT retained and reset to default values
RES
10, 11
Input, LVCMOS
w/ pull down
Reserved.
This pin MUST be tied LOW.
NC
22, 21, 20, 19
No Connect
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DS90UR903Q Serializer Pin Functions (continued)
PIN
NAME
I/O, TYPE
NUMBER
DESCRIPTION
FPD-LINK II INTERFACE
Output, CML
Non-inverting differential output. The interconnect must be AC Coupled with a
100 nF capacitor.
16
Output, CML
Inverting differential output. The interconnect must be AC Coupled with a 100
nF capacitor.
VDDPLL
14
Power, Analog
PLL Power, 1.8V ±5%
VDDT
15
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
18
Power, Analog
CML Power, 1.8V ±5%
VDDD
34
Power, Digital
Digital Power, 1.8V ±5%
VDDIO
31
Power, Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from
VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side,
located at the center of the WQFN package. Connected to the ground plane
(GND) with at least 16 vias.
DOUT+
17
DOUTPOWER AND GROUND (1)
VSS
(1)
DAP
See Power Up Requirements and PDB PIN.
ROUT[2]
ROUT[3]
25
VDDIO1
29
26
NC
30
ROUT[0]
NC
31
ROUT[1]
NC
32
27
NC
33
28
PDB
LOCK
34
24
ROUT[4]
23
ROUT[5]
22
ROUT[6]
21
ROUT[7]
20
VDDIO2
19
ROUT[8]
18
ROUT[9]
17
VDDD
45
16
ROUT[10]
46
15
ROUT[11]
MODE
47
14
ROUT[12]
ID[x]
48
13
ROUT[13]
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9
10
11
12
ROUT[17]
ROUT[16]
ROUT[15]
ROUT[14]
8
RES
7
VDDPLL
VDDIO3
44
ROUT[18]
43
RES
6
RES
DS90UR904Q
Deserializer
48-Pin WQFN
(Top View)
ROUT[19]
42
5
41
RIN-
4
RIN+
PCLK
40
ROUT[20]
VDDCML
DAP = GND
3
39
2
38
RES
SCL
RES
VDDSSCG
37
1
RES
SDA
4
35
VDDR
36
48 Pin Deserializer - DS90UR904Q
Package RHS
Top View
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
DS90UR904Q Deserializer Pin Descriptions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs,
LVCMOS
Parallel data outputs.
4
Output,
LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
PCLK
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
2
Input,
Open Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
1
Input/Output,
Open Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE
47
ID[x]
9
I2C Mode select
Input, LVCMOS
MODE = H -REQUIRED. The MODE pin must be set HIGH to allow I2C configuration
w/ pull up
of the deserializer.
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 2
CONTROL AND CONFIGURATION
PDB
35
LOCK
34
RES
37, 38, 39, 43,
44, 46
NC
30, 31, 32, 33
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
Input, LVCMOS
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
w/ pull down
Down. Programmed control register data are NOT retained and reset to default
values.
Output,
LVCMOS
-
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
Reserved.
Pin 46: This pin MUST be tied LOW.
Pin 37, 43, 44: Leave pin open.
Pins 38, 39: Route to test point or leave open if unused.
No Connect
FPD-LINK II INTERFACE
RIN+
41
Input, CML
Noninverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
RIN-
42
Inputt, CML
Inverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
POWER AND GROUND
(1)
VDDSSCG
3
Power, Digital
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
VDDIO1/2/3
29, 20, 7
Power, Digital
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDD
17
Power, Digital
Digital Core Power, 1.8V ±5%
VDDR
36
Power, Analog
Rx Analog Power, 1.8V ±5%
VDDCML
40
Power, Analog
1.8V ±5%
VDDPLL
45
Power, Analog
PLL Power, 1.8V ±5%
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
VSS
(1)
See Power Up Requirements and PDB PIN.
Copyright © 2011–2014, Texas Instruments Incorporated
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
MIN
MAX
UNIT
Supply Voltage – VDDn (1.8V)
PARAMETER
−0.3
+2.5
V
Supply Voltage – VDDIO
−0.3
+4.0V
V
LVCMOS Input Voltage I/O Voltage
−0.3
(VDDIO + 0.3V)
V
CML Driver I/O Voltage (VDD)
−0.3
(VDD + 0.3V)
V
CML Receiver I/O Voltage (VDD)
−0.3
(VDD + 0.3V)
V
+150
°C
1/θJA above +25°
°C/W
Junction Temperature
Maximum Package Power Dissipation Capacity
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 Handling Ratings
Tstg
MIN
MAX
UNIT
–65
150
°C
-8
+8
-1
+1
Machine Model (MM)
-250
+250
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-25
+25
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-10
+10
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-15
+15
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-10
+10
Storage temperature range
Human body model (HBM), per AEC Q100-002
V(ESD)
Electrostatic discharge
ESD Rating (IEC 61000-4-2)
RD = 330Ω, CS = 150pF
ESD Rating (ISO10605)
RD = 330Ω, CS = 150/330pF
RD = 2KΩ, CS = 150/330pF
(1)
(1)
Charged device model (CDM), per AEC Q100-011
kV
V
kV
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO) (1.8V)
1.71
1.8
1.89
V
3.0
3.3
LVCMOS Supply Voltage (VDDIO) (3.3V)
Supply Noise
3.6
V
VDDn (1.8V)
25
mVp-p
VDDIO (1.8V)
25
mVp-p
VDDIO (3.3V)
50
mVp-p
Operating Free Air Temperature (TA)
-40
PCLK Clock Frequency
10
6
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+25
+105
°C
43
MHz
Copyright © 2011–2014, Texas Instruments Incorporated
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DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
Thermal Information (1)
6.4
THERMAL METRIC
(2)
DS90UR903Q
40L WQFN
DS90UR904Q
48L WQFN
RTA
RHS
40 PINS
48 PINS
RθJA
Junction-to-ambient thermal resistance
31.9
30.0
RθJC(top)
Junction-to-case (top) thermal resistance
18.5
11.1
RθJB
Junction-to-board thermal resistance
8.1
6.9
ψJT
Junction-to-top characterization parameter
0.3
0.1
ψJB
Junction-to-board characterization parameter
8.1
6.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.5
2.4
(1)
(2)
UNIT
°C/W
For soldering specifications, see SNOA549
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics (1)
(2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VDDIO = 3.0V to 3.6V
2.0
VDDIO
V
VIL
Low Level Input Voltage
VDDIO = 3.0V to 3.6V
GND
0.8
V
IIN
Input Current
VIN = 0V or 3.6V
VDDIO = 3.0V to 3.6V
-20
+20
µA
VOH
High Level Output Voltage
VDDIO = 3.0V to 3.6V
IOH = -4 mA
2.4
VDDIO
V
VOL
Low Level Output Voltage
VDDIO = 3.0V to 3.6V
IOL = +4 mA
GND
0.4
V
IOS
Output Short Circuit Current
VOUT = 0V
TRI-STATE Output Current
PDB = 0V,
VOUT = 0V or VDD
IOZ
±1
-39
-20
±1
mA
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VDDIO = 1.71V to 1.89V
0.65 VDDIO
VDDIO +0.3
V
VIL
Low Level Input Voltage
VDDIO = 1.71V to 1.89V
GND
0.35 VDDIO
V
IIN
Input Current
VIN = 0V or 1.89V
VDDIO = 1.71V to 1.89V
-20
+20
µA
VOH
High Level Output Voltage
VDDIO = 1.71V to 1.89V
IOH = −4 mA
VDDIO 0.45
VDDIO
V
VOL
Low Level Output Voltage
VDDIO = 1.71V to 1.89V
IOL = +4 mA
GND
0.45
V
IOS
Output Short Circuit Current
VOUT = 0V
IOZ
TRI-STATE Output Current
PDB = 0V,
VOUT = 0V or VDD
(1)
(2)
(3)
±1
-20
-20
±1
mA
+20
µA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
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Electrical Characteristics(1) (2)
(continued)
www.ti.com
(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
268
340
412
mV
1
50
mV
VDD - VOD
VDD (MAX) VOD (MIN)
V
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD|
Output Differential Voltage
RT = 100Ω, Figure 5
ΔVOD
Output Differential Voltage Unbalance
RL = 100Ω
VOS
Output Differential Offset Voltage
RL = 100Ω
Figure 5
ΔVOS
Offset Voltage Unbalance
RL = 100Ω
IOS
Output Short Circuit Current
DOUT+/- = 0V
RT
Differential Internal Termination Resistance
Differential across DOUT+ and
DOUT-
VDD (MIN) VOD (MAX)
-27
80
100
mA
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
VTH
Differential Threshold High Voltage
VTL
Differential Threshold Low Voltage
VIN
Differential Input Voltage Range
RIN+ - RIN-
180
Input Current
VIN = VDD or 0V,
VDD = 1.89V
-20
±1
+20
µA
Differential Internal Termination Resistance
Differential across RIN+ and
RIN-
80
100
120
Ω
62
90
IIN
RT
Figure 7
+90
-90
mV
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
IDDT
Serializer (Tx)
VDDn Supply Current (includes load
current)
RT = 100Ω
WORST
CASE pattern
Figure 2
VDDn = 1.89V
PCLK = 43 MHz
Default
Registers
mA
RT = 100Ω
RANDOM
PRBS-7
pattern
IDDIOT
IDDTZ
Serializer (Tx)
VDDIO Supply Current (includes load
current)
Serializer (Tx) Supply Current Power-down
IDDIOTZ
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RT = 100Ω
WORST
CASE pattern
Figure 2
PDB = 0V; All
other
LVCMOS
Inputs = 0V
55
VDDIO = 1.89V
PCLK = 43 MHz
Default
Registers
2
VDDIO = 3.6V
PCLK = 43 MHz
Default
Registers
7
15
VDDn = 1.89V
370
775
VDDIO = 1.89V
55
125
VDDIO = 3.6V
65
135
5
mA
µA
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Electrical Characteristics(1) (2)
(continued)
(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
IDDR
IDDIOR
IDDRZ
IDDIORZ
TEST CONDITIONS
Deserializer (Rx) VDDn Supply Current
(includes load current)
Deserializer (Rx) VDDIO Supply Current
(includes load current)
Deserializer (Rx) Supply Current Powerdown
VDDn = 1.89V
CL = 8 pF
WORST
CASE Pattern
Figure 2
PCLK = 43 MHz
SSCG[3:0] =
ON
Default
Registers
VDDn = 1.89V
CL = 8 pF
RANDOM
PRBS-7
Pattern
PCLK = 43 MHz
Default
Registers
VDDIO = 1.89V
CL = 8 pF
WORST
CASE Pattern
Figure 2
PCLK = 43 MHz
Default
Registers
VDDIO = 3.6V
CL = 8 pF
WORST
CASE Pattern
PCLK = 43 MHz
Default
Registers
PDB = 0V; All
other
LVCMOS
Inputs = 0V
VDDn = 1.89V
MIN
TYP
MAX
60
96
UNIT
53
mA
21
32
49
83
42
400
VDDIO = 1.89V
8
40
VDDIO = 3.6V
350
800
µA
6.6 Recommended Serializer Timing for PCLK (1)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
MIN
TYP
MAX
UNIT
23.3
T
100
ns
Transmit Clock Input High Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock Input Low Time
0.4T
0.5T
0.6T
ns
tCLKT
PCLK Input Transition Time
Figure 8
0.5
3
ns
fOSC
Internal oscillator clock source
tTCP
Transmit Clock Period
tTCIH
(1)
TEST CONDITIONS
10 MHz – 43 MHz
25
MHz
Recommended Input Timing Requirements are input specifications and not tested in production.
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Serial Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (See Figure 1)
6.7
Over recommended supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
RECOMMENDED INPUT TIMING REQUIREMENTS
fSCL
SCL Clock Frequency
tLOW
SCL Low Period
tHIGH
MIN
TYP
MAX
UNIT
100
kHz
(1)
>0
fSCL = 100 kHz
4.7
µs
SCL High Period
4.0
µs
tHD:STA
Hold time for a start or a repeated start
condition
4.0
µs
tSU:STA
Set Up time for a start or a repeated
start condition
4.7
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
250
ns
tSU:STO
Set Up Time for STOP Condition
4.0
µs
tr
SCL & SDA Rise Time
1000
tf
SCL & SDA Fall Time
300
ns
Cb
Capacitive load for bus
400
pF
3.45
µs
0
3.45
µs
ns
SWITCHING CHARACTERISTICS (2)
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
tf
SCL & SDA Fall Time
(1)
(2)
0
250
ns
300
ns
Recommended Input Timing Requirements are input specifications and not tested in production.
Specification is ensured by design.
SDA
tf
tHD;STA
tLOW
tr
tr
tBUF
tf
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 1. Serial Control Bus Timing
10
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6.8 Serial Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.7 x
VDDIO
VDDIO
V
GND
0.3 x
VDDIO
V
VIH
Input High Level
SDA and SCL
VIL
Input Low Level Voltage
SDA and SCL
VHY
Input Hysteresis
SDA and SCL
IOZ
TRI-STATE Output Current
PDB = 0V
VOUT = 0V or VDD
-20
±1
+20
µA
IIN
Input Current
SDA or SCL,
Vin = VDDIO or GND
-20
±1
+20
µA
CIN
Input Pin Capacitance
VOL
Low Level Output Voltage
>50
mV
<5
pF
SCL and SDA
VDDIO = 3.0V
IOL = 1.5mA
0.36
V
SCL and SDA
VDDIO = 1.71V
IOL = 1mA
0.36
V
Device Pin Name
Signal Pattern
T
PCLK
(RFB = H)
DIN/ROUT
Figure 2. “Worst Case” Test Pattern
Vdiff
80%
80%
20%
Vdiff = 0V
20%
tLHT
tHLT
Vdiff = (DOUT+) - (DOUT-)
Figure 3. Serializer CML Output Load and Transition Times
DOUT+
100 nF
50:
ZDiff = 100:
SCOPE
BW 8 4.0 GHz
100:
50:
DOUT-
100 nF
Figure 4. Serializer CML Output Load and Transition Times
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DIN
PARALLEL-TO-SERIAL
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
DOUT+
RL
DOUT-
PCLK
Figure 5. Serializer VOD DC Diagram
DOUT-
Single Ended
V
V
OD
V
OD+
ODV
DOUT+
|
OS
0V
Differential
V
OD+
0V
(DOUT+)-(DOUT-)
V
OD-
Figure 6. Serializer VOD DC Diagram
RIN+
RIN+
VTH
VCM
VID
VTL
VIN
VID
VIN
RIN-
RIN-
GND
Figure 7. Differential VTH/VTL Definition Diagram
80%
VDD
80%
PCLK
20%
20%
0V
tCLKT
tCLKT
Figure 8. Serializer Input Clock Transition Times
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tTCP
PCLK
VDDIO/2
tDIS
VDDIO/2
VDDIO/2
tDIH
VDDIO
DINn VDDIO/2
Setup
Hold
VDDIO/2
0V
Figure 9. Serializer Setup/Hold Times
PDB
VDDIO/2
PCLK
tPLD
TRI-STATE
DOUT±
TRI-STATE
Output Active
SYMBOL N+2
| |
SYMBOL N+1
| |
SYMBOL N
| |
DIN
| |
Figure 10. Serializer Data Lock Time
SYMBOL N+3
tSD
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
| |
| |
| |
SYMBOL N
0V
| |
SYMBOL N-4
| |
|
|
|
DOUT+-
|
PCLK
VDDIO/2
Figure 11. Serializer Delay
PDB
VDDIO/2
| |
tDDLT
RIN±
LOCK
TRI-STATE
|
VDDIO/2
Figure 12. Deserializer Data Lock Time
80%
80%
Deserializer
8 pF
lumped
20%
20%
tCLH
tCHL
Figure 13. Deserializer LVCMOS Output Load and Transition Times
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SYMBOL N + 2
SYMBOL N + 3
SYMBOL N + 3
| |
0V
| |
SYMBOL N + 1
| |
SYMBOL N
RIN±
| |
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| |
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
tDD
PCLK
SYMBOL N - 1
| ||
SYMBOL N - 2
| ||
SYMBOL N - 3
| ||
| ||
| ||
ROUTn
VDDIO/2
SYMBOL N
SYMBOL N+1
Figure 14. Deserializer Delay
tRCP
PCLK
VDDIO
1/2 VDDIO
1/2 VDDIO
0V
VDDIO
ROUT[n],
VS, HS
1/2 VDDIO
1/2 VDDIO
0V
tROS
tROH
Figure 15. Deserializer Output Setup/Hold Times
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tRJIT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI
- tRJIT
Figure 16. Receiver Input Jitter Tolerance
Frequency
FPCLK+
fdev (max)
FPCLK
fdev
FPCLK-
fdev (min)
Time
1 / fmod
Figure 17. Spread Spectrum Clock Output Profile
14
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6.9 Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tLHT
CML Low-to-High Transition
Time
RL = 100Ω
Figure 3
150
330
ps
tHLT
CML High-to-Low Transition
Time
RL = 100Ω
Figure 3
150
330
ps
tDIS
Data Input Setup to PCLK
tDIH
Data Input Hold from PCLK
Serializer Data Inputs
Figure 9
tPLD
Serializer PLL Lock Time
RL = 100Ω (1)
tSD
Serializer Delay
RT = 100Ω
PCLK = 10–43 MHz
Register 0x03h b[0] (TRFB = 1)
Figure 11
tJIND
tJINR
tJINT
δSTX
δSTXf
(1)
(2)
(3)
(4)
ns
2.0
ns
(2)
6.386T
+5
1
2
ms
6.386T
+ 12
6.386T
+ 19.7
ns
Serializer Output Deterministic
Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern
PCLK = 43 MHz (3) (4)
0.13
UI
Serializer Output Random Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 43 MHz (3) (4)
0.04
UI
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
PCLK = 43 MHz (3) (4)
0.396
UI
Serializer Jitter Transfer Function PCLK = 43 MHz
-3 dB Bandwidth
Default Registers
Figure 18 (3)
1.90
MHz
Serializer Jitter Transfer Function PCLK = 43 MHz
(Peaking)
Default Registers
Figure 18 (3)
0.944
dB
Serializer Jitter Transfer Function PCLK = 43 MHz
(Peaking Frequency)
Default Registers
Figure 18 (3)
500
kHz
Peak-to-peak Serializer Output
Jitter
λSTXBW
2.0
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
Specification is ensured by design.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
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6.10 Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
tRCP
Receiver Output Clock Period
tRCP = tTCP
PCLK
tPDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
tCLH
LVCMOS Low-to-High Transition
Time
PCLK
tCHL
LVCMOS High-to-Low Transition
Time
VDDIO: 1.71V to 1.89V or
3.0 to 3.6V,
CL = 8 pF (lumped load)
Default Registers
Figure 13 (1)
tCLH
LVCMOS Low-to-High Transition
Time
Deserializer ROUTn
Data Outputs
tCHL
LVCMOS High-to-Low Transition
Time
VDDIO: 1.71V to 1.89V or
3.0 to 3.6V,
CL = 8 pF (lumped load)
Default Registers
Figure 13 (1)
tROS
ROUT Setup Data to PCLK
tROH
ROUT Hold Data to PCLK
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V,
CL = 8 pF (lumped load)
Default Registers
Deserializer ROUTn
Data Outputs
Deserializer Delay
Default Registers
Register 0x03h b[0]
(RRFB = 1)
Figure 14
10 MHz–43 MHz
tDD
tDDLT
Deserializer Data Lock Time
Figure 12
tRJIT
Receiver Input Jitter Tolerance
Figure 16, Figure 19
(3)
tRCJ
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF (1)
(5)
tDPJ
Deserializer Period Jitter
tDCCJ
(2)
(1) (6)
Deserializer Cycle-to-Cycle Clock
Jitter
PCLK
SSCG[3:0] = OFF (1)
fdev
Spread Spectrum Clocking
Deviation Frequency
fmod
Spread Spectrum Clocking
Modulation Frequency
LVCMOS Output Bus
SSC[3:0] = ON
Figure 17
(1)
(2)
(3)
(4)
(5)
(6)
(7)
16
TYP
MAX
UNIT
23.3
T
100
ns
45
50
55
%
1.3
2.0
2.8
1.3
2.0
2.8
1.6
2.4
3.3
1.6
2.4
3.3
0.38T
0.5T
0.38T
0.5T
4.571T
+8
4.571T
+ 12
ns
ns
10 MHz–43 MHz
(4)
PCLK
SSCG[3:0] = OFF
MIN
(7)
43 MHz
ns
4.571T
+ 16
ns
10
ms
0.53
UI
10 MHz
300
550
43 MHz
120
250
10 MHz
425
600
43 MHz
320
480
10 MHz
320
500
43 MHz
300
500
ps
ps
ps
20 MHz–43 MHz
±0.5% to
±2.0%
%
20 MHz–43 MHz
9 kHz to
66 kHz
kHz
Specification is ensured by characterization and is not tested in production.
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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6.11 Typical Characteristics
2
0.62
0.61
-2
JITTER AMPLITUDE (UI)
JITTER TRANSFER (dB)
0
-4
-6
-8
-10
-12
0.60
0.59
0.58
0.57
0.56
0.55
-14
0.54
-16
0.53
-18
1.0E+04
1.0E+05
1.0E+06
1.0E+07
MODULATION FREQUENCY (Hz)
Figure 18. Typical Serializer Jitter
Transfer Function Curve at 43 MHz
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0.52
1.0E+04
1.0E+05
1.0E+06
1.0E+07
JITTER FREQUENCY (Hz)
Figure 19. Typical Deserializer Input Jitter
Tolerance Curve at 43 MHz
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7 Detailed Description
7.1 Overview
The DS90UR903Q/904Q FPD-Link II chipset is intended for video display applications. The Serializer/
Deserializer chipset operates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UR903Q transforms a
21-bit wide parallel LVCMOS data bus into a single high-speed differential pair. The high-speed serial bit stream
contains an embedded clock and DC-balance information which enhances signal quality to support AC coupling.
The DS90UR904Q receives the single serial data stream and converts it back into a 21-bit wide parallel data
bus.
7.2 Functional Block Diagram
7.2.1 Typical Application Diagram
FPD-Link II
Parallel
Data In
18+3
Graphics
Controller
-Video
Processor
Parallel
Data Out
18+3
Display
Module
DS90UR903Q
DS90UR904Q
SCL
SDA
SCL
SDA
Deserializer
Serializer
Figure 20. Typical Application Circuit
DOUT+
RIN+
DOUT-
RIN-
RT
RT
Output Latch
RT
Decoder
RT
Deserializer
Serializer
Encoder
R/G/B[5:0], 21
HS,VS,DE
Input Latch
7.2.2 Block Diagrams
21 R/G/B[5:0],
HS,VS,DE
PCLK
PCLK
PDB
MODE
PLL
Clock
Gen
CDR
Timing
and
Control
PDB
Clock
Gen
LOCK
Timing
and
Control
MODE
SDA
SDA
SCL
SCL
ID[x]
ID[x]
DS90UR903Q - SERIALIZER
DS90UR904Q - DESERIALIZER
Figure 21. Block Diagram
18
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DS90UR903Q
Serializer
FPD-Link II
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
Graphics
Controller
--Video
Processor
PCLK
DS90UR904Q
Deserializer
Timing
Controller
PLL
LCD
Display
PDB
MODE
PDB
MODE
Config.
PC
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
Config.
SDA
SCL
SDA
SCL
PC
Figure 22. Application Block Diagram
7.3 Feature Description
7.3.1 Serial Frame Format
The DS90UR903Q/904Q chipset will transmit and receive a pixel of data in the following format:
CLK0
CLK1
Bit 0 to Bit 20
Figure 23. Serial Bitstream for 28-bit Symbol
The High Speed Serial Channel is a 28-bit symbol composed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the
serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal
transmission over an AC coupled link. Data is randomized, balanced and scrambled.
7.3.2 Signal Quality Enhancers
7.3.2.1 Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting.
7.3.3 Emi Reduction
7.3.3.1 Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a
defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching
simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall
EMI.
7.3.3.2 Des Spread Spectrum Clocking
The DS90UR904Q parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and
±0.5%–±2% from 20 MHz to 43 MHz. The modulation rate and modulation frequency variation of output spread is
controlled through the SSC control registers.
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7.4 Device Functional Modes
7.4.1 LVCMOS VDDIO Option
1.8V or 3.3V SER Inputs and DES Outputs are user selectable to provide compatibility with 1.8V and 3.3V
system interfaces.
7.4.2 Powerdown
The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host
and is used to disable the Link to save power when the remote device is not operational. An auto mode is also
available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the
PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and
transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (High).
The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system
and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied
High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again,
the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the
Data and PCLK outputs are set by the OSS_SEL control register.
7.4.3 Pixel Clock Edge Select (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the Falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 24. Programmable PCLK Strobe Select
7.5 Programming
7.5.1 Description of Serial Control Bus
An integrated I2C slave controller is embedded in each of the DS90UR903Q Serializer and DS90UR904Q
Deserializer. It must be used to access and program the extra features embedded within the configuration
registers. Refer to Table 3 and Table 4 for details of control registers.
7.5.2 ID[X] Address Decoder
The ID[x] pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
20
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Programming (continued)
1.8V
10k
VDDIO
ID[x]
RPU
RPU
RID
HOST
SCL
SCL
SDA
SDA
SER
or
DES
To other
Devices
Figure 25. Serial Control Bus Connection
Table 1. ID[x] Resistor Value – DS90UR903Q
ID[x] RESISTOR VALUE - DS90UR903Q Ser
RESISTOR RID Ω (±0.1%)
ADDRESS 7'b (1)
ADDRESS 8'b 0 APPENDED (WRITE)
0
GND
7b' 101 1000 (h'58)
8b' 1011 0000 (h'B0)
2.0k
7b' 101 1001 (h'59)
8b' 1011 0010 (h'B2)
4.7k
7b' 101 1010 (h'5A)
8b' 1011 0100 (h'B4)
8b' 1011 0110 (h'B6)
(1)
8.2k
7b' 101 1011 (h'5B)
12.1k
7b' 101 1100 (h'5C)
8b' 1011 1000 (h'B8)
39.0k
7b' 101 1110 (h'5E)
8b' 1011 1100 (h'BC)
Specification is ensured by design.
Table 2. ID[x] Resistor Value – DS90UR904Q
ID[x] RESISTOR VALUE - DS90UR904Q Des
RESISTOR RID Ω (±0.1%)
ADDRESS 7'b (1)
ADDRESS 8'b 0 APPENDED (WRITE)
0
GND
7b' 110 0000 (h'60)
8b' 1100 0000 (h'C0)
2.0k
7b' 110 0001 (h'61)
8b' 1100 0010 (h'C2)
4.7k
7b' 110 0010 (h'62)
8b' 1100 0100 (h'C4)
8b' 1101 0110 (h'C6)
(1)
8.2k
7b' 110 0011 (h'63)
12.1k
7b' 110 0100 (h'64)
8b' 1101 1000 (h'C8)
39.0k
7b' 110 0110 (h'66)
8b' 1100 1100 (h'CC)
Specification is ensured by design.
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7.6 Register Maps
Table 3. DS90UR903Q Control Registers
ADDR
(HEX)
0
1
2
3
NAME
FIELD
7:1
DEVICE ID
0
SER ID SEL
7:3
RESERVED
2
RESERVED
1
DIGITAL
RESET0
0
DIGITAL RESET1
2
I C Device ID
Reset
R/W
RW
DEFAULT
0xB0'h
DESCRIPTION
7-bit address of Serializer; 0x58'h
(1011_000X'b) default
0: Device ID is from ID[x]
1: Register I2C Device ID overrides ID[x]
0x00'h
Reserved
RW
0
Reserved
RW
0
self clear
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
RW
0
self clear
1: Digital Reset, retains all register values
Reserved
7:0
RESERVED
0x20'h
Reserved
Reserved
7:6
RESERVED
11'b
Reserved
VDDIO Control
5
VDDIO CONTOL
RW
1
Auto VDDIO detect
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO Mode
4
VDDIO MODE
RW
1
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
RESERVED
3
RESERVED
RW
1
Reserved
RESERVED
2
RESERVED
0
Reserved
1
Switch over to internal 25 MHz Oscillator clock in the
absence of PCLK
0: Disable
1: Enable
1
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
TRFB 0 TRFB RW 1 Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
PCLK_AUTO
1
PCLK_AUTO
TRFB
RW
TRFB
0
4
Reserved
7:0
RESERVED
0x80'h
Reserved
5
Reserved
7:0
RESERVED
RW
0x40'h
Reserved
6
Reserved
7:0
RESERVED
RW
0xC0'h
Reserved
7
Reserved
7:0
RESERVED
RW
0x00'h
Reserved
8
Reserved
7:0
RESERVED
0x00'h
Reserved
9
Reserved
7:0
RESERVED
0x01'h
Reserved
A
Reserved
7:0
RESERVED
0x00'h
Reserved
B
Reserved
7:0
RESERVED
0x00'h
Reserved
Reserved
7:3
RESERVED
0x00'h
Reserved
PCLK Detect
2
PCLK DETECT
RW
Reserved
3
RESERVED
Reserved
0
RESERVED
D
Reserved
7:0
E
Reserved
F
Reserved
10
0
1: Valid PCLK detected
0: Valid PCLK not detected
0
Reserved
0
Reserved
RESERVED
0x11'h
Reserved
7:0
RESERVED
0x01'h
Reserved
7:0
RESERVED
0x03'h
Reserved
Reserved
7:0
RESERVED
0x03'h
Reserved
11
Reserved
7:0
RESERVED
0x03'h
Reserved
12
Reserved
7:0
RESERVED
0x03'h
Reserved
C
22
BITS
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R
R
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Register Maps (continued)
Table 3. DS90UR903Q Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
RW
0x00'h
DESCRIPTION
GPCR[7]
GPCR[6]
GPCR[5]
13
General Purpose
Control Reg
7:0
GPCR[4]
GPCR[3]
0: LOW
1: HIGH
GPCR[2]
GPCR[1]
GPCR[0]
Table 4. DS90UR904Q Control Registers
ADDR
(HEX)
0
1
NAME
BITS
FIELD
R/W
DEFAULT
RW
0xC0'h
7:1
DEVICE ID
7-bit address of Deserializer;
0x60h
(1100_000X) default
0
DES ID SEL
0: Device ID is from ID[x]
1: Register I2C Device ID overrides ID[x]
7:3
RESERVED
2
RESERVED
I2C Device ID
Reset
DESCRIPTION
0x00'h
Reserved
RW
0
Reserved
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
1: Digital Reset, retains all register values
1
DIGITALRESET0
RW
0
self clear
0
DIGITALRESET1
RW
0
self clear
RESERVED
7:6
RESERVED
00'b
Auto Clock
5
AUTO_CLOCK
RW
0
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
OSS Select
4
OSS_SEL
RW
0
Output Sleep State Select
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
2
SSCG
3:0
SSCG
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0000'b
Reserved
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
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Table 4. DS90UR904Q Control Registers (continued)
ADDR
(HEX)
3
NAME
BITS
RESERVED
7:6
VDDIO Control
5
VDDIO CONTROL
RW
1
Auto voltage control
0: Disable
1: Enable (auto detect mode)
VDDIO Mode
4
VDDIO MODE
RW
0
VDDIO voltage set
0: 1.8V
1: 3.3V
RESERVED
3
RESERVED
RW
1
Reserved
RESERVED
2
RESERVED
RW
0
Reserved
RESERVED
1
RESERVED
0
Reserved
1
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
RRFB
R/W
RESERVED
RRFB
DEFAULT
11'b
RW
DESCRIPTION
Reserved
0x00'h
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
RESERVED
0x00'h
Reserved
RESERVED
0
Reserved
RW
000'b
Reserved
RW
1111'b
Reserved
RESERVED
RW
0xB0'h
Reserved
7:0
RESERVED
RW
0x00'h
Reserved
7:0
RESERVED
0x00'h
Reserved
RESERVED
7:0
RESERVED
0x01'h
Reserved
1A
RESERVED
7:0
RESERVED
0x00'h
Reserved
1B
RESERVED
7:0
RESERVED
0x00'h
Reserved
RESERVED
7:3
RESERVED
0x00'h
Reserved
RESERVED
2
RESERVED
0
Reserved
Signal Detect
Status
1
R
0
0: Active signal not detected
1: Active signal detected
LOCK Pin Status
0
R
0
0: CDR/PLL Unlocked
1: CDR/PLL Locked
1D
Reserved
7:0
RESERVED
0x17'h
Reserved
1E
Reserved
7:0
RESERVED
0x07'h
Reserved
1F
Reserved
7:0
RESERVED
0x01'h
Reserved
20
Reserved
7:0
RESERVED
0x01'h
Reserved
21
Reserved
7:0
RESERVED
0x01'h
Reserved
22
Reserved
7:0
RESERVED
0x01'h
Reserved
7:0
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
0x00'h
0: LOW
1: HIGH
4
EQ Control
7:0
EQ
5
RESERVED
7:0
RESERVED
7
RESERVED
6:4
RESERVED
RESERVED
3:0
RESERVED
7
RESERVED
7:0
8:17
RESERVED
18
RESERVED
19
6
1C
23
24
0
FIELD
General Purpose
Control Reg
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RW
RW
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Table 4. DS90UR904Q Control Registers (continued)
ADDR
(HEX)
NAME
24
RESERVED
25
RESERVED
26
RESERVED
BITS
FIELD
R/W
0
RESERVED
RW
0
Reserved
7:0
RESERVED
R
0x00'h
Reserved
7:6
RESERVED
RW
00'b
Reserved
5:0
RESERVED
RW
0
Reserved
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DEFAULT
DESCRIPTION
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8 Application and Implementation
8.1 Application Information
The DS90UR903Q/904Q chipset is intended for interface between a host (graphics processor) and a Display. It
supports a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a RGB666 configuration,
18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link.
The DS90UR903Q Serializer accepts a 21-bit parallel data bus. The parallel data is converted into a single
differential link. The DS90UR904Q Deserializer extracts the clock/control information from the incoming data
stream and reconstructs the 21-bit parallel data.
Camera applications are also supported by the DS90UR903Q/904Q chipset. The host controller/processsor is
connected to the deserializer, while the CMOS image sensor provides data to the serializer.
8.2 Typical Applications
DS90UR903Q
Serializer
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
Graphics
Controller
--Video
Processor
PC
DS90UR904Q
Deserializer
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
FPD-Link II
SDA
SCL
Config
Confg
Timing
Controller
SDA
SCL
LCD Display
PC
Figure 26. Typical Display System Diagram
DS90UR903Q
Serializer
DS90UR904Q
Deserializer
ROUT[20:0]
PCLK
DIN[20:0]
PCLK
CMOS
Image
Sensor
SDA
SCL
Config
SDA
SCL
Config
Host
-FPGA
-Video
Processor
Figure 27. Typical Camera System Diagram
8.2.1 Design Requirements
For the typical design applications, use the following as input parameters.
Table 5. Design Parameters
26
Design Parameter
Example Value
VDDIO
1.8 V or 3.3 V
VDDn
1.8 V
AC Coupling Capacitor for DOUT± and RIN±
100 nF
PCLK Frequency
43 MHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Typical Application Connection
Figure 28 shows a typical connection of the DS90UR903Q Serializer for an 18-bit application. The CML outputs
require 0.1 μF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors
are placed near the power supply Terminals. System GPO (General Purpose Output) signals control the PDB
and MODE Terminals. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO Terminal is
connected also to the 1.8V rail. The optional Serial Bus control is used in this example, thus SCL and SDA are
connected to the system and the ID[x] Terminal is connected to a resistor divider.
DS90UR903Q (SER)
VDDIO
VDDIO
C12
VDDT
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
LVCMOS
Parallel
Bus
DIN14
DIN15
DIN16
DIN17
DIN18
DIN19
DIN20
C10
C5
FB3
C11
C6
FB4
C7
FB5
MODE
PDB
RPU
C1
C2
1.8V
10 k:
ID[X]
RID
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
SCL
SDA
Optional
Optional
Serial
FPD-Link II
Interface
DOUT+
DOUT-
RPU
C15
C13
VDDD
FB6
C14
C9
VDDCML
VDDIO
FB7
FB2
VDDPLL
PCLK
LVCMOS
Control
Interface
I2C
Bus
Interface
C4
C3
FB1
C8
1.8V
RES
DAP (GND)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 28. DS90UR903Q Typical Connection Diagram — Pin Control
40-Pin WQFN (RTA Package)
Figure 29 shows a typical connection of the DS90UR904Q Deserializer for an 18-bit application. The CML inputs
utilize 0.1 μF coupling capacitors to the line and the receiver provides internal termination. Bypass capacitors are
placed near the power supply Terminals. System GPO (General Purpose Output) signals control the PDB and
the MODE Terminals. The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO Terminal
is connected to the 3.3 V rail. The optional Serial Bus control is used in this example, thus SCL and SDA are
connected to the system and the ID[x] Terminal is connected to a resistor divider. LOCK is monitored by a
system GPI (General Purpose Input).
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DS90UR904Q (DES)
1.8V
VDDD
C13
C11
FB1
C3
FB2
C4
FB3
C5
FB5
C16
C7
C12
C14
VDDIO2
VDDIO3
C10
VDDPLL
C6
FB6
C9
VDDSSCG
C15
VDDIO1
C8
VDDR
FB4
VDDIO
VDDCML
C1
Serial
FPD-Link II
Interface
RIN+
RINC2
TP_A
RES_PIN38
RES_PIN39
TP_B
LVCMOS
Control
Interface
MODE
PDB
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
LVCMOS
Parallel
Bus
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
PCLK
VDDIO
RPU
I2C
Bus
Interface
RPU
SCL
FB7
LOCK
SDA
FB8
C17
1.8V
C18
Optional
Optional
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C16 = 4.7 PF
C17 - C18 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
10 k:
ID[X]
RES_PIN46
DAP (GND)
RID
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 29. DS90UR904Q Typical Connection Diagram — Pin Control
48-Pin WQFN (RHS Package)
28
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8.2.2.2 AC Coupling
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link II signal path as illustrated in
Figure 30.
DOUT+
RIN+
DOUT-
RIN-
D
R
Figure 30. AC-Coupled Connection
For high-speed FPD-Link II transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
8.2.2.3 Power Up Requirements and PDB PIN
When power is applied, the VDDIO supply needs to reach the expected operating voltage (1.8V or 3.3V) before
the other supplies (VDDn) begin to ramp. It is also required to delay and release the PDB input signal after VDD
(VDDn and VDDIO) power supplies have settled to the recommended operating voltages. A external RC network
can be connected to the PDB pin to ensure PDB arrives after all the VDD have stabilized.
1.8V OR 3.3V
VDDIO
1.8V
VDD_CORE,
All other 1.8V Supplies
1.8V OR 3.3V
PDB
Figure 31. Power Up Sequence
8.2.2.4 Transmission Media
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for FPD-Link II interface should present a differential impedance of 100 Ohms. Use of cables
and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or
un-shielded cables may be used depending upon the noise environment and application requirements. The
chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling
rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. Other
cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk
and pair-to-pair skew.
For obtaining optimal performance, we recommend:
• Use Shielded Twisted Pair (STP) cable
• 100Ω differential impedance and 24 AWG (or lower AWG) cable
• Low skew, impedance matched
• Ground and/or terminate unused conductors
Figure 32 shows the Typical Performance Characteristics demonstrating various lengths and data rates using
Rosenberger HSD and Leoni DACAR 538 Cable.
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70
1960
60
1680
50
1400
40
1120
30
840
DS90UR903Q/904Q
20
560
10
280
0
0
5
15
20
10
CABLE LENGTH (m)
MAX RAW SERIAL RATE (Mbps)
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PCLK FREQUENCY (MHz)
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
0
25
*Note: Equalization is enabled for cable lengths greater than 7 meters
Figure 32. Rosenberger HSD & Leoni DACAR 538 Cable Performance
8.2.2.5 Serial Interconnect Guidelines
For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008)
and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
Time (200 ps/DIV)
Figure 33. Serializer Eye Diagram at 1.2 Gbps Line Rate
(43MHz Pixel Clock)
30
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43 MHz TX Pixel Clock Input
(1 V/DIV)
Magnitude (80 mV/DIV)
CML Serializer Data Throughput
(200 mV/DIV)
8.2.2.6 Application Curves
Time (4 ns/DIV)
Figure 34. Serializer CML Output with 43MHz TX Pixel
Clock
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9 Power Supply Recommendations
These devices are designed to operate from an input core voltage supply of 1.8V. Some devices provide
separate power and ground Terminals for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal
Description tables typically provide guidance on which circuit blocks are connected to which power Terminal
pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.
Copyright © 2011–2014, Texas Instruments Incorporated
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SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
10 Layout
10.1 Layout Guidelines
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to
ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled
lines will also radiate less.
Information on the LLP style package is provided in the AN-1187 Leadless Leadframe Package (LLP) Application
Report (literature number SNOA401).
10.2 Layout Example
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the LLP package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
32
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DS90UR903Q-Q1, DS90UR904Q-Q1
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SNLS346C – AUGUST 2011 – REVISED JUNE 2014
Layout Example (continued)
Figure 35. No Pullback LLP, Single Row Reference Diagram
Table 6. No Pullback LLP Stencil Aperture Summary for DS90UR903Q-Q1 and DS90UR904Q-Q1
PCB
Pitch
(mm)
PCB DAP
size(mm)
Stencil I/O
Aperture
(mm)
Stencil
DAP
Aperture
(mm)
Number of
DAP
Aperture
Openings
Gap
Between
DAP
Aperture
(Dim A
mm)
Device
Pin
Count
MKT Dwg
PCB I/O
Pad Size
(mm)
DS90UR903Q-Q1
40
SNA40A
0.25 x 0.6
0.5
4.6 x 4.6
0.25 x 0.7
1.0 x 1.0
16
0.2
DS90UR904Q-Q1
48
SNA48A
0.25 x 0.6
0.5
5.1 x 5.1
0.25 x 0.7
1.1 x 1.1
16
0.2
Figure 36. 48-Pin WQFN Stencil Example of Via and Opening Placement
The following PCB layout examples are derived from the layout design of the DS90UB903Q-Q1 and
DS90UB904Q-Q1 in the SERDESUB-21USB Evaluation Module User's Guide ( SNLU101). These graphics and
additional layout description are used to demonstrate both proper routing and proper solder techniques when
designing in the Ser/Des pair.
Copyright © 2011–2014, Texas Instruments Incorporated
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Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
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DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
Figure 37. DS90UR903Q-Q1 Serializer Example Layout
Figure 38. DS90UR904Q-Q1 Deserializer Example Layout
34
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Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Soldering Specifications Application Report, SNOA549
• IC Package Thermal Metrics Application Report, SPRA953
• Channel-Link PCB and Interconnect Design-In Guidelines, SNLA008
• Transmission Line RAPIDESIGNER Operation and Application Guide, SNLA035
• Leadless Leadframe Package (LLP) Application Report, SNOA401
• LVDS Owner's Manual, SNLA187
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DS90UR903Q-Q1
Click here
Click here
Click here
Click here
Click here
DS90UR904Q-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2014, Texas Instruments Incorporated
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Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
35
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90UR903QSQ/NOPB
ACTIVE
WQFN
RTA
40
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR903QSQ
DS90UR903QSQE/NOPB
ACTIVE
WQFN
RTA
40
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR903QSQ
DS90UR903QSQX/NOPB
ACTIVE
WQFN
RTA
40
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR903QSQ
DS90UR904QSQ/NOPB
ACTIVE
WQFN
RHS
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR904QSQ
DS90UR904QSQE/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR904QSQ
DS90UR904QSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR904QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS90UR903QSQ/NOPB
Package Package Pins
Type Drawing
WQFN
RTA
40
DS90UR903QSQE/NOPB WQFN
RTA
DS90UR903QSQX/NOPB WQFN
RTA
WQFN
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
40
250
178.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
40
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
RHS
48
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
DS90UR904QSQE/NOPB WQFN
RHS
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
DS90UR904QSQX/NOPB WQFN
RHS
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
DS90UR904QSQ/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UR903QSQ/NOPB
WQFN
RTA
40
1000
367.0
367.0
38.0
DS90UR903QSQE/NOPB
WQFN
RTA
40
250
210.0
185.0
35.0
DS90UR903QSQX/NOPB
WQFN
RTA
40
2500
367.0
367.0
38.0
DS90UR904QSQ/NOPB
WQFN
RHS
48
1000
367.0
367.0
38.0
DS90UR904QSQE/NOPB
WQFN
RHS
48
250
210.0
185.0
35.0
DS90UR904QSQX/NOPB
WQFN
RHS
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHS0048A
WQFN - 0.8 mm max height
SCALE 1.800
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
A
B
PIN 1 INDEX AREA
0.5
0.3
7.15
6.85
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
(0.2)
5.1 0.1
(A) TYP
24
13
44X 0.5
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
12
25
EXPOSED
THERMAL PAD
2X
5.5
49
SYMM
SEE TERMINAL
DETAIL
1
PIN 1 ID
(OPTIONAL)
36
48
37
SYMM
48X
0.5
0.3
48X
0.30
0.18
0.1
0.05
C A B
4214990/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 5.1)
SYMM
37
48
48X (0.6)
1
36
48X (0.25)
(1.05) TYP
44X (0.5)
(1.25) TYP
49
SYMM
(6.8)
(R0.05)
TYP
( 0.2) TYP
VIA
25
12
13
24
(1.25)
TYP
(1.05)
TYP
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214990/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.625) TYP
(1.25)
TYP
37
48
48X (0.6)
1
36
49
48X (0.25)
44X (0.5)
(1.25)
TYP
(0.625) TYP
SYMM
(6.8)
(R0.05) TYP
METAL
TYP
25
12
13
16X
( 1.05)
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4214990/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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