Texas Instruments | PCA9554 Remote 8-Bit I2C and SMBus I/O Expander With Interrupt Output (Rev. C) | Datasheet | Texas Instruments PCA9554 Remote 8-Bit I2C and SMBus I/O Expander With Interrupt Output (Rev. C) Datasheet

Texas Instruments PCA9554 Remote 8-Bit I2C and SMBus I/O Expander With Interrupt Output (Rev. C) Datasheet
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PCA9554
SCPS128C – JULY 2006 – REVISED JUNE 2014
PCA9554 Remote 8-Bit I2C AND SMBus I/O Expander With Interrupt Output and
Configuration Registers
1 Features
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1
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•
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2 Description
This 8-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC
operation. It provides general-purpose remote I/O
expansion for most microcontroller families via the I2C
interface [serial clock (SCL), serial data (SDA)].
2
I C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
Operating Power-Supply Voltage Range of 2.3 V
to 5.5 V
5-V Tolerant I/Os
400-kHz Fast I2C Bus
Three Hardware Address Pins Allow up to Eight
Devices on the I2C/SMBus
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power-Up With All Channels Configured as Inputs
No Glitch On Power Up
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The PCA9554 consists of one 8-bit Configuration
(input or output selection), Input, Output, and Polarity
Inversion (active high or active low) registers. At
power on, the I/Os are configured as inputs with a
weak pullup to VCC. However, the system master can
enable the I/Os as either inputs or outputs by writing
to the I/O configuration bits. The data for each input
or output is kept in the corresponding Input or Output
register. The polarity of the Input Port register can be
inverted with the Polarity Inversion register. All
registers can be read by the system master.
The system master can reset the PCA9554 in the
event of a timeout or other improper operation by
utilizing the power-on reset feature, which puts the
registers in their default state and initializes the
I2C/SMBus state machine.
The PCA9554 open-drain interrupt (INT) output is
activated when any input state differs from its
corresponding Input Port register state and is used to
indicate to the system master that an input state has
changed.
Device Information(1)
PART NUMBER
PCA9554
PACKAGE
BODY SIZE (NOM)
SSOP (16)
6.20 mm × 5.30 mm
VQFN (16)
4.00 mm × 4.00 mm
QFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4
13
5
12
6
11
7
10
8
9
SDA
A0
A1
A0
VCC
SDA
14
16 15 14 13
A2 1
12 SCL
P0 2
11
P1 3
10 P7
P2 4
INT
9 P6
5
6
7
8
A2
P0
P1
P2
16 15 14 13
12 SCL
11 INT
2
3
10 P7
9 P6
4
5 6 7 8
1
P3
GND
P4
P5
3
VCC
SDA
SCL
INT
P7
P6
P5
P4
P5
15
P4
16
2
P3
1
RGT PACKAGE
(TOP VIEW)
GND
A0
A1
A2
P0
P1
P2
P3
GND
VCC
RGV PACKAGE
(TOP VIEW)
A1
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9554
SCPS128C – JULY 2006 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
2
3
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
6
6
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 13
8.1 Functional Block Diagram ....................................... 13
8.2 Device Functional Modes........................................ 14
8.3 Programming........................................................... 15
9
Application And Implementation........................ 21
9.1 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 23
10.1 Power-On Reset Errata......................................... 23
11 Device and Documentation Support ................. 24
11.1 Trademarks ........................................................... 24
11.2 Electrostatic Discharge Caution ............................ 24
11.3 Glossary ................................................................ 24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
3 Revision History
Changes from Revision B (August 2008) to Revision C
Page
•
Added Interrupt Errata section.............................................................................................................................................. 15
•
Added Power-On Reset Errata section. ............................................................................................................................... 23
2
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SCPS128C – JULY 2006 – REVISED JUNE 2014
4 Description (Continued)
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9554 can remain a simple slave device.
The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current
consumption.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus.
The PCA9554 is pin-to-pin and I2C address compatible with the PCF8574. However, software changes are
required, due to the enhancements in the PCA9554 over the PCF8574.
The PCA9554 and PCA9554A are identical except for their fixed I2C address. This allows for up to 16 of these
devices (eight of each) on the same I2C/SMBus.
5 Pin Configuration and Functions
4
13
5
12
6
11
7
10
8
9
SDA
VCC
A1
A0
VCC
SDA
14
16 15 14 13
A2 1
12 SCL
P0 2
11
P1 3
10 P7
P2 4
INT
9 P6
5
6
7
8
A2
P0
P1
P2
16 15 14 13
12 SCL
11 INT
2
3
10 P7
9 P6
4
5 6 7 8
1
P3
GND
P4
P5
3
VCC
SDA
SCL
INT
P7
P6
P5
P4
P5
15
P4
16
2
GND
1
RGT PACKAGE
(TOP VIEW)
P3
A0
A1
A2
P0
P1
P2
P3
GND
A0
RGV PACKAGE
(TOP VIEW)
A1
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NAME
QSOP (DBQ)
SOIC (DW),
SSOP (DB),
TSSOP (PW), AND
TVSOP (DGV)
QFN (RGT) AND
QFN (RGV)
A0
1
15
Address input. Connect directly to VCC or ground.
A1
2
16
Address input. Connect directly to VCC or ground.
A2
3
1
Address input. Connect directly to VCC or ground.
P0
4
2
P-port input/output. Push-pull design structure.
P1
5
3
P-port input/output. Push-pull design structure.
P2
6
4
P-port input/output. Push-pull design structure.
P3
7
5
P-port input/output. Push-pull design structure.
GND
8
6
Ground
P4
9
7
P-port input/output. Push-pull design structure.
P5
10
8
P-port input/output. Push-pull design structure.
P6
11
9
P-port input/output. Push-pull design structure.
P7
12
10
P-port input/output. Push-pull design structure.
INT
13
11
Interrupt output. Connect to VCC through a pullup resistor.
SCL
14
12
Serial clock bus. Connect to VCC through a pullup resistor.
SDA
15
13
Serial data bus. Connect to VCC through a pullup resistor.
VCC
16
14
Supply voltage
DESCRIPTION
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SCPS128C – JULY 2006 – REVISED JUNE 2014
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6
UNIT
V
(2)
–0.5
6
V
–0.5
6
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
ICC
–50
mA
Continuous current through GND
–250
mA
Continuous current through VCC
160
mA
DB package
Package thermal impedance (3)
θJA
(1)
(2)
(3)
V
82
DBQ package
90
DGV package
120
DW package
57
N package
67
PW package
108
RGT package
TBD
RGV package
TBD
°C/W
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC
MIN
MAX
2.3
5.5
0.7 × VCC
5.5
2
5.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, P7–P0
–0.5
0.8
Supply voltage
SCL, SDA
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P7–P0
IOL
Low-level output current
P7–P0
TA
Operating free-air temperature
4
A2–A0, P7–P0
–40
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UNIT
V
V
V
–10
mA
25
mA
85
°C
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SCPS128C – JULY 2006 – REVISED JUNE 2014
6.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
IOH = –8 mA
P-port high-level output
voltage (2)
VOH
IOH = –10 mA
SDA
VOL = 0.4 V
VOL = 0.5 V
P port (3)
IOL
VOL = 0.7 V
INT
SCL, SDA
II
A2–A0
VCC
MIN
2.3 V to 5.5 V
–1.2
VPOR
2.3 V
1.8
3V
2.6
4.5 V
3.1
4.75 V
4.1
2.3 V
1.7
3V
2.5
TYP (1)
MAX
1.5
1.65
UNIT
V
V
V
4.5 V
3
4.75 V
4
2.3 V to 5.5 V
3
8
2.3 V
8
10
3V
8
14
4.5 V
8
17
4.75 V
8
35
2.3 V
10
13
3V
10
19
4.5 V
10
24
4.75 V
10
45
VOL = 0.4 V
2.3 V to 5.5 V
3
10
VI = VCC or GND
2.3 V to 5.5 V
mA
±1
±1
μA
IIH
P port
VI = VCC
2.3 V to 5.5 V
1
μA
IIL
P port
VI = GND
2.3 V to 5.5 V
–100
μA
VI = VCC, IO = 0, I/O = inputs,
fscl = 400 kHz, No load
Operating mode
VI = VCC, IO = 0, I/O = inputs,
fscl = 100 kHz, No load
ICC
VI = GND, IO = 0, I/O = inputs,
fscl = 0 kHz, No load
Standby mode
VI = VCC, IO = 0, I/O = inputs,
fscl = 0 kHz, No load
ΔICC
Ci
Cio
(1)
(2)
(3)
Additional current in
standby mode
SCL
SDA
P port
5.5 V
104
175
3.6 V
50
90
2.7 V
20
65
5.5 V
60
150
3.6 V
15
40
2.7 V
8
20
5.5 V
450
700
3.6 V
300
600
2.7 V
225
500
5.5 V
0.25
1
3.6 V
0.2
0.9
2.7 V
0.1
0.8
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
Every LED I/O at VI = 4.3 V,
fscl = 0 kHz
5.5 V
μA
1.5
mA
VI = VCC or GND
2.3 V to 5.5 V
VIO = VCC or GND
2.3 V to 5.5 V
1
4
5
5.5
6.5
8
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
The total current sourced by all I/Os must be limited to 85 mA.
Each I/O must be externally limited to a maximum of 25 mA, and the P port (P0 to P7) must be limited to a maximum current of 200 mA.
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6.5 I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 14)
STANDARD MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
FAST MODE
I2C BUS
MAX
0
400
μs
1.3
50
50
250
100
0
kHz
μs
0.6
4.7
2
UNIT
MIN
ns
ns
tsdh
I C serial-data hold time
ticr
I2C input rise time
1000
20 + 0.1Cb
(1)
300
ns
ticf
I2C input fall time
300
20 + 0.1Cb
(1)
300
ns
tocf
I2C output fall time
300
20 + 0.1Cb
(1)
300
ns
10-pF to 400-pF bus
2
0
ns
tbuf
I C bus free time between stop and start
4.7
1.3
μs
tsts
I2C start or repeated start condition setup
4.7
0.6
μs
tsth
I2C start or repeated start condition hold
4
0.6
μs
2
tsps
I C stop condition setup
tvd(data)
Valid data time
SCL low to SDA output
valid
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low
to SDA (out) low
Cb
(1)
4
0.6
μs
300
50
ns
0.3
2
I C bus capacitive load
3.45
0.1
400
0.9
μs
400
ns
Cb = Total capacitive load of one bus in pF
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 15 and Figure 16)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
STANDARD MODE
I2C BUS
MIN
MAX
FAST MODE
I2C BUS
MIN
UNIT
MAX
tiv
Interrupt valid time
P port
INT
4
4
μs
tir
Interrupt reset delay time
SCL
INT
4
4
μs
tpv
Output data valid
SCL
P7–P0
200
200
ns
tps
Input data setup time
P port
SCL
100
100
ns
tph
Input data hold time
P port
SCL
1
1
μs
6
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6.7 Typical Characteristics
35
55
50
VCC = 5 V
30
40
f SCL = 400 kHz
I/Os unloaded
35
30
25
VCC = 3.3 V
20
15
VCC = 2.5 V
10
VCC = 5 V
ICC – Supply Current – nA
ICC – Supply Current – µA
45
25
VCC = 3.3 V
20
15
VCC = 2.5 V
10
5
5
SCL = VCC
0
-40
-15
10
35
60
0
-40
85
-15
TA – Free-Air Temperature – °C
Figure 1. Supply Current vs Temperature
35
60
85
Figure 2. Quiescent Supply Current vs Temperature
600
70
f SCL = 400 kHz
I/Os unloaded
60
VCC = 5 V
550
500
450
ICC – Supply Current – µA
ICC – Supply Current – µA
10
TA – Free-Air Temperature – °C
50
40
30
20
400
TA = –40°C
350
300
TA = 25°C
250
200
TA = 85°C
150
100
10
50
0
0
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
1
2
3
4
5
6
7
8
5.5
Number of I/Os Held Low
VCC – Supply Voltage – V
Figure 3. Supply Current vs Supply Voltage
Figure 4. Supply Current vs Number Of I/Os Held Low
30
300
250
VCC = 2.5 V
VCC = 2.5 V, ISINK = 10 mA
25
ISINK – I/O Sink Current – mA
VOL – Output Low Voltage – mV
275
225
200
175
150
VCC = 5 V, ISINK = 10 mA
125
100
75
VCC = 2.5 V, ISINK = 1 mA
50
TA = –40°C
20
TA = 25°C
15
TA = 85°C
10
VCC = 5 V, ISINK = 1 mA
5
25
0
-40
0
-15
10
35
60
0.0
85
0.1
0.2
0.3
0.4
0.5
0.6
0.7
TA – Free-Air Temperature – °C
VOL – Output Low Voltage – V
Figure 5. I/O Output Low Voltage vs Temperature
Figure 6. I/O Sink Current vs Output Low Voltage
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Typical Characteristics (continued)
60
40
VCC = 3.3 V
VCC = 5 V
55
35
50
ISINK – I/O Sink Current – mA
ISINK – I/O Sink Current – mA
TA = –40°C
30
25
TA = 25°C
20
15
TA = 85°C
10
45
TA = –40°C
40
35
TA = 25°C
30
25
TA = 85°C
20
15
10
5
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VOL – Output Low Voltage – V
VOL – Output Low Voltage – V
Figure 7. I/O Sink Current vs Output Low Voltage
Figure 8. I/O Sink Current vs Output Low Voltage
35
275
VCC = 2.5 V
VCC = 2.5 V, IOL = 10 mA
ISOURCE – I/O Source Current – mA
(V CC – V OH ) – Output High Voltage – mV
250
225
200
175
150
125
VCC = 5 V, IOL = 10 mA
100
75
VCC = 2.5 V, IOL = 1 mA
50
VCC = 5 V, IOL = 1 mA
30
TA = –40°C
25
TA = 25°C
20
15
10
25
TA = 85°C
5
0
0
-40
0.0
-15
10
35
60
85
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
TA – Free-Air Temperature – °C
Figure 10. I/O Source Current vs Output High Voltage
Figure 9. I/O Output High Voltage vs Temperature
75
70
50
ISOURCE – I/O Source Current – mA
40
ISOURCE – I/O Source Current – mA
VCC = 3.3 V
45
TA = –40°C
35
TA = 25°C
30
25
20
TA = 85°C
15
10
5
TA = –40°C
45
40
35
30
TA = 25°C
TA = 85°C
25
20
15
10
5
0
0
0.0
8
VCC = 5 V
65
60
55
50
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
(VCC – VOH) – Output High Voltage – V
Figure 11. I/O Source Current vs Output High Voltage
Figure 12. I/O Source Current vs Output High Voltage
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Typical Characteristics (continued)
6
TA = 25°C
VOH – Output High Voltage – V
5
4
IOH = –8 mA
3
IOH = –10 mA
2
1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VCC – Supply Voltage – V
Figure 13. Output High Voltage vs Supply Voltage
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7 Parameter Measurement Information
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
ticf
tbuf
tsts
tPHL
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 14. I2C Interface Load Circuit And Voltage Waveforms
10
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Parameter Measurement Information (continued)
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Bytes)
From Port
R/W
Slave Address
S
0
1
0
0 A2 A1 A0 1
A
1
2
3
4
A
5
6
7
8
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
0.3 × VCC
SCL
Data 2
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
1.5 V
0.3 × VCC
INT
0.3 × VCC
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 15. Interrupt Load Circuit And Voltage Waveforms
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Parameter Measurement Information (continued)
500 W
Pn
2 × VCC
DUT
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P0
A
P7
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note B)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P0
A
tps
P7
0.3 × VCC
tph
0.7 × VCC
1.5 V
0.3 × VCC
Pn
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O pin output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 16. P-Port Load Circuit And Voltage Waveforms
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8 Detailed Description
8.1 Functional Block Diagram
INT
A0
A1
A2
SCL
SDA
13
Interrupt
Logic
LP Filter
1
2
3
14
15
Input
Filter
I2C Bus
Control
P7−P0
Shift
Register
8 Bits
I/O
Port
Write Pulse
VCC
GND
16
8
Power-On
Reset
Read Pulse
A.
Pin numbers shown are for the DB, DBQ, DGV, DW, N, or PW package.
B.
All I/Os are set to inputs at reset.
Figure 17. Logic Diagram
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Functional Block Diagram (continued)
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
Configuration
Register
VCC
Q1
Q
D
FF
Write Configuration
Pulse
100 kW
D
CK Q
Q
FF
Write Pulse
P0 to P7
CK Q
Q2
Output Port
Register
Input Port
Register
D
GND
Input Port
Register Data
Q
FF
Read Pulse
CK Q
INT
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity
Pulse
CK Q
Polarity
Inversion
Register
A.
At power-on reset, all registers return to default values.
Figure 18. Simplified Schematic Of P0 To P7
8.2 Device Functional Modes
8.2.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9554 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released and the PCA9554 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
Refer to the Power-On Reset Errata section.
8.2.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 18) are off, which creates a high-impedance
input with a weak pullup (100 kΩ typ) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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Device Functional Modes (continued)
8.2.3 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to VCC.
8.2.3.1 Interrupt Errata
Description
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I2C command byte (register pointer) written to the device was 00h.
NOTE
This generally means the last operation with the device was a Read of the input
register. However, the command byte may have been written with 00h without ever
going on to read the input register. After reading from the device, if no other command
byte written, it will remain 00h.
2. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high
System Impact
Can cause improper interrupt handling as the Master will see the interrupt as being cleared.
System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9554 device or before reading from another slave device.
NOTE
Software change will be compatible with other versions (competition and TI redesigns) of
this device.
8.3 Programming
8.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 19). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
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Programming (continued)
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 20).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 19).
Any number of data bytes can be transferred from the transmitter to the receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 21). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 19. Definition Of Start And Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 20. Bit Transfer
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Programming (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 21. Acknowledgment On The I2C Bus
8.3.2 Register Map
Table 1. Interface Definition
BYTE
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
L
L
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
I2C slave address
Px I/O data bus
8.3.2.1 Device Address
Figure 22 shows the address byte for the PCA9554.
Slave Address
0
1
0
Fixed
0
A2
A1
A0 R/W
Hardware
Selectable
Figure 22. PCA9554 Address
Table 2. Address Reference
INPUTS
A0
I2C BUS SLAVE ADDRESS
A2
A1
L
L
L
32 (decimal), 20 (hexadecimal)
L
L
H
33 (decimal), 21 (hexadecimal)
L
H
L
34 (decimal), 22 (hexadecimal)
L
H
H
35 (decimal), 23 (hexadecimal)
H
L
L
36 (decimal), 24 (hexadecimal)
H
L
H
37 (decimal), 25 (hexadecimal)
H
H
L
38 (decimal), 26 (hexadecimal)
H
H
H
39 (decimal), 27 (hexadecimal)
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The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
8.3.2.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9554. Two bits of this command byte state the operation (read or write)
and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can
be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by readsuntil a
new command byte has been sent.
0
0
0
0
0
0
B1
B0
Figure 23. Control Register Bits
Table 3. Command Byte
CONTROL REGISTER BITS
B1
B0
COMMAND BYTE
(HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0x00
Input Port Register
Read byte
XXXX XXXX
0
1
0x01
Output Port Register
Read/write byte
1111 1111
1
0
0x02
Polarity Inversion Register
Read/write byte
0000 0000
1
1
0x03
Configuration Register
Read/write byte
1111 1111
8.3.2.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register will be accessed next.
Table 4. Register 0 (Input Port Register) Table
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 5. Register 1 (Output Port Register) Table
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Table 6. Register 2 (Polarity Inversion Register) Table
18
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
0
0
0
0
0
0
0
0
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The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Register 3 (Configuration Register) Table
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
8.3.2.4 Bus Transactions
Data is exchanged between the master and PCA9554 through write and read commands.
8.3.2.4.1 Writes
Data is transmitted to the PCA9554 by sending the device address and setting the least-significant bit to a logic 0
(see Figure 22 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one
write transmission.
SCL
1
2
3
4
5
6
7
8
9
Slave Address
S
SDA
0
1
0
Command Byte
0 A2 A1 A0 0
A
0
0
0
0
0
0
0
1
Data 1
A
A
P
ACK From Slave
ACK From Slave
R/W ACK From Slave
Start Condition
Data to Port
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 24. Write To Output Port Register
<br/>
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
1
0
Start Condition
Command Byte
0 A2 A1 A0 0
R/W
A
0
0
0
0
ACK From Slave
0
0
Data to Register
1 1/0 A
Data
ACK From Slave
A
P
ACK From Slave
Data to
Register
Figure 25. Write To Configuration Or Polarity Inversion Registers
8.3.2.4.2 Reads
The bus master first must send the PCA9554 address with the least-significant bit set to a logic 0 (see Figure 22
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9554 (see Figure 26 and Figure 27). After
a restart, the value of the register defined by the command byte matches the register being accessed when the
restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation
on the number of data bytes received in one read transmission, but when the final byte is received, the bus
master must not acknowledge the data
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1
0
ACK From
Slave
ACK From
Slave
Slave Address
S 0
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0 A2 A1 A0 0
Command Byte
A
A S 0
ACK From
ACK From
Master
Slave Data from Register
Slave Address
1
0
Data
A
Data from Register
NACK From
Master
0 A2 A1 A0 1 A
R/W
R/W
Data
NA P
Last Byte
Figure 26. Read From Register
<br/>
SCL
1
2
3
4
5
6
7
8
9
Data From Port
Slave Address
SDA
S 0
1
Start
Condition
0
0 A2 A1 A0 1
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT
tiv
tir
A.
This figure assumes the command byte has previously been programmed with 00h.
B.
Transfer of data can be stopped at any moment by a Stop condition.
C.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port. See Figure 26 for these details.
Figure 27. Read From Input Port Register
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9 Application And Implementation
9.1 Typical Application
Figure 28 shows an application in which the PCA9554 can be used.
VCC
(5 V)
10 kW
VCC
Master
Controller
10 kW
2 kW
10 kW
100 kW
(y3)
VCC
SDA
SDA
SCL
SCL
INT
INT
P0
Subsystem 1
(e.g., temperature sensor)
P1
INT
P2
RESET
P3
GND
Subsystem 2
(e.g., counter)
PCA9554
P4
A
P5
A2
Controlled Device
(e.g., CBT device)
P6
ENABLE
A1
P7
B
A0
GND
ALARM
Subsystem 3
(e.g., alarm system)
VCC
A.
Device address is configured as 0100000 for this example.
B.
P0, P2, and P3 are configured as outputs.
C.
P1, P4, and P5 are configured as inputs.
D.
P6 and P7 are not used and and have internal 100-kΩ pullup resistors to protect them from floating.
Figure 28. Typical Application
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Typical Application (continued)
9.1.1 Design Requirements
9.1.1.1 Minimizing ICC When I/Os Control Leds
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in
Figure 28. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC. ΔICC in
Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC.
For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when
the LED is off to minimize current consumption. Figure 29 shows a high-value resistor in parallel with the LED.
Figure 30 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VIN at or above VCC and prevent additional supply-current consumption when the LED is off.
VCC
LED
100 kW
VCC
LEDx
Figure 29. High-Value Resistor In Parallel With Led
3.3 V
VCC
5V
LED
LEDx
Figure 30. Device Supplied By A Lower Voltage
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10 Power Supply Recommendations
10.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed below.
System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCA9554DB
ACTIVE
SSOP
DB
16
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
PCA9554DBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
PCA9554DGVR
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
PCA9554DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9554
PCA9554DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9554
PCA9554PW
NRND
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
PCA9554PWG4
NRND
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
PCA9554PWR
NRND
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
PCA9554PWRG4
NRND
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD554
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCA9554DGVR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TVSOP
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
PCA9554DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
PCA9554PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9554DGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
PCA9554DWR
SOIC
DW
16
2000
350.0
350.0
43.0
PCA9554PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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