Texas Instruments | PCA9536 Remote 4-Bit I²C and SMBus I/O Expander With Configuration Registers (Rev. G) | Datasheet | Texas Instruments PCA9536 Remote 4-Bit I²C and SMBus I/O Expander With Configuration Registers (Rev. G) Datasheet

Texas Instruments PCA9536 Remote 4-Bit I²C and SMBus I/O Expander With Configuration Registers (Rev. G) Datasheet
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PCA9536
SCPS125G – APRIL 2006 – REVISED JUNE 2014
PCA9536 Remote 4-Bit I2C and SMBus I/O Expander With Configuration Registers
1 Features
2 Description
•
This 4-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC
operation. It provides general-purpose remote I/O
expansion for most microcontroller families via the I2C
interface [serial clock (SCL), serial data (SDA)].
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Available in the Texas Instruments NanoFree™
Package
Low Standby Current Consumption of 1 μA Max
I2C to Parallel Port Expander
Operating Power-Supply Voltage Range of 2.3 V
to 5.5 V
5-V Tolerant I/O Ports
400-kHz Fast I2C Bus
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
No Glitch on Power Up
Power-Up With All Channels Configured as Inputs
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The PCA9536 features 4-bit Configuration (input or
output selection), Input Port, Output Port, and Polarity
Inversion (active high or active low) registers. At
power on, the I/Os are configured as inputs with a
weak pullup to VCC. However, the system master can
enable the I/Os as either inputs or outputs by writing
to the I/O configuration bits. If no signals are applied
externally to the PCA9536, the voltage level is 1, or
high, because of the internal pullup resistors. The
data for each input or output is stored in the
corresponding Input Port or Output Port register. The
polarity of the Input Port register can be inverted with
the Polarity Inversion register. All registers can be
read by the system master.
The system master can reset the PCA9536 in the
event of a timeout or other improper operation by
utilizing the power-on reset feature, which puts the
registers in their default state and initializes the
I2C/SMBus state machine.
The device's outputs (latched) have high-current drive
capability for directly driving LEDs. It has low current
consumption.
Device Information (1)
PART NUMBER
PCA9536
(1)
1
8
VCC
P1
2
7
SDA
P2
3
6
SCL
GND
4
5
P3
BODY SIZE (NOM)
1.90 mm × 0.90 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
DGK PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
P0
PACKAGE
GSBGA (8)
YZP PACKAGE
(BOTTOM VIEW)
P0
1
8
VCC
P1
2
7
SDA
P2
3
6
SCL
GND
4
5
P3
GND
P2
P1
P0
D1
4 5 D2
C1
3 6 C2
B1
2 7 B2
A1
1 8 A2
P3
SCL
SDA
VCC
See mechanical drawings for dimensions.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9536
SCPS125G – APRIL 2006 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
2
3
4
5.1
5.2
5.3
5.4
5.5
5.6
5.7
4
4
4
5
6
6
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
7
Detailed Description ............................................ 12
7.1 Functional Block Diagram ....................................... 12
7.2 Feature Description................................................. 13
7.3 Programming........................................................... 13
8
Application and Implementation ........................ 19
9
Power Supply Recommendations...................... 20
8.1 Typical Application .................................................. 19
9.1 Power-On Reset Errata........................................... 20
10 Device and Documentation Support ................. 21
10.1 Trademarks ........................................................... 21
10.2 Electrostatic Discharge Caution ............................ 21
10.3 Glossary ................................................................ 21
11 Mechanical, Packaging, and Orderable
Information ........................................................... 21
3 Revision History
Changes from Revision F (September 2008) to Revision G
•
2
Page
Added Power-On Reset Errata section. ............................................................................................................................... 20
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SCPS125G – APRIL 2006 – REVISED JUNE 2014
4 Pin Configuration and Functions
DGK PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
P0
P1
VCC
8
1
SDA
7
2
P2
3
6
SCL
GND
4
5
P3
YZP PACKAGE
(BOTTOM VIEW)
P0
1
8
VCC
P1
2
7
SDA
P2
3
6
SCL
GND
4
5
P3
GND
P2
P1
P0
D1
4 5 D2
C1
3 6 C2
B1
2 7 B2
A1
1 8 A2
P3
SCL
SDA
VCC
See mechanical drawings for dimensions.
Pin Functions
NO.
NAME
1
P0
P-port input/output. Push-pull design structure.
DESCRIPTION
2
P1
P-port input/output. Push-pull design structure.
3
P2
P-port input/output. Push-pull design structure.
4
GND
5
P3
Ground
P-port input/output. Push-pull design structure.
6
SCL
Serial clock bus. Connect to VCC through a pullup resistor.
7
SDA
Serial data bus. Connect to VCC through a pullup resistor.
8
VCC
Supply voltage
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PCA9536
SCPS125G – APRIL 2006 – REVISED JUNE 2014
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5 Specifications
5.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6
UNIT
V
(2)
–0.5
6
V
–0.5
6
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
Continuous current through GND
–200
Continuous current through VCC
160
D package
θJA
(1)
(2)
(3)
Package thermal impedance
(3)
V
mA
97
DGK package
172
YZP package
102
°C/W
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
5.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
MIN
MAX
2.3
5.5
0.7 × VCC
5.5
2
5.5
SCL, SDA
–0.5
0.3 × VCC
P3–P0
–0.5
0.8
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P3–P0
–10
mA
IOL
Low-level output current
P3–P0
25
mA
TA
Operating free-air temperature
85
°C
4
SCL, SDA
P3–P0
–40
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V
V
V
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SCPS125G – APRIL 2006 – REVISED JUNE 2014
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
IOH = –8 mA
P-port high-level
output voltage (2)
VOH
IOH = –10 mA
SDA
VOL = 0.4 V
VOL = 0.5 V
IOL
P-port (3)
VOL = 0.7 V
VCC
MIN
2.3 V to 5.5 V
–1.2
VPOR
2.3 V
1.8
3V
2.6
4.5 V
4.1
4.75 V
4.1
2.3 V
1.7
3V
2.5
3
10
2.3 V
8
10
3V
8
14
4.5 V
8
17
4.75 V
8
32
2.3 V
10
13
3V
10
19
4.5 V
10
24
4.75 V
10
44
μA
2.3 V to 5.5 V
1
μA
2.3 V to 5.5 V
–100
μA
P-port
VI = VCC
P-port
VI = GND
VI = VCC, IO = 0,
I/O = inputs, fscl = 0 kHz
ΔICC
Ci
Cio
(1)
(2)
(3)
Additional current in
standby mode
SCL
SDA
P-port
mA
±1
IIL
Standby mode
5.5 V
73
150
3.6 V
9
50
2.7 V
7
30
5.5 V
14
25
3.6 V
9
20
2.7 V
6
15
5.5 V
225
350
3.6 V
175
250
2.7 V
125
200
5.5 V
0.25
1
3.6 V
0.2
0.9
2.7 V
0.1
0.8
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
0.35
Every LED I/O at VI = 4.3 V,
fscl = 0 kHz
5.5 V
0.4
VI = VCC or GND
VIO = VCC or GND
V
V
2.3 V to 5.5 V
IIH
VI = GND, IO = 0,
I/O = inputs, fscl = 0 kHz
UNIT
V
4
2.3 V to 5.5 V
ICC
1.65
4
VI = VCC or GND
VI = VCC, IO = 0,
I/O = inputs, fscl = 100 kHz
1.5
4.75 V
SCL, SDA
Operating mode
MAX
4.5 V
II
VI = VCC, IO = 0,
I/O = inputs, fscl = 400 kHz
TYP (1)
μA
mA
2.3 V to 5.5 V
2.3 V to 5.5 V
4
5
5
6.5
7.5
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
The total current sourced by all I/Os must be limited to 85 mA.
Each I/O must be limited externally to a maximum of 25 mA, and the P-port (P3–P0) must be limited to a maximum current of 100 mA.
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PCA9536
SCPS125G – APRIL 2006 – REVISED JUNE 2014
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5.5 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 14)
STANDARD MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
FAST MODE
I2C BUS
UNIT
MIN
MAX
0
400
4.7
μs
1.3
50
50
250
2
100
0
kHz
μs
0.6
ns
ns
tsdh
I C serial-data hold time
ticr
I2C input rise time
1000 20 + 0.1Cb
(1)
300
ns
ticf
I2C input fall time
300 20 + 0.1Cb
(1)
300
ns
tocf
I2C output fall time, 10-pF to 400-pF bus
300 20 + 0.1Cb
(1)
300
ns
2
0
ns
tbuf
I C bus free time between Stop and Start
4.7
1.3
μs
tsts
I2C Start or repeated Start condition setup time
4.7
0.6
μs
tsth
I2C Start or repeated Start condition hold time
4
0.6
μs
2
tsps
I C Stop condition setup time
4
tvd(ack)
Valid data time of ACK condition, ACK signal from SCL low to SDA (out)
low
Cb
I2C bus capacitive load
(1)
μs
0.6
tvd(data) Valid data time, SCL low to SDA output valid
1
0.9
μs
1
0.9
μs
400
400
pF
Cb = Total capacitive load of one bus in pF
5.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 15)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
STANDARD MODE
I2C BUS
MIN
MAX
FAST MODE
I2C BUS
MIN
tpv
Output data valid
SCL
P3–P0
tps
Input data setup time
P-port
SCL
100
100
ns
tph
Input data hold time
P-port
SCL
1
1
μs
6
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200
UNIT
MAX
200
ns
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5.7 Typical Characteristics
TA = 25°C (unless otherwise noted)
300
55
VCC = 5 V
50
VCC = 5 V
250
ICC – Supply Current – nA
ICC – Supply Current – µA
45
40
f SCL = 400 kHz
I/Os unloaded
35
30
25
VCC = 3.3 V
20
15
VCC = 2.5 V
10
200
VCC = 3.3 V
150
VCC = 2.5 V
100
50
5
SCL = VCC
0
-50
-25
0
25
50
75
0
-50
100
Figure 1. Supply Current vs Temperature
0
25
50
75
100
Figure 2. Quiescent Supply Current vs Temperature
300
70
f SCL = 400 kHz
I/Os unloaded
60
VCC = 5 V
275
250
ICC – Supply Current – µA
ICC – Supply Current – µA
-25
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
50
40
30
20
225
200
TA = –40°C
175
150
TA = 25°C
125
100
TA = 85°C
75
50
10
25
0
0
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
1
5.5
2
3
4
Number of I/Os Held Low
VCC – Supply Voltage – V
Figure 3. Supply Current vs Supply Voltage
Figure 4. Supply Current vs Number of I/Os Held Low
300
300
VCC = 2.5 V, ISINK = 10 mA
275
(V CC – V OH ) – Output High Voltage – mV
275
VOL – Output Low Voltage – mV
250
225
200
175
150
VCC = 5 V, ISINK = 10 mA
125
100
75
VCC = 2.5 V, ISINK = 1 mA
50
VCC = 5 V, ISINK = 1 mA
25
0
-50
-25
0
25
50
75
250
VCC = 2.5 V, IOL = 10 mA
225
200
175
150
125
VCC = 5 V, IOL = 10 mA
100
75
50
25
0
-50
100
-25
0
25
50
75
100
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 5. I/O Output Low Voltage vs Temperature
Figure 6. I/O Output High Voltage vs Temperature
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
30
40
VCC = 3.3 V
VCC = 2.5 V
35
TA = –40°C
ISINK – I/O Sink Current – mA
ISINK – I/O Sink Current – mA
25
20
TA = 25°C
15
TA = 85°C
10
5
TA = –40°C
30
TA = 25°C
25
20
15
TA = 85°C
10
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VOL – Output Low Voltage – V
VOL – Output Low Voltage – V
Figure 7. I/O Sink Current vs Output Low Voltage
Figure 8. I/O Sink Current vs Output Low Voltage
30
60
VCC = 5 V
VCC = 2.5 V
ISOURCE – I/O Source Current – mA
55
ISINK – I/O Sink Current – mA
50
45
TA = –40°C
40
35
TA = 25°C
30
25
20
TA = 85°C
15
10
25
TA = –40°C
20
TA = 25°C
15
TA = 85°C
10
5
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.7
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
Figure 9. I/O Sink Current vs Output Low Voltage
Figure 10. I/O Source Current vs Output High Voltage
70
45
VCC = 3.3 V
TA = –40°C
ISOURCE – I/O Source Current – mA
ISOURCE – I/O Source Current – mA
VCC = 5 V
65
40
35
30
TA = 25°C
25
20
15
10
TA = 85°C
5
60
55
50
TA = –40°C
45
40
35
TA = 25°C
30
25
TA = 85°C
20
15
10
5
0
0
0.0
8
0.1
VOL – Output Low Voltage – V
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
(VCC – VOH) – Output High Voltage – V
Figure 11. I/O Source Current vs Output High Voltage
Figure 12. I/O Source Current vs Output High Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
6
TA = 25°C
VOH – Output High Voltage – V
5
4
IOH = –8 mA
3
IOH = –10 mA
2
1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VCC – Supply Voltage – V
Figure 13. Output High Voltage vs Supply Voltage
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6 Parameter Measurement Information
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
ticf
tbuf
tsts
tPHL
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A.
CL include probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 14. I2C Interface Load Circuit and Voltage Waveforms
10
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Parameter Measurement Information (continued)
500 W
Pn
DUT
CL = 50 pF
(see Note A)
2 × VCC
500 W
P-PORT LOAD CONFIGURATION
SCL
0.7 × VCC
P0
A
P3
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note B)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
SCL
0.7 × VCC
P0
A
tps
P3
0.3 × VCC
tph
0.7 × VCC
Pn
0.3 × VCC
READ MODE (R/W = 1)
A.
CL include probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 15. P-Port Load Circuit and Voltage Waveforms
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7 Detailed Description
7.1 Functional Block Diagram
SCL
SDA
6
7
I2C Bus
Control
Input
Filter
I/O
Port
4 Bits
Shift
Register
P3−P0
Write Pulse
Read Pulse
VCC
GND
8
Power-On
Reset
4
Figure 16. Logic Diagram
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
Configuration
Register
VCC
Q1
Q
D
FF
Write Configuration
Pulse
CK Q
100 kW
Q
D
FF
Write Pulse
P0 to P3
CK Q
Q2
Output Port
Register
Input Port
Register
GND
Input Port
Register Data
Q
D
FF
Read Pulse
ESD Protection
Diode
CK Q
Data From
Shift Register
D
Write Polarity
Pulse
CK Q
Polarity
Register Data
Q
FF
Polarity
Inversion
Register
Figure 17. Simplified Schematic Of P0 To P3
12
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7.2 Feature Description
7.2.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9536 in a reset condition until
VCC has reached VPOR. At that time, the reset condition is released and the PCA9536 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
Refer to the Power-On Reset Errata section.
7.2.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 17) are off, creating a high-impedance input
with a weak pullup (100 kΩ typ) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
7.3 Programming
7.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 18). After the Start condition, the device address
byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 19).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 18).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 20). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 18. Definition of Start and Stop Conditions
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Programming (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 19. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 20. Acknowledgment on the I2C Bus
7.3.2 Register Map
Table 1. Interface Definition
BYTE
2
I C slave address
Px I/O data bus
14
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
H
L
L
L
L
L
H
R/W
P3
P2
P1
P0
Does not affect operation of the PCA9536
P7
P6
P5
P4
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7.3.2.1 Device Address
Figure 21 shows the address byte of the PCA9536.
Slave Address
1
0
0
0
0
0
1
R/W
Fixed
Figure 21. PCA9536 Address
The slave address equates to 65 (decimal) and 41 (hexadecimal).
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
7.3.2.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9536. Two bits of this data byte state the operation (read or write) and
the internal register (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
0
0
0
0
0
0
B1
B0
Figure 22. Control Register Bits
Table 2. Command Byte
CONTROL REGISTER BITS
B1
B0
COMMAND BYTE
(HEX)
0
0
0x00
0
1
0x01
1
0
0x02
1
1
0x03
PROTOCOL
POWER-UP
DEFAULT
Input Port
Read byte
1111 XXXX
Output Port
Read/write byte
1111 1111
Polarity Inversion
Read/write byte
0000 0000
Configuration
Read/write byte
1111 1111
REGISTER
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7.3.2.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to instruct the I2C device that the
Input Port register will be accessed next.
Table 3. Register 0 (Input Port Register)
I7
BIT
I6
I5
I4
Not Used
DEFAULT
1
1
1
1
I3
I2
I1
I0
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 4. Register 1 (Output Port Register)
O7
BIT
O6
O5
O4
Not Used
DEFAULT
1
1
1
1
O3
O2
O1
O0
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Table 5. Register 2 (Polarity Inversion Register)
N7
BIT
N6
N5
N4
Not Used
DEFAULT
0
0
0
0
N3
N2
N1
N0
0
0
0
0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 6. Register 3 (Configuration Register)
BIT
DEFAULT
16
C7
C6
C5
C4
Not Used
1
1
1
1
C3
C2
C1
C0
1
1
1
1
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7.3.2.4 Bus Transactions
Data is exchanged between the master and PCA9536 through write and read commands.
7.3.2.4.1 Writes
Data is transmitted to the PCA9536 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 21 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission (see Figure 23 and Figure 24).
SCL
1
2
3
4
5
6
7
8
9
Slave Address
S
SDA
1
0
0
0
0
Command Byte
0
1
0
A
0
0
0
0
0
0
Data to Port
0
1
Data 1
A
P
ACK From Slave
ACK From Slave
R/W ACK From Slave
Start Condition
A
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 23. Write to Output Port Register
<br/>
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
1
0
0
Start Condition
0
0
0
Command Byte
1
0
R/W
A
0
0
0
0
ACK From Slave
0
0
Data to Register
1
1
A
Data
ACK From Slave
A
P
ACK From Slave
Data to
Register
Figure 24. Write to Configuration or Polarity Inversion Registers
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7.3.2.4.2 Reads
The bus master first must send the PCA9536 address with the LSB set to a logic 0 (see Figure 21 for device
address). The command byte is sent after the address and determines which register is accessed. After a restart,
the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the
command byte then is sent by the PCA9536 (see Figure 25 and Figure 26). After a restart, the value of the
register defined by the command byte matches the register being accessed when the restart occurred. Data is
clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data
bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
S 1
0
0
0
0
0
ACK From
Slave
ACK From
Slave
Slave Address
1
0
Command Byte
A
A S 1
0
0
0
0
0
1 A
1
A
Data
R/W
At this time, the master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
R/W
ACK From
Master
ACK From
Data from Register
Slave
Slave Address
Data from Register
NACK From Master
NA P
Data
Last Byte
Figure 25. Read From Register
<br/>
1
SCL
2
3
4
5
6
7
8
9
Data From Port
Slave Address
S
SDA
1
0
0
0
0
Start
Condition
0
1
1
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT
tiv
tir
A.
This figure assumes that the command byte previously has been programmed with 00h.
B.
Transfer of data can be stopped at any moment by a Stop condition.
C.
This figure eliminates the command byte transfer, a restart, and the slave address call between the initial slave
address call and actual data transfer from the P-port (see Figure 25).
Figure 26. Read Input Port Register
18
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8 Application and Implementation
8.1 Typical Application
Figure 27 shows an application in which the PCA9536 can be used.
VCC
10 kW
VCC
2 kW
10 kW
VCC
SCL
SCL
Master
SDA
Controller
SDA
Subsystem 1
(e.g., temperature
sensor)
INT
P0
P1
P2
PCA9536
GND
RESET
P3
Subsystem 2
(e.g., counter)
A
GND
Controlled Device
(e.g., CBT device)
ENABLE
B
A.
Device address is 10000001.
B.
P0, P2, and P3 are configured as outputs.
C.
P1 is configured as an input.
Figure 27. Typical Application
8.1.1 Design Requirements
8.1.1.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in
Figure 27. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The supply
current, ICC, increases as VIN becomes lower than VCC and is specified as ΔICC in Electrical Characteristics.
Designs needing to minimize current consumption, such as battery power applications, should consider
maintaining the I/O pins greater than or equal to VCC when the LED is off. Figure 28 shows a high-value resistor
in parallel with the LED. Figure 29 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these
methods maintain the I/O VIN at or above VCC and prevent additional supply-current consumption when the LED
is off.
VCC
LED
100 kW
VCC
Pn
Figure 28. High-Value Resistor in Parallel With the LED
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Typical Application (continued)
3.3 V
VCC
5V
LED
Pn
Figure 29. Device Supplied by a Lower Voltage
9 Power Supply Recommendations
9.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed below.
System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
20
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10 Device and Documentation Support
10.1 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCA9536D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD536
PCA9536DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD536
PCA9536DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(7CF, 7CL)
PCA9536DGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(7CF, 7CL)
PCA9536DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD536
PCA9536DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD536
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PCA9536DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
PCA9536DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
PCA9536DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9536DGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
PCA9536DGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
PCA9536DR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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