Texas Instruments | PCA9539 Remote 16-Bit I2C and SMBus Low-Power I/O Expander, PCA9539 (Rev. G) | Datasheet | Texas Instruments PCA9539 Remote 16-Bit I2C and SMBus Low-Power I/O Expander, PCA9539 (Rev. G) Datasheet

Texas Instruments PCA9539 Remote 16-Bit I2C and SMBus Low-Power I/O Expander, PCA9539 (Rev. G) Datasheet
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PCA9539
SCPS130G – AUGUST 2005 – REVISED JUNE 2014
PCA9539 Remote 16-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output,
Reset, and Configuration Registers
1 Features
•
•
•
•
•
•
•
•
•
1
•
•
•
2 Description
Low Standby-Current Consumption of 1 μA Max
I2C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
Active-Low Reset Input
5-V Tolerant I/O Ports
Compatible With Most Microcontrollers
400-kHz Fast I2C Bus
Polarity Inversion Register
Address by Two Hardware Address Pins for Use
of up to Four Devices
Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
This 16-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC
operation. It provides general-purpose remote I/O
expansion for most microcontroller families via the I2C
interface [serial clock (SCL), serial data (SDA)].
The PCA9539 consists of two 8-bit Configuration
(input or output selection), Input Port, Output Port,
and Polarity Inversion (active-high or active-low
operation) registers. At power-on, the I/Os are
configured as inputs. The system master can enable
the I/Os as either inputs or outputs by writing to the
I/O configuration bits. The data for each input or
output is kept in the corresponding Input or output
register. The polarity of the Input Port register can be
inverted with the Polarity Inversion register. All
registers can be read by the system master.
Device Information(1)
PART NUMBER
PCA9539
PACKAGE
BODY SIZE (NOM)
SSOP (24)
8.20 mm × 5.30 mm
TVSOP (24)
5.00 mm × 4.40 mm
SOIC (24)
15.40 mm × 7.50 mm
TSSOP (24)
7.80 mm × 4.40 mm
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
SDA
SCL
24
2
RESET
A1
INT
VCC
1
24 23 22 21 20 19
P00
P01
P02
P03
P04
P05
1
18 A0
17 P17
2
3
16 P16
15 P15
14 P14
4
5
6
13 P13
7 8 9 10 11 12
P06
P07
GND
P10
P11
P12
INT
A1
RESET
P00
P01
P02
P03
P04
P05
P06
P07
GND
RGE PACKAGE
(TOP VIEW)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9539
SCPS130G – AUGUST 2005 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
2
3
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
6
7
7
7
8
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
I2C Interface Timing Requirements..........................
RESET Timing Requirements...................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 14
8.1 Functional Block Diagram ....................................... 14
8.2 Device Functional Modes........................................ 16
8.3 Programming........................................................... 17
9
Application And Implementation........................ 24
9.1 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 26
10.1 Power-On Reset Requirements ........................... 26
10.2 Power-On Reset Errata......................................... 27
11 Device and Documentation Support ................. 28
11.1 Trademarks ........................................................... 28
11.2 Electrostatic Discharge Caution ............................ 28
11.3 Glossary ................................................................ 28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
3 Revision History
Changes from Revision F (January 2011) to Revision G
Page
•
Added RESET Errata section. .............................................................................................................................................. 16
•
Added Interrupt Errata section.............................................................................................................................................. 17
•
Power-On Reset Errata section............................................................................................................................................ 27
2
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SCPS130G – AUGUST 2005 – REVISED JUNE 2014
4 Description (Continued)
The system master can reset the PCA9539 in the event of a time-out or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. Asserting RESET causes the same reset/initialization to occur without de-powering the part.
The PCA9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9539 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low
current consumption.
The PCA9539 is identical to the PCA9555, except for the removal of the internal I/O pullup resistor, which greatly
reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different address
range.
Two hardware pins (A0 and A1) are used to program and vary the fixed I2C address and allow up to four devices
to share the same I2C bus or SMBus.
5 Pin Configuration and Functions
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
SDA
SCL
24
RESET
A1
INT
VCC
1
24 23 22 21 20 19
P00
P01
P02
P03
P04
P05
1
2
3
18 A0
17 P17
16 P16
4
5
15 P15
14 P14
6
13 P13
7 8 9 10 11 12
P06
P07
GND
P10
P11
P12
INT
A1
RESET
P00
P01
P02
P03
P04
P05
P06
P07
GND
RGE PACKAGE
(TOP VIEW)
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SCPS130G – AUGUST 2005 – REVISED JUNE 2014
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Pin Functions
PIN
NO.
SOIC (DW),
SSOP (DB),
QSOP (DBQ),
TSSOP (PW), AND
TVSOP (DGV)
QFN (RGE)
INT
1
22
Interrupt output. Connect to VCC through a pullup resistor.
A1
2
23
Address input. Connect directly to VCC or ground.
RESET
3
24
Active-low reset input. Connect to VCC through a pullup resistor if no active
connection is used.
P00
4
1
P-port input/output. Push-pull design structure.
P01
5
2
P-port input/output. Push-pull design structure.
P02
6
3
P-port input/output. Push-pull design structure.
P03
7
4
P-port input/output. Push-pull design structure.
P04
8
5
P-port input/output. Push-pull design structure.
P05
9
6
P-port input/output. Push-pull design structure.
P06
10
7
P-port input/output. Push-pull design structure.
P07
11
8
P-port input/output. Push-pull design structure.
GND
12
9
Ground
P10
13
10
P-port input/output. Push-pull design structure.
P11
14
11
P-port input/output. Push-pull design structure.
P12
15
12
P-port input/output. Push-pull design structure.
P13
16
13
P-port input/output. Push-pull design structure.
P14
17
14
P-port input/output. Push-pull design structure.
P15
18
15
P-port input/output. Push-pull design structure.
P16
19
16
P-port input/output. Push-pull design structure.
P17
20
17
P-port input/output. Push-pull design structure.
A0
21
18
Address input. Connect directly to VCC or ground.
NAME
4
DESCRIPTION
SCL
22
19
Serial clock bus. Connect to VCC through a pullup resistor.
SDA
23
20
Serial data bus. Connect to VCC through a pullup resistor.
VCC
24
21
Supply voltage
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SCPS130G – AUGUST 2005 – REVISED JUNE 2014
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6
UNIT
V
(2)
–0.5
6
V
–0.5
6
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
θJP
(2)
(3)
–250
Continuous current through VCC
160
Package thermal impedance, junction to free air (3)
θJA
(1)
Continuous current through GND
Package thermal impedance, junction to pad
DB package
63
DBQ package
61
DGV package
86
DW package
46
PW package
88
RGE package
45
RGE package
1.5
V
mA
°C/W
°C/W
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC
Supply voltage
MIN
MAX
2.3
5.5
SCL, SDA
0.7 × VCC
5.5
A0, A1, RESET, P07–P00, P17–P10
0.7 × VCC
5.5
SCL, SDA
–0.5
0.3 × VCC
A0, A1, RESET, P07–P00, P17–P10
–0.5
0.3 × VCC
UNIT
V
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P07–P00, P17–P10
–10
mA
IOL
Low-level output current
P07–P00, P17–P00
25
mA
TA
Operating free-air temperature
85
°C
–40
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V
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6.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
IOH = –8 mA
P-port high-level output voltage (2)
VOH
IOH = –10 mA
VCC
MIN
2.3 V to 5.5 V
–1.2
VPOR
2.3 V
1.8
3V
2.6
4.75 V
4.1
2.3 V
1.7
3V
2.5
4.75 V
SDA
P port (3)
IOL
INT
SCL, SDA
II
A0, A1, RESET
VOL = 0.4 V
VOL = 0.5 V
VOL = 0.7 V
TYP (1)
MAX
1.5
1.65
UNIT
V
V
V
4
3
2.3 V to 5.5 V
VOL = 0.4 V
8
20
10
24
mA
3
VI = VCC or GND
2.3 V to 5.5 V
±1
±1
μA
IIH
P port
VI = VCC
2.3 V to 5.5 V
1
μA
IIL
P port
VI = GND
2.3 V to 5.5 V
–1
μA
Operating mode
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz
ICC
Standby mode
VI = GND, IO = 0, I/O = inputs,
fSCL = 0 kHz
ΔICC
Additional current in standby mode
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
SCL
VI = VCC or GND
Cio
(1)
(2)
(3)
6
SDA
P port
VIO = VCC or GND
5.5 V
100
200
3.6 V
30
75
2.7 V
20
50
5.5 V
0.5
1
3.6 V
0.4
0.9
2.7 V
0.25
0.8
2.3 V to 5.5 V
2.3 V to 5.5 V
2.3 V to 5.5 V
μA
200
μA
3
7
pF
3
7
3.7
9.5
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum
current of 100 mA, for a device total of 200 mA.
The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
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SCPS130G – AUGUST 2005 – REVISED JUNE 2014
I2C Interface Timing Requirements
6.5
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
MIN
MAX
UNIT
0
400
kHz
2
fscl
I C clock frequency
tsch
I2C clock high time
0.6
tscl
I2C clock low time
1.3
tsp
I2C spike time
I C serial-data setup time
tsdh
I2C serial-data hold time
ticr
I2C input rise time
μs
50
2
tsds
μs
100
ns
0
2
ns
ns
20 + 0.1Cb
(1)
300
ns
20 + 0.1Cb
(1)
300
ns
20 + 0.1Cb
(1)
300
ticf
I C input fall time
tocf
I2C output fall time
tbuf
I2C bus free time between Stop and Start
1.3
μs
tsts
I2C Start or repeated Start condition setup
0.6
μs
tsth
I2C Start or repeated Start condition hold
0.6
μs
tsps
I2C Stop condition setup
0.6
μs
tvd(data)
Valid-data time
SCL low to SDA output valid
50
ns
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low to SDA (out) low
0.1
Cb
I2C bus capacitive load
(1)
10-pF to 400-pF bus
ns
0.9
μs
400
pF
Cb = total capacitance of one bus line in pF
6.6 RESET Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 16)
MIN
MAX
UNIT
tW
Reset pulse duration
6
ns
tREC
Reset recovery time
0
ns
tRESET
Time to reset
400
ns
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 14 and Figure 15)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
tiv
Interrupt valid time
P port
INT
4
μs
tir
Interrupt reset delay time
SCL
INT
4
μs
tpv
Output data valid
SCL
P port
200
ns
tps
Input data setup time
P port
SCL
150
ns
tph
Input data hold time
P port
SCL
1
μs
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6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
55
30
SCL = V CC
50
V CC = 5 V
25
ICC – Supply Current – nA
ICC – Supply Current – µA
45
40
f SCL = 400 kHz
I/Os Unloaded
35
30
25
V CC = 3.3 V
20
15
10
20
V CC = 5 V
15
V CC = 3.3 V
10
0
-50
-25
0
25
50
75
0
-50
100
TA – Free-Air Tem perature – °C
-25
0
25
50
75
100
TA – Free-Air Tem perature – °C
Figure 1. Supply Current vs Temperature
Figure 2. Standby Supply Current vs Temperature
30
70
V CC = 2.5 V
f SCL = 400 kHz
I/Os Unloaded
25
ISINK – I/O Sink Current – mA
60
ICC – Supply Current – µA
V CC = 2.5 V
5
V CC = 2.5 V
5
50
40
30
20
10
TA = –40°C
20
TA = 25°C
15
10
TA = 125°C
5
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0
0.0
V CC – Supply Voltage – V
0.1
0.2
0.3
0.4
0.5
0.6
V OL – Output Low Voltage – V
Figure 3. Supply Current vs Supply Voltage
Figure 4. I/O Sink Current vs Output Low Voltage
50
40
V CC = 3.3 V
TA = –40°C
40
30
ISINK – I/O Sink Current – mA
ISINK – I/O Sink Current – mA
TA = –40°C
25
TA = 25°C
20
15
10
TA = 125°C
35
TA = 25°C
30
25
20
15
10
5
TA = 125°C
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
V OL – Output Low Voltage – V
0.1
0.2
0.3
0.4
0.5
0.6
V OL – Output Low Voltage – V
Figure 5. I/O Sink Current vs Output Low Voltage
8
V CC = 5 V
45
35
Figure 6. I/O Sink Current vs Output Low Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
300
35
V CC = 2.5 V, ISINK = 10 m A
275
V CC = 2.5 V
ISOURCE – I/O Source Current – mA
V OL – Output Low Voltage – mV
250
225
200
175
V CC = 5 V, ISINK = 10 m A
150
125
100
75
V CC = 2.5 V, ISINK = 1 m A
50
30
TA = –40°C
25
TA = 25°C
20
15
10
TA = 125°C
5
V CC = 5 V, ISINK = 1 m A
25
0
0.0
0
-50
-25
0
25
50
75
0.1
0.2
100
0.3
0.4
0.5
0.6
0.7
(V CC – V OH) – V
TA – Free-Air Tem perature – °C
Figure 8. I/O Source Current vs Output High Voltage
Figure 7. I/O Output Low Voltage vs Temperature
50
TA = –40°C
40
35
ISOURCE – I/O Source Current – mA
ISOURCE – I/O Source Current – mA
75
70
65
V CC = 3.3 V
45
TA = 25°C
30
25
20
15
10
TA = 125°C
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
V CC = 5 V
TA = –40°C
60
55
50
45
40
TA = 25°C
35
30
25
20
15
TA = 125°C
10
5
0
0.7
0.0
0.1
0.2
(V CC – V OH) – V
Figure 9. I/O Source Current vs Output High Voltage
250
V OH – Output High Voltage – mV
V OH – Output High Voltage – mV
0.6
0.7
275
V CC = 2.5 V, IOL = 10 m A
225
200
175
150
V CC = 5 V, IOL = 10 m A
100
75
50
V CC = 2.5 V, IOL = 10 m A
225
200
175
150
125
V CC = 5 V, IOL = 10 m A
100
25
0
-50
0.5
300
275
125
0.4
Figure 10. I/O Source Current vs Output High Voltage
300
250
0.3
(V CC – V OH) – V
75
50
25
-25
0
25
50
75
0
-50
100
-25
0
25
50
75
100
TA – Free-Air Tem perature – °C
TA – Free-Air Tem perature – °C
Figure 11. I/O High Voltage vs Temperature
Figure 12. Output High Voltage vs Supply Voltage
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7 Parameter Measurement Information
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
ticf
tbuf
tsts
tPHL
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 13. I2C Interface Load Circuit And Voltage Waveforms
10
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Parameter Measurement Information (continued)
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
1
1
1
0
1
1
2
3
4
5
A1 A0 1
6
7
8
Data 1
A
ACK
From Slave
Data From Port
A
Data 2
1
P
A
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
0.3 × VCC
SCL
Data 2
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
INT
0.3 × VCC
0.3 × VCC
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 14. Interrupt Load Circuit And Voltage Waveforms
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Parameter Measurement Information (continued)
500 W
Pn
2 × VCC
DUT
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P0
A
P3
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note B)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P0
A
tps
P3
0.3 × VCC
tph
0.7 × VCC
Pn
0.3 × VCC
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 15. P-Port Load Circuit And Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
Pn
RL = 1 kΩ
DUT
500 W
2 × VCC
DUT
SDA
CL = 50 pF
(see Note A)
500 W
CL = 50 pF
(see Note A)
P-PORT LOAD CONFIGURATION
SDA LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y VCC
tRESET
RESET
VCC/2
tREC
tw
Pn
VCC/2
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 16. Reset Load Circuits And Voltage Waveforms
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8 Detailed Description
8.1 Functional Block Diagram
INT
A0
A1
SCL
SDA
PCA9539
1
Interrupt
Logic
LP Filter
21
2
P07−P00
22
23
I2C Bus
Control
Input
Filter
Shift
Register
16 Bits
I/O
Port
P17−P10
Write Pulse
3
RESET
VCC
GND
24
12
Power-On
Reset
Read Pulse
A.
Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
B.
All I/Os are set to inputs at reset.
Figure 17. Logic Diagram (Positive Logic)
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Functional Block Diagram (continued)
Data From
Shift Register
Output Port
Register Data
Configuration
Register
Data From
Shift Register
D
Q
FF
Write Configuration
Pulse
VCC
Q1
D
CLK Q
Q
FF
I/O Pin
CLK Q
Write Pulse
Output Port
Register
Q2
Input Port
Register
D
GND
Q
Input Port
Register Data
FF
Read Pulse
CLK Q
To INT
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
(1)
At power-on reset, all registers return to default values.
Figure 18. Simplified Schematic Of P-Port I/Os
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8.2 Device Functional Modes
8.2.1
RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA9539 registers and
I2C/SMBus state machine are held in their default states until RESET is once again high. This input requires a
pullup resistor to VCC, if no active connection is used.
8.2.1.1 RESET Errata
If RESET voltage set higher than VCC, current will flow from RESET pin to VCC pin.
System Impact
VCC will be pulled above its regular voltage level
System Workaround
Design such that RESET voltage is same or lower than VCC
8.2.2 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9539 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released and the PCA9539 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
Refer to the Power-On Reset Errata section.
8.2.3 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 18) are off, which creates a high-impedance
input. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.2.4 Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to VCC.
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Device Functional Modes (continued)
8.2.4.1 Interrupt Errata
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I2C command byte (register pointer) written to the device was 00h.
NOTE
This generally means the last operation with the device was a Read of the input register.
However, the command byte may have been written with 00h without ever going on to
read the input register. After reading from the device, if no other command byte written, it
will remain 00h.
2. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high
System Impact
Can cause improper interrupt handling as the Master will see the interrupt as being cleared.
System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9539 device or before reading from another slave device.
NOTE
Software change will be compatible with other versions (competition and TI redesigns) of
this device.
8.3 Programming
8.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 19). After the Start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address.
After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during
the high of the ACK-related clock pulse. The address inputs (A0 and A1) of the slave device must not be
changed between the Start and Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 20).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 19).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 21). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
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Programming (continued)
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 19. Definition Of Start And Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 20. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 21. Acknowledgment On I2C Bus
8.3.2 Register Map
Table 1. Interface Definition
BYTE
18
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C slave address
H
H
H
L
H
A1
A0
R/W
P0x I/O data bus
P07
P06
P05
P04
P03
P02
P01
P00
P1x I/O data bus
P17
P16
P15
P14
P13
P12
P11
P10
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8.3.2.1 Device Address
Figure 22 shows the address byte of the PCA9539.
R/W
Slave Address
1
1
1
0
Fixed
1
A1 A0
Programmable
Figure 22. Pca9539 Address
Table 2. Address Reference
INPUTS
A1
I2C BUS SLAVE ADDRESS
A0
L
L
116 (decimal), 74 (hexadecimal)
L
H
117 (decimal), 75 (hexadecimal)
H
L
118 (decimal), 76 (hexadecimal)
H
H
119 (decimal), 77 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.3.2.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9539. Three bits of this data byte state the operation (read or write) and
the internal register (input, output, Polarity Inversion or Configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
0
0
0
0
0
B2
B1
B0
Figure 23. Control Register Bits
Table 3. Command Byte
CONTROL REGISTER BITS
B2
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0
0x00
Input Port 0
Read byte
xxxx xxxx
0
0
1
0x01
Input Port 1
Read byte
xxxx xxxx
0
1
0
0x02
Output Port 0
Read/write byte
1111 1111
0
1
1
0x03
Output Port 1
Read/write byte
1111 1111
1
0
0
0x04
Polarity Inversion Port 0
Read/write byte
0000 0000
1
0
1
0x05
Polarity Inversion Port 1
Read/write byte
0000 0000
1
1
0
0x06
Configuration Port 0
Read/write byte
1111 1111
1
1
1
0x07
Configuration Port 1
Read/write byte
1111 1111
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8.3.2.3 Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to
these registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register will be accessed next.
Table 4. Registers 0 And 1 (Input Port Registers)
Bit
Default
Bit
Default
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
X
X
X
X
X
X
X
X
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
X
X
X
X
X
X
X
X
The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 5. Registers 2 And 3 (Output Port Registers)
Bit
Default
Bit
Default
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
1
1
1
1
1
1
1
1
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
1
1
1
1
1
1
1
1
The Polarity Inversion registers (registers 4 and 5) allow Polarity Inversion of pins defined as inputs by the
Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Table 6. Registers 4 And 5 (Polarity Inversion Registers)
Bit
Default
Bit
Default
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
0
0
0
0
0
0
0
N0.0
0
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
0
0
0
0
0
0
0
0
The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is
set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this
register is cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Registers 6 And 7 (Configuration Registers)
Bit
Default
Bit
Default
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
1
1
1
1
1
1
1
C0.0
1
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
1
1
1
1
1
1
1
1
8.3.2.4 Bus Transactions
Data is exchanged between the master and PCA9539 through write and read commands.
8.3.2.4.1 Writes
Data is transmitted to the PCA9539 by sending the device address and setting the least-significant bit to a logic 0
(see Figure 22 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte.
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The eight registers within the PCA9539 are configured to operate as four register pairs. The four pairs are Input
Ports, Output Ports, Polarity Inversion ports, and Configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 24 and Figure 25). For example, if the first byte is
sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
1
SCL
2
3
4
5
6
7
8
9
Command Byte
Slave Address
SDA
S
1
1
1
0
1
A1 A0
0
0
A
0
0
0
0
0
Data to Port 0
1
A 0.7
0
R/W Acknowledge
From Slave
Start Condition
Data to Port 1
0.0
Data 0
Acknowledge
From Slave
A 1.7
1.0
Data 1
A
P
Acknowledge
From Slave
Write to Port
Data Out from Port 0
tpv
Data Valid
Data Out from Port 1
tpv
Figure 24. Write To Output Port Registers
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Slave Address
SDA
S
1
1
1
Start Condition
0
1
A1 A0
4
5
6
7
8
9
1
2
3
R/W
A
0
0
0
Acknowledge
From Slave
0
0
1
1
5
6
7
8
9
1
2
3
Data to Register
Command Byte
0
4
0
A MSB
Data 0
4
5
Data to Register
LSB
Acknowledge
From Slave
A MSB
Data 1
LSB
A
P
Acknowledge
From Slave
Figure 25. Write To Configuration Registers
8.3.2.4.2 Reads
The bus master first must send the PCA9539 address with the least-significant bit set to a logic 0 (see Figure 22
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9539 (see Figure 26 through Figure 28).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
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Slave Address
S
1
1
1
0
1
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Acknowledge
From Slave
A1 A0
0
Slave Address
Acknowledge
From Slave
A
A
Command Byte
S
R/W
1
1
1
0
1
Data From Lower
or Upper Byte
of Register
Acknowledge
From Slave
A1 A0
1
A MSB
LSB
Data
A
First Byte
R/W
At this moment, master
transmitter becomes master
receiver, and slave receiver
becomes slave transmitter.
Acknowledge
From Master
Data From Upper
or Lower Byte
of Register
MSB
No Acknowledge
From Master
LSB NA
Data
P
Last Byte
Figure 26. Read From Register
1
SCL
2
3
4
5
6
7
8
9
I0.x
SDA
S
1
1
1
0
1
A1
A0
1
R/W
A
7
6
5
Acknowledge
From Slave
4
3
I1.x
2
1
0
A
7
6
5
Acknowledge
From Master
4
3
I0.x
2
1
0
A
7
6
5
4
3
I1.x
2
Acknowledge
From Master
1
0
A
7
6
5
4
3
2
Acknowledge
From Master
1
0
1
P
No Acknowledge
From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
tiv
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 26 for these details).
Figure 27. Read Input Port Register, Scenario 1
<br/>
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1
SCL
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2
3
4
5
6
7
8
9
I0.x
SDA
S
1
1
1
0
1
A1
A0
1
R/W
A
00
Acknowledge
From Slave
I1.x
A
10
I0.x
A
I1.x
03
A
Acknowledge
From Master
Acknowledge
From Master
P
No Acknowledge
From Master
tps
tph
1
12
Acknowledge
From Master
Read From Port 0
Data Into Port 0
Data 00
Data 01
Data 02
Data 03
tph
tps
Read From Port 1
Data 10
Data Into Port 1
Data 11
Data 12
INT
tiv
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 26 for these details).
Figure 28. Read Input Port Register, Scenario 2
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9 Application And Implementation
9.1 Typical Application
Figure 29 shows an application in which the PCA9539 can be used.
Subsystem 1
(e.g., Temperature
Sensor)
INT
VCC
(5 V)
10 kW
VCC
10 kW
10 kW
24
10 kW
22
SCL
Master
Controller SDA
23
SCL
SDA
Subsystem 2
(e.g., Counter)
100 kW
VCC
1
3 INT
RESET
INT
GND
2 kW
4
P00
5
P01
6
P02
7
P03
8
P04
9
P05
100 kW
100 kW
RESET
A
ENABLE
B
PCA9539
P06
P07
P10
P11
2
A1
P12
P13
21
A0
P14
P15
P16
GND P17
12
A.
Device address is configured as 1110100 for this example.
B.
P00, P02, and P03 are configured as outputs.
C.
P01 and P04 to P17 are configured as inputs.
D.
Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
10
11
13
14
15
16
17
18
19
20
VCC
Controlled Switch
(e.g., CBT Device)
ALARM
Keypad
Subsystem 3
(e.g., Alarm)
Figure 29. Typical Application
24
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Typical Application (continued)
9.1.1 Detailed Design Procedure
9.1.1.1 Minimizing ICC When I/O Is Used To Control Led
When an I/O is used to control an LED, normally it is connected to VCC through a resistor (see Figure 29).
Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For batterypowered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC, when the LED is
off, to minimize current consumption.
Figure 30 shows a high-value resistor in parallel with the LED. Figure 31 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VCC at or above VCC and prevent additional
supply-current consumption when the LED is off.
VCC
LED
VCC
100 kW
Pn
Figure 30. High-Value Resistor In Parallel With Led
3.3 V
VCC
5V
LED
Pn
Figure 31. Device Supplied By Lower Voltage
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9539 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 32 and Figure 33.
VCC
Ramp-Up
Ramp-Down
Re-Ramp-Up
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 32. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 33. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC
Table 8 specifies the performance of the power-on reset feature for PCA9539 for both types of power-on reset.
Table 8. Recommended Supply Sequencing And Ramp Rates (1)
MAX
UNIT
VCC_FT
Fall rate
PARAMETER
See Figure 32
1
100
ms
VCC_RT
Rise rate
See Figure 32
0.01
100
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 32
0.001
ms
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 33
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 34
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 34
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on rising VCC
1.033
1.428
V
(1)
26
MIN
TYP
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 34 and Table 8 provide more
information on how to measure these specifications.
VCC
VCC_GH
Time
VCC_GW
Figure 34. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 35 and Table 8 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 35. VPOR
10.2 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed above.
System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCA9539DB
ACTIVE
SSOP
DB
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9539
PCA9539DBQR
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PCA9539
PCA9539DBR
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9539
PCA9539DGVR
ACTIVE
TVSOP
DGV
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9539
PCA9539DW
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9539
PCA9539DWR
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9539
PCA9539PW
NRND
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9539
PCA9539PWE4
NRND
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9539
PCA9539PWG4
NRND
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9539
PCA9539PWR
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9539
PCA9539PWRG4
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD9539
PCA9539RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD9539
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCA9539DBQR
Package Package Pins
Type Drawing
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
PCA9539DBR
SSOP
DB
24
2000
330.0
16.4
8.2
8.8
2.5
12.0
16.0
Q1
PCA9539DGVR
TVSOP
DGV
24
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
PCA9539DWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
PCA9539PWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
PCA9539RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9539DBQR
SSOP
DBQ
24
2500
367.0
367.0
38.0
PCA9539DBR
SSOP
DB
24
2000
367.0
367.0
38.0
PCA9539DGVR
TVSOP
DGV
24
2000
367.0
367.0
35.0
PCA9539DWR
SOIC
DW
24
2000
350.0
350.0
43.0
PCA9539PWR
TSSOP
PW
24
2000
367.0
367.0
38.0
PCA9539RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 2.5
2.1±0.1
(0.2) TYP
12
7
20X 0.5
6
13
25
2X
2.5
SYMM
1
PIN 1 ID
(OPTIONAL)
18
24X 0.30
0.18
24
19
SYMM
24X 0.50
0.30
0.1
0.05
C A B
C
4224376 / A 07/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
(
2.1)
19
24
24X (0.6)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.8)
2X
(0.8)
(Ø0.2) VIA
TYP
6
13
(R0.05)
12
7
2X(0.8)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224376 / A 07/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
(0.19)
4X ( 0.94)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.8)
(0.57)
TYP
6
13
(R0.05) TYP
METAL
TYP
25
7
SYMM
12
(0.57)
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 20X
4224376 / A 07/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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