Texas Instruments | PCA9515A Dual Bidirectional I2C Bus and SMBus Repeater (Rev. D) | Datasheet | Texas Instruments PCA9515A Dual Bidirectional I2C Bus and SMBus Repeater (Rev. D) Datasheet

Texas Instruments PCA9515A Dual Bidirectional I2C Bus and SMBus Repeater (Rev. D) Datasheet
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PCA9515A
SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
Dual Bidirectional I2C Bus and SMBus Repeater
The I2C bus capacitance limit of 400 pF restricts the
number of devices and bus length. Using the
PCA9515A enables the system designer to isolate
two halves of a bus, accommodating more I2C
devices or longer trace lengths.
1 Features
•
•
•
•
•
1
•
•
•
•
•
Two-Channel Bidirectional Buffers
I2C Bus and SMBus Compatible
Active-High Repeater-Enable Input
Open-Drain I2C I/O
5.5-V Tolerant I2C I/O and Enable Input Support
Mixed-Mode Signal Operation
Lockup-Free Operation
Accommodates Standard Mode and Fast Mode
I2C Devices and Multiple Masters
Powered-Off High-Impedance I2C Pins
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The PCA9515A has an active-high enable (EN) input
with an internal pullup, which allows the user to select
when the repeater is active. This can be used to
isolate a badly behaved slave on power-up reset. It
never should change state during an I2C operation,
because disabling during a bus operation hangs the
bus, and enabling part way through a bus cycle could
confuse the I2C parts being enabled. The EN input
should change state only when the global bus and
the repeater port are in an idle state, to prevent
system failures.
2 Description
This dual bidirectional I2C buffer is operational at 2.3V to 3.6-V VCC.
The PCA9515A is a BiCMOS integrated circuit
intended for I2C bus and SMBus systems
applications. The device contains two identical
bidirectional open-drain buffer circuits that enable I2C
and similar bus systems to be extended without
degradation of system performance.
The PCA9515A buffers both the serial data (SDA)
and serial clock (SCL) signals on the I2C bus, while
retaining all the operating modes and features of the
I2C system. This enables two buses of 400-pF bus
capacitance to be connected in an I2C application.
The PCA9515A also can be used to run two buses:
one at 5-V interface levels and the other at 3.3-V
interface levels, or one at 400-kHz operating
frequency and the other at 100-kHz operating
frequency. If the two buses are operating at different
frequencies, the 100-kHz bus must be isolated when
the 400-kHz operation of the other bus is required. If
the master is running at 400 kHz, the maximum
system operating frequency may be less than
400 kHz, because of the delays that are added by the
repeater.
The PCA9515A does not support clock stretching
across the repeater.
Device Information(1)
PART NUMBER
PCA9515A
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
D, DCT, DGK, OR PW PACKAGE
(TOP VIEW)
NC
1
8
VCC
SCL0
SDA0
2
3
7
6
SCL1
SDA1
GND
4
5
EN
DRG PACKAGE
(TOP VIEW)
NC
SCL0
SDA0
GND
1
2
3
4
8
7
6
5
VCC
SCL1
SDA1
EN
NC – No internal connection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9515A
SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
2
3
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
5
Absolute Maximum Ratings .....................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
7
8
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Functional Block Diagram ......................................... 7
8.2 Feature Description................................................... 7
8.3 Device Functional Modes.......................................... 7
9
Application and Implementation .......................... 8
9.1 Typical Application ................................................... 8
10 Device and Documentation Support ................... 9
10.1 Trademarks ............................................................. 9
10.2 Electrostatic Discharge Caution .............................. 9
10.3 Glossary .................................................................. 9
11 Mechanical, Packaging, and Orderable
Information ............................................................. 9
3 Revision History
Changes from Revision C (January 2011) to Revision D
•
Added Clock Stretching Errata section. ................................................................................................................................. 7
Changes from Revision B (October 2007) to Revision C
•
2
Page
Page
Deleted all references to arbitration and clock stretching support. This does not effect min/max specifications. ................. 1
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SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
4 Description (Continued)
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal
buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents
a lockup condition from occurring when the input low condition is released.
Two or more PCA9515A devices cannot be used in series. The PCA9515A design does not allow this
configuration. Because there is no direction pin, slightly different valid low-voltage levels are used to avoid lockup
conditions between the input and the output of each repeater. A valid low applied at the input of a PCA9515A is
propagated as a buffered low with a slightly higher value on the enabled outputs. When this buffered low is
applied to another PCA9515A-type device in series, the second device does not recognize it as a valid low and
does not propagate it as a buffered low again.
The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from
becoming active until VCC is at a valid level (VCC = 2.3 V).
As with the standard I2C system, pullup resistors are required to provide the logic high levels on the buffered bus.
The PCA9515A has standard open-collector configuration of the I2C bus. The size of these pullup resistors
depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to
work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices. Standard Mode I2C devices
only specify 3 mA in a generic I2C system where Standard Mode devices and multiple masters are possible.
Under certain conditions, high termination currents can be used.
5 Pin Configuration and Functions
D, DCT, DGK, OR PW PACKAGE
(TOP VIEW)
NC
1
8
VCC
SCL0
SDA0
2
3
7
6
SCL1
SDA1
GND
4
5
EN
DRG PACKAGE
(TOP VIEW)
NC
SCL0
SDA0
GND
1
2
3
4
8
7
6
5
VCC
SCL1
SDA1
EN
NC – No internal connection
Pin Functions
PIN
NAME
NO.
DESCRIPTION
NC
1
No internal connection
SCL0
2
Serial clock bus 0
SDA0
3
Serial data bus 0
GND
4
Supply ground
EN
5
Active-high repeater enable input
SDA1
6
Serial data bus 1
SCL1
7
Serial clock bus 1
VCC
8
Supply power
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3
PCA9515A
SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
(2)
MIN
MAX
–0.5
7
UNIT
V
–0.5
7
V
–0.5
7
VI
Enable input voltage range
VI/O
I2C bus voltage range (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
D package
97
DCT package
Package thermal impedance (3)
θJA
220
DGK package
172
DRG package
TBD
PW package
(1)
V
°C/W
149
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
(2)
(3)
6.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
(2)
MAX
UNIT
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC
VIH
VIL
VILc
(1)
3.6
0.7 × VCC
5.5
2
5.5
SDA and SCL inputs
–0.5
0.3 × VCC
EN input
–0.5
0.8
(1)
–0.5
0.4
EN input
Low-level input voltage
SDA and SCL low-level input voltage contention
Low-level output current
TA
Operating free-air temperature
4
MAX
2.3
SDA and SCL inputs
High-level input voltage
IOL
(1)
MIN
Supply voltage
VCC = 2.3 V
6
VCC = 3 V
6
–40
85
UNIT
V
V
V
V
mA
°C
VIL specification is for the EN input and the first low level seen by the SDAx and SCLx lines. VILc is for the second and subsequent low
levels seen by the SDAx and SCLx lines. VILc must be at least 70 mV below VOL.
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SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
6.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input diode clamp voltage
II = –18 mA
2.3 V to 3.6 V
2.3 V to 3.6 V
2.3 V to 3.6 V
VOL
Low-level output voltage
SDAx,
IOL = 20 μA or 6 mA
SCLx
VOL – VILc
Low-level input voltage below
low-level output voltage
SDAx,
II = 10 μA
SCLx
ICC
Quiescent supply current
II
–1.2
V
0.6
V
70
mV
0.52
0.5
3
3.6 V
0.5
3
Both channels low,
SDA0 = SCL0 = GND and
SDA1 = SCL1 = open; or
SDA0 = SCL0 = open and
SDA1 = SCL1 = GND
2.7 V
1
4
3.6 V
1
4
In contention,
SDAx = SCLx = GND
2.7 V
1
4
3.6 V
1
mA
4
±1
3
2.3 V to 3.6 V
–10
Leakage current
SDAx, VI = 3.6 V
SCLx VI = GND
EN = L or H
0V
II(ramp)
Leakage current during
power up
SDAx,
VI = 3.6 V
SCLx
EN = L or H
0 V to 2.3 V
Cin
Input capacitance
μA
±1
VI = 0.2 V
Ioff
(1)
UNIT
2.7 V
VI = VCC
EN
0.47
MAX
Both channels high,
SDAx = SCLx = VCC
SDAx, VI = 3.6 V
SCLx VI = 0.2 V
Input current
MIN TYP (1)
VCC
–20
0.5
μA
0.5
μA
1
EN
3.3 V
7
9
SDAx, VI = 3 V or GND
EN = H
SCLx
3.3 V
7
9
pF
All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C.
6.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
UNIT
MAX
tsu
Setup time, EN↑ before Start condition
100
100
ns
th
Hold time, EN↓ after Stop condition
130
100
ns
6.6 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted)
PARAMETER
tPZL
tPLZ
ttHL
ttLH
(1)
(2)
Propagation delay time (2)
Output transition time (2)
(SDAx, SCLx)
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
SDA0, SCL0 or
SDA1, SCL1
SDA1, SCL1 or
SDA0, SCL0
80%
20%
57
58
20%
80%
148
147
MIN
TYP (1)
MAX
MIN
TYP (1)
MAX
45
82
130
45
68
120
33
113
190
33
102
180
UNIT
ns
ns
All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C.
Different load resistance and capacitance alter the RC time constant, thereby changing the propagation delay and transition times.
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PCA9515A
SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
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7 Parameter Measurement Information
VCC
VIN
VCC
VOUT
PULSE
GENERATOR
RL = 1.35 kΩ
S1
DUT
GND
CL = 50 pF
(see Note B)
RT
(see Note A)
TEST
S1
tPLZ/tPZL
VCC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
Input
VCC
1.5 V
1.5 V
0V
tPZL
Output
tPLZ
80%
1.5 V
1.5 V
20%
20%
80%
ttHL
VCC
VOL
ttLH
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A.
RT termination resistance should be equal to ZOUT of pulse generators.
B.
CL includes probe and jig capacitance.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
slew rate ≥ 1 V/ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLH and tPHL are the same as tpd.
F.
tPLZ and tPHZ are the same as tdis.
G.
tPZL and tPZH are the same as ten.
Figure 1. Test Circuit and Voltage Waveforms
6
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8 Detailed Description
8.1 Functional Block Diagram
VCC
8
PCA9515A
SDA0
SCL0
3
6
2
7
SDA1
SCL1
Pullup
Resistor
EN
5
4
Figure 2. Logic Diagram (Positive Logic)
8.2 Feature Description
8.2.1 Clock Stretching Errata
Description
Due to the static offset on both sides of the buffer (SCLx & SDAx) and the possibility of an overshoot above 500
mV during events like clock stretching, the device should not be used with rise time accelerators.
System Impact
An incorrect logic state will be passed through the buffer, creating an I2C communication failure on the bus.
System Workaround
There is a possible workaround to avoid an I2C communication failure:
• Do not use rise-time accelerators in conjunction with the PCA9515A.
8.3 Device Functional Modes
Table 1. Function Table
INPUT
EN
FUNCTION
L
Outputs disabled
H
SDA0 = SDA1
SCL0 = SCL1
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PCA9515A
SCPS150D – DECEMBER 2005 – REVISED JUNE 2014
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9 Application and Implementation
9.1 Typical Application
A typical application is shown in Figure 3. In this example, the system master is running on a 3.3-V bus, while the
slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated, and then the
master bus can run at 400 kHz. Master devices can be placed on either bus.
3.3 V
5V
SDA
SDA0
SDA1
SDA
SCL
SCL0
SCL1
SCL
PCA9515A
I2C BUS MASTER
400 kHz
I2C BUS SLAVE
100 kHz
EN
BUS 0
BUS 1
Figure 3. Typical Application
9.1.1 Design Requirements
The PCA9515A is 5.5-V tolerant, so it does not require any additional circuitry to translate between the different
bus voltages.
When one side of the PCA9515A is pulled low by a device on the I2C bus, a CMOS hysteresis-type input detects
the falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to go
low. The side driven low by the PCA9515A typically is at VOL = 0.5 V.
9.1.2 Detailed Design Procedure
Figure 4 and Figure 5 show the waveforms that are seen in a typical application. If the bus master in Figure 3
writes to the slave through the PCA9515A, Bus 0 has the waveform shown in Figure 4. This looks like a normal
I2C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the data line
(SDA) while the slave pulls it low through the PCA9515A. Because the VOL of the PCA9515A typically is around
0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases the
data line.
9th Clock Pulse
SCL
SDA
VOL of Master
VOL of PCA9515A
Figure 4. Bus 0 Waveforms
8
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Typical Application (continued)
9th Clock Pulse
SCL
SDA
VOL of PCA9515A
VOL of Slave
Figure 5. Bus 1 Waveforms
On the Bus 1 side of the PCA9515A, the clock and data lines have a positive offset from ground equal to the VOL
of the PCA9515A. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is very
close to ground in the example.
10 Device and Documentation Support
10.1 Trademarks
All trademarks are the property of their respective owners.
10.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCA9515AD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD515A
PCA9515ADGKR
NRND
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(7BA, 7BE)
PCA9515ADGKRG4
NRND
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(7BA, 7BE)
PCA9515ADGKT
NRND
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(7BA, 7BE)
PCA9515ADGKTG4
NRND
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(7BA, 7BE)
PCA9515ADR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD515A
PCA9515ADRGR
ACTIVE
SON
DRG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZVD
PCA9515ADT
ACTIVE
SOIC
D
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD515A
PCA9515APW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD515A
PCA9515APWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD515A
PCA9515APWT
ACTIVE
TSSOP
PW
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD515A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PCA9515ADGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
PCA9515ADGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
PCA9515ADGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
PCA9515ADGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
PCA9515ADR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
PCA9515ADRGR
SON
DRG
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
PCA9515ADT
SOIC
D
8
250
180.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
PCA9515APWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
PCA9515APWT
TSSOP
PW
8
250
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9515ADGKR
VSSOP
DGK
8
2500
346.0
346.0
35.0
PCA9515ADGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
PCA9515ADGKT
VSSOP
DGK
8
250
220.0
205.0
50.0
PCA9515ADGKT
VSSOP
DGK
8
250
358.0
335.0
35.0
PCA9515ADR
SOIC
D
8
2500
367.0
367.0
35.0
PCA9515ADRGR
SON
DRG
8
3000
367.0
367.0
35.0
PCA9515ADT
SOIC
D
8
250
210.0
185.0
35.0
PCA9515APWR
TSSOP
PW
8
2000
367.0
367.0
35.0
PCA9515APWT
TSSOP
PW
8
250
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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