Texas Instruments | Class V 2x2 LVDS Crosspoint Switch (Rev. A) | Datasheet | Texas Instruments Class V 2x2 LVDS Crosspoint Switch (Rev. A) Datasheet

Texas Instruments Class V 2x2 LVDS Crosspoint Switch (Rev. A) Datasheet
SN55LVCP22-SP
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SLLSE43A – JUNE 2012 – REVISED JANUARY 2014
CLASS V 2x2 LVDS CROSSPOINT SWITCH
Check for Samples: SN55LVCP22-SP
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
High Speed (>1000 Mbps) Upgrade for
DS90CP22 2x2 LVDS Crosspoint Switch
Low-Jitter Fully Differential Data Path
50 ps (Typ), of Peak-to-Peak Jitter With PRBS
= 223–1 Pattern
Less Than 200 mW (Typ), 300 mW (Max) Total
Power Dissipation
Output (Channel-to-Channel) Skew Is 80 ps
(Typ)
Configurable as 2:1 Mux, 1:2 Demux, Repeater
or 1:2 Signal Splitter
Inputs Accept LVDS, LVPECL, and CML
Signals
Fast Switch Time of 1.7 ns (Typ)
Fast Propagation Delay of 0.65 ns (Typ)
Available in 16 pin CFP Package
Inter-Operates With TIA/EIA-644-A LVDS
Standard
Military Temperature Range: –55°C to 125°C
APPLICATIONS
•
•
•
•
•
•
•
(1)
Base Stations
Add/Drop Muxes
Protection Switching for Serial Backplanes
Network Switches/Routers
Optical Networking Line Cards/Switches
Clock Distribution
Engineering Evaluation (/EM) Samples are
Available (1)
These units are intended for engineering evaluation only.
They are processed to a non-compliant flow (e.g. no burn-in,
etc.) and are tested to temperature rating of 25°C only. These
units are not suitable for qualification, production, radiation
testing or flight use. Parts are not warranted for performance
on full MIL specified temperature range of
-55°C to 125°C or operating life.
DESCRIPTION
The SN55LVCP22 is a 2×2 crosspoint switch
providing greater than 1000 Mbps operation for each
path. The dual channels incorporate wide commonmode (0 V to 4 V) receivers, allowing for the receipt
of LVDS, LVPECL, and CML signals. The dual
outputs are LVDS drivers to provide low-power, lowEMI, high-speed operation. The SN55LVCP22
provides a single device supporting 2:2 buffering
(repeating), 1:2 splitting, 2:1 multiplexing, 2×2
switching, and LVPECL/CML to LVDS level
translation on each channel. The flexible operation of
the SN55LVCP22 provides a single device to support
the redundant serial bus transmission needs (working
and protection switching cards) of fault-tolerant switch
systems found in optical networking, wireless
infrastructure, and data communications systems. TI
offers additional gigabit repeater/ translator and
crosspoint products in the SN65LVDS100 and
SN65LVDS122.
The SN55LVCP22 uses a fully differential data path
to ensure low-noise generation, fast switching times,
low pulse width distortion, and low jitter. Output
channel-to- channel skew is 80 ps (typ) to ensure
accurate alignment of outputs in all applications. Both
SOIC and TSSOP package options are available to
allow easy upgrade for existing solutions, and board
area savings where space is critical.
OUTPUTS OPERATING SIMULTANEOUSLY
1 Gbps
223 -1 PRBS
OUTPUT 1
VCC = 3.3 V
|VID| = 200 mV, VIC = 1.2 V
Vertical Scale = 200 mV/div
OUTPUT 2
500 MHz
Horizontal Scale = 300 ps
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2014, Texas Instruments Incorporated
SN55LVCP22-SP
SLLSE43A – JUNE 2012 – REVISED JANUARY 2014
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
θJA
Junction-to-ambient thermal resistance
θJC
Junction-to-case thermal resistance
PD
Device power dissipation
VALUE
UNITS
82.5
°C/W
7.5
°C/W
Typical
VCC = 3.3 V, TA = 25°C, 1 Gbps
198
Maximum
VCC = 3.6 V, TA = 125°C, 1 Gbps
313
mW
10000
Estimated Life (Years)
1000
100
Electromigration Fail Mode
10
1
0.1
80
90
100
110
120
130
140
150
160
170
180
Continuous TJ (°C)
A.
See datasheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
C.
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 1. SN55LVCP22-SP Operating Life Derating Chart
2
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Table 1. FUNCTION TABLE
SEL0
SEL1
OUT0
OUT1
FUNCTION
0
0
IN0
IN0
1:2 Splitter
0
1
IN0
IN1
Repeater
1
0
IN1
IN0
Switch
1
1
IN1
IN1
1:2 Splitter
FUNCTIONAL BLOCK DIAGRAM
OUT 0
OUT 1
EN 0
EN 1
SEL 1
SEL 0
0
1
0
1
IN 0
IN 1
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUTS
VCC
IN +
IN -
400 Ω
SEL, EN
300 kΩ
7V
7V
7V
OUTPUTS
VCC
OUT +
OUT -
7V
7V
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNITS
Supply voltage
(2)
range, VCC
–0.5 V to 4 V
CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1)
–0.5 V to 4 V
LVDS receiver input voltage (IN+, IN–)
–0.7 V to 4.3 V
LVDS driver output voltage (OUT+, OUT–)
–0.5 V to 4 V
LVDS output short circuit current
Continuous
Storage temperature range
–65°C to 125°C
Maximum Junction temperature
Electrostatic discharge
(1)
(2)
(3)
(4)
4
150°C
Human body model (3)
All pins
±5 kV
Charged-device mode (4)
All pins
±500 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminals.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
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RECOMMENDED OPERATING CONDITIONS
MIN
NOM MAX
3
Receiver input voltage
0
4
V
–55
125
°C
0.1
3
V
Operating Case Ttemperature range, TC
(1)
Magnitude of differential input voltage |VID|
(1)
3.3
3.6
UNIT
Supply voltage, VCC
V
Maximum case temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
TYP (1)
MIN
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1)
VIH
High-level input voltage
2
VIL
Low-level input voltage
IIH
High-level input current
VIN = 3.6 V or 2.0 V, VCC = 3.6 V
-25
IIL
Low-level input current
VIN = 0.0 V or 0.8 V, VCC = 3.6 V
-15
VCL
Input clamp voltage
ICL = –18 mA
VCC
GND
±3
V
0.8
V
25
µA
±1
15
µA
-0.8
-1.5
V
LVDS OUTPUT SPECIFICATIONS (OUT0, OUT1)
RL = 75 Ω, See Figure 3
255
365
475
RL = 75 Ω, VCC = 3.3 V, TA = 25°C, See
Figure 3
285
365
440
Change in differential output voltage magnitude
between logic states
VID = ±100 mV, See Figure 3
–25
VOS
Steady-state offset voltage
See Figure 4
1
ΔVOS
Change in steady-state offset voltage between
logic states
See Figure 4
–25
VOC(PP)
Peak-to-peak common-mode output voltage
See Figure 4
IOZ
High-impedance output current
VOUT = GND or VCC
-15
15
IOFF
Power-off leakage current
VCC = 0 V, 1.5 V; VOUT = 3.6 V or GND
-15
15
µA
IOS
Output short-circuit current
VOUT+ or VOUT- = 0 V
-8
mA
IOSB
Both outputs short-circuit current
VOUT+ and VOUT- = 0 V
8
mA
CO
Differential output capacitance
VI = 0.4 sin(4E6πt) + 0.5 V
|VOD|
Differential output voltage
Δ|VOD|
25
1.2
1.45
25
50
–8
mV
mV
V
mV
mV
3
µA
pF
LVDS RECEIVER DC SPECIFICATIONS (IN0, IN1)
VTH
Positive-going differential input voltage threshold
See Figure 2 and Table 2
VTL
Negative-going differential input voltage threshold
See Figure 2 and Table 2
100
–100
VID(HYS) Differential input voltage hysteresis
VCMR
Common-mode voltage range
IIN
Input current
CIN
Differential input capacitance
mV
25
VID = 100 mV, VCC = 3.0 V to 3.6 V
mV
0.05
150
mV
3.95
V
VIN = 4 V, VCC = 3.6 V or 0.0
-18
±1
18
VIN = 0 V, VCC = 3.6V or 0.0
-18
±1
18
µA
VI = 0.4 sin (4E6πt) + 0.5 V
3
pF
Quiescent supply current
RL = 75 Ω, EN0=EN1=High
60
87
mA
ICCD
Total supply current
RL = 75 Ω, CL = 5 pF, 500 MHz (1000
Mbps), EN0=EN1=High
63
87
mA
ICCZ
3-state supply current
EN0 = EN1 = Low
25
35
mA
SUPPLY CURRENT
ICCQ
(1)
All typical values are at 25°C and with a 3.3-V supply.
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SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
parameter
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSET
Input to SEL setup time
See Figure 7
2.2
0.8
tHOLD
Input to SEL hold time
See Figure 7
2.2
1.0
tSWITCH
SEL to switched output
See Figure 7
1.7
2.6
ns
tPHZ
Disable time, high-level-to-high-impedance
See Figure 6
2
8
ns
tPLZ
Disable time, low-level-to-high-impedance
See Figure 6
2
8
ns
tPZH
Enable time, high-impedance -to-high-level output
See Figure 6
2
8
ns
tPZL
Enable time, high-impedance-to-low-level output
See Figure 6
2
8
ns
CL = 5 pF, See Figure 5
280
620
ps
CL = 5 pF, See Figure 5
280
620
ps
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 50 MHz, CL = 5 pF
13.7
22.2
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 240 MHz, CL = 5 pF
13.4
24.5
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 500 MHz, CL = 5 pF
14.4
35.7
VID = 200 mV, PRBS = 215-1 data pattern,
VCM = 1.2 V, 240 Mbps, CL = 5 pF
68.3
204
VID = 200 mV, PRBS = 215-1 data pattern,
VCM = 1.2 V, 1000 Mbps, CL = 5 pF
73.2
282
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 50 MHz, CL = 5 pF
0.97
1.5
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 240 MHz, CL = 5 pF
0.85
1.53
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 500 MHz, CL = 5 pF
0.86
1.79
(1)
tLHT
Differential output signal rise time (20%-80%)
tHLT
Differential output signal fall time (20%-80%) (1)
tJIT
Added peak-to-peak jitter
tJrms
Added random jitter (rms)
ns
ns
ps
ps
psRMS
tPLHD
Propagation delay time, low-to-high-level output (1)
200
650
2350
ps
tPHLD
Propagation delay time, high-to-low-level output (1)
200
650
2350
ps
tskew (2)
Pulse skew (|tPLHD – tPHLD|) (3)
CL = 5 pF, See Figure 5
45
160
ps
tCCS
Output channel-to-channel skew, splitter mode
CL = 5 pF, See Figure 5
fMAX (2)
Maximum operating frequency (4)
(1)
(2)
(3)
(4)
6
80
1
ps
GHz
Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps
tskew and fMAX parameters are guaranteed by characterization, but not production tested.
tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device.
Signal generator conditions: 50% duty cycle, tr or tf ≤ 100 ps (10% to 90%), transmitter output criteria: duty cycle = 45% to 55% VOD ≥
300 mV.
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PIN ASSIGNMENTS
W PACKAGE
(TOP VIEW)
SEL1
1
16
EN0
SEL0
2
15
EN1
IN0+
3
14
OUT0+
IN0-
4
13
OUT0-
VCC
5
12
GND
IN1+
6
11
OUT1+
IN1-
7
10
OUT1-
NC
8
9
NC
NC - No internal connection
PARAMETER MEASUREMENT INFORMATION
IIN+
OUT +
IN+
VID
IN+ + IN-
VIC
VOD
VIN+
VIN-
2
VOY
IN-
OUT -
VOUT++ VOUT-
VOZ
IIN-
2
Figure 2. Voltage and Current Definitions
3.74 kΩ
Y
VOD
Z
+
_
75 Ω
0 V ≤ V(test) ≤ 2.4 V
3.74 kΩ
Figure 3. Differential Output Voltage (VOD) Test Circuit
IN+
OUT+
IN+
≈1.4 V
IN-
≈1 V
37.4 Ω ±1%
VID
VOC(PP)
IN-
OUT-
37.4 Ω ±1%
1 pF
VOS
VOS
VOC
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; RL = 100 Ω; CL includes instrumentation and fixture capacitance within
0,06 mm of the D.U.T.; the measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least
300 MHz.
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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PARAMETER MEASUREMENT INFORMATION (continued)
OUT+
IN+
1 pF
VID
VIN+
IN-
VOUT+ VOD
75 Ω
OUT5 pF
VIN-
VOUT-
VIN+
1.3 V
VIN-
1.1 V
VID
0.2 V
0V
-0.2 V
tPLHD
tPHLD
+VOD
80%
0V
Vdiff = (OUT+) - (OUT-)
20%
-VOD
tHLT
tLHT
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ .25 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 5. Timing Test Circuit and Waveforms
37.4 Ω ±1%
OUT+
1 V or 1.4 V
VOUT+
1.2 V
37.4 Ω ±1%
OUT-
EN
5 pF
1.2 V
VOUT-
EN
3V
1.5 V
0V
OUT
VOH
50%
1.2 V
tPHZ
tPZH
1.2 V
50%
VOL
OUT
tPLZ
tPZL
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 6. Enable and Disable Time Circuit and Definitions
8
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Table 2. Receiver Input Voltage Threshold Test
APPLIED VOLTAGES
(1)
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VID
VIC
OUTPUT (1)
VIA
VIB
1.25 V
1.15 V
100 mV
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
L
4.0 V
3.9 V
100 mV
3.95 V
H
3.9 V
4. 0 V
–100 mV
3.95 V
L
0.1 V
0.0 V
100 mV
0.05 V
H
0.0 V
0.1 V
–100 mV
0.05 V
L
1.7 V
0.7 V
1000 mV
1.2 V
H
0.7 V
1.7 V
–1000 mV
1.2 V
L
4.0 V
3.0 V
1000 mV
3.5 V
H
3.0 V
4.0 V
–1000 mV
3.5 V
L
1.0 V
0.0 V
1000 mV
0.5 V
H
0.0 V
1.0 V
–1000 mV
0.5 V
L
H
H = high level, L = low level
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IN0
IN1
SEL
tSET
tHOLD
OUT
IN0
IN1
tSWITCH
EN
IN0
IN1
SEL
tSET
OUT
tHOLD
IN1
IN0
tSWITCH
EN
NOTE: tSET and tHOLD times specify that data must be in a stable state before and after mux control switches.
Figure 7. Input to Select for Both Rising and Falling Edge Setup and Hold Times
10
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TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
vs
RESISTIVE LOAD
SUPPLY CURRENT
vs
FREQUENCY
75
400
300
200
100
0
40
80
120
160
50
25
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|V ID| = 200 mV
0
0
200
400
800
1200
1600
0
20
40
60
80
Figure 9.
Figure 10.
PEAK-TO-PEAK JITTER
vs
FREQUENCY
PEAK-TO-PEAK JITTER
vs
DATA RATE
PEAK-TO-PEAK JITTER
vs
FREQUENCY
10
40
800 mV
30
500 mV
20
400 mV
10
5
400 mV
300
400
15
500
0
600
200
400
600
10
800 mV
1000
800
300 mV
0
1200
0
100
Data Rate − Mbps
f − Frequency − MHz
600 mV
400 mV
500 mV
600 mV
800 mV
0
200
20
5
300 mV
0
100
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
Input = Clock
25
Peak-to-Peak Jitter − ps
500 mV
300 mV
200
300
400
500
f − Frequency − MHz
Figure 11.
Figure 12.
Figure 13.
PEAK-TO-PEAK JITTER
vs
DATA RATE
PEAK-TO-PEAK JITTER
vs
FREQUENCY
PEAK-TO-PEAK JITTER
vs
DATA RATE
30
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
Input = PRBS 223 −1
25
Peak-to-Peak Jitter − ps
800 mV
40
400 mV
600 mV
20
300 mV
10
60
VCC = 3.3 V,
TA = 25°C,
VIC = 1.6 V,
Input = Clock
20
15
300 mV
800 mV
600 mV
10
400 mV 500 mV
400
600
800
1000
1200
Data Rate − Mbps
Figure 14.
800 mV
600 mV
30
500 mV
20
400 mV
300 mV
500 mV
200
40
600
10
5
0
VCC = 3.3 V,
TA = 25°C,
VIC = 1.6 V,
Input = PRBS 223 −1
50
Peak-to-Peak Jitter − ps
60
100
30
VCC = 3.3 V,
TA = 25°C,
VIC = 400 mV,
Input = PRBS 223 −1
50
Peak-to-Peak Jitter − ps
600 mV
0
tPHL
675
Figure 8.
15
30
tPLH
TA − Free-Air Temperature − °C
20
50
750
600
−60 −40 −20
2000
60
0
825
f − Frequency − MHz
VCC = 3.3 V,
TA = 25°C,
VIC = 400 mV,
Input = Clock
25
VCC = 3 − 3.6 V,
VIC = 1.2 V,
|V ID| = 300 mV
Input = 1 MHz
Resistive Load − Ω
30
Peak-to-Peak Jitter − ps
t pd − Propagation Delay Time − ps
500
0
Peak-to-Peak Jitter − ps
900
VCC = 3.3 V
TA = 25°C
I CC − Supply Current − mA
V OD − Differential Output Voltage − mV
600
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
0
0
0
100
200
300
400
500
f − Frequency − MHz
600
Figure 15.
0
200
400
600
800
1000
Figure 16.
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1200
Data Rate − Mbps
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TYPICAL CHARACTERISTICS (continued)
PEAK-TO-PEAK JITTER
vs
DATA RATE
30
600 mV
300 mV
400 mV
10
40
V OD − Differential Output Voltage − mV
Peak-to-Peak Jitter − ps
15
VCC = 3.3 V,
TA = 25°C,
VIC = 3.3 V,
Input = PRBS 223 −1
50
20
500 mV
300 mV
30
20
600 mV
800 mV
600 mV
10
5
800 mV
500 mV
0
0
0
100
200
300
400
500
f − Frequency − MHz
0
600
80
400
60
VCC = 3.3 V,
TA = 25°C,
VIC = 3.3 V,
Input = Clock
25
Peak-to-Peak Jitter − ps
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
200
400
600
800
1000
1200
Data Rate − Mbps
Figure 17.
Figure 18.
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|V ID| = 200 mV
350
300
70
60
250
50
200
40
150
30
Added Random Jitter
100
20
50
10
0
0
400
800
1200
1600
f − Frequency − MHz
Period Jitter − ps
PEAK-TO-PEAK JITTER
vs
FREQUENCY
0
2000
Figure 19.
PEAK-TO-PEAK JITTER
vs
DATA RATE
230
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|V ID| = 200 mV
Input = PRBS 223 −1
Peak-to-Peak Jitter − ps
200
170
140
110
80
50
20
0
500
1000 1500 2000
2500 3000 3500
Data Rate − Mbps
Figure 20.
12
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Product Folder Links :SN55LVCP22-SP
SN55LVCP22-SP
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SLLSE43A – JUNE 2012 – REVISED JANUARY 2014
APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
50 Ω
3.3 V or 5 V
3.3 V
SN65LVCP22
A
ECL
B
50 Ω
50 Ω
50 Ω
VTT = VCC -2 V
VTT
Figure 21. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V
50 Ω
3.3 V
50 Ω
SN65LVCP22
3.3 V
A
CML
B
50 Ω
50 Ω
3.3 V
Figure 22. Current-Mode Logic (CML)
3.3 V
3.3 V
50 Ω
SN65LVCP22
A
ECL
B
50 Ω
1.1 kΩ
VTT
1.5 kΩ
VTT = VCC -2 V
3.3 V
Figure 23. Single-Ended (LVPECL)
3.3 V or 5 V
50 Ω
3.3 V
SN65LVCP22
A
100 Ω
LVDS
B
50 Ω
Figure 24. Low-Voltage Differential Signaling (LVDS)
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Product Folder Links :SN55LVCP22-SP
13
SN55LVCP22-SP
SLLSE43A – JUNE 2012 – REVISED JANUARY 2014
www.ti.com
IN0 +
OUT0 +
IN0 -
OUT0 -
IN1 +
OUT1 +
IN1 -
OUT1 -
Figure 25. 2 x 2 Crosspoint
OUT0 +
IN +
OUT0 -
(1 or 2)
IN -
OUT1 +
OUT1 -
Figure 26. 1:2 Spitter
IN0 +
OUT0 +
IN0 -
OUT0 -
IN1 +
OUT1 +
IN1 -
OUT1 -
Figure 27. Dual Repeater
IN0 +
OUT +
IN0 MUX
IN1 +
(1 or 2)
OUT -
IN1 -
Figure 28. 2:1 MUX
14
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Product Folder Links :SN55LVCP22-SP
SN55LVCP22-SP
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SLLSE43A – JUNE 2012 – REVISED JANUARY 2014
REVISION HISTORY
Changes from Original (June 2012) to Revision A
Page
•
Added /EM bullet to FEATURES .......................................................................................................................................... 1
•
Deleted PACKAGE/ORDERING INFORMATION table ........................................................................................................ 2
•
Changed SWITCHING CHARACTERISTICS, tJIT and tJrms .................................................................................................. 6
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15
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-1124201VFA
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN55LVCP22W/EM
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
25 Only
5962-1124201VF
A
LVCP22W-SP
SN55LVCP22W/EM
EVAL ONLY
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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