Texas Instruments | Fault-Protected RS-485 Transceiver With Extended Common-Mode Range (Rev. A) | Datasheet | Texas Instruments Fault-Protected RS-485 Transceiver With Extended Common-Mode Range (Rev. A) Datasheet

Texas Instruments Fault-Protected RS-485 Transceiver With Extended Common-Mode Range (Rev. A) Datasheet
SN65HVD1792-EP
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SLLSEG8A – AUGUST 2013 – REVISED AUGUST 2013
Fault-Protected RS-485 Transceivers With Extended Common-Mode Range
Check for Samples: SN65HVD1792-EP
FEATURES
1
•
•
Bus-Pin Fault Protection to > ±70 V
Common-Mode Voltage Range (–20 V to 25 V)
More Than Doubles TIA/EIA 485 Requirement
Bus I/O Protection
– ±16 kV JEDEC HBM Protection
Reduced Unit Load for Up to 256 Nodes
Failsafe Receiver for Open-Circuit, ShortCircuit and Idle-Bus Conditions
Low Power Consumption
– Low Standby Supply Current, 1 μA Typ
– ICC 5 mA Quiescent During Operation
Power-Up, Power-Down Glitch-Free Operation
•
•
•
•
•
APPLICATIONS
•
Designed for RS-485 and RS-422 Networks
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DESCRIPTION
The SN65HVD1792 is designed to survive overvoltage faults such as direct shorts to power supplies, mis-wiring
faults, connector failures, cable crushes, and tool mis-applications. It is also robust to ESD events, with high
levels of protection to human-body model specifications.
The SN65HVD1792 combines a differential driver and a differential receiver, which operate from a single power
supply. The SN65HVD1792 is characterized from –40°C to 105°C.
VFAULT up to 70 V
M0092-01
ORDERING INFORMATION (1)
TA
–40°C to 105°C
(1)
(2)
PACKAGE (2)
ORDERABLE PART NUMBER
SOIC - D
SN65HVD1792TDREP
SN65HVD1792TDEP
TOP-SIDE MARKING
1792EP
VID NUMBER
V62/13620-01XE
V62/13620-01XE-T
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
SN65HVD1792-EP
SLLSEG8A – AUGUST 2013 – REVISED AUGUST 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
DRIVER FUNCTION TABLE
Input
Enable
D
DE
A
Outputs
H
H
H
L
Actively drive bus high
L
H
L
H
Actively drive bus low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
B
RECEIVER FUNCTION TABLE
Differential Input
Enable
Output
VID = VA – VB
RE
R
VIT+ < VID
L
H
Receive valid bus high
VIT– < VID < VIT+
L
?
Indeterminate bus state
VID < VIT–
L
L
Receive valid bus low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
D Package
(Top View)
NC
1
14
VCC
R
2
13
VCC
RE
3
12
A
DE
4
11
B
D
5
10
Z
GND
6
9
Y
GND
7
8
NC
NC - No internal connection
Pins 6 and 7 are connected together internally.
Pins 13 and 14 are connected together internally.
Logic Diagram (Positive Logic)
DE
D
RE
R
4
9
5
10
Y
Z
3
12
2
11
A
B
S0300-01
2
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ABSOLUTE MAXIMUM RATINGS (1)
VCC
VALUE
UNIT
–0.5 to 7
V
–70 to 70
V
–0.3 to VCC + 0.3
V
Supply voltage
Voltage range at bus pins
A, B pins
Input voltage range at any logic pin
Transient overvoltage pulse through 100 Ω per TIA-485
–100 to 100
V
–24 to 24
mA
Junction temperature
170
°C
IEC 60749-26 ESD (human-body model), bus terminals and GND
±16
kV
JEDEC Standard 22, Test Method A114 (human-body model), bus terminals and GND
±16
kV
JEDEC Standard 22, Test Method A114 (human-body model), all pins
±4
kV
±2
kV
±400
V
Receiver output current
TJ
JEDEC Standard 22, Test Method C101 (charged-device model), all pins
JEDEC Standard 22, Test Method A115 (machine model), all pins
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
SN65HVD1792-EP
THERMAL METRIC (1)
D
UNITS
14 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
70.8
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
25.3
ψJT
Junction-to-top characterization parameter (5)
8.2
ψJB
Junction-to-board characterization parameter (6)
25
θJCbot
Junction-to-case (bottom) thermal resistance (7)
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
29.4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VI
Input voltage at any bus terminal (separately or common mode) (1)
–20
25
V
VIH
High-level input voltage (driver, driver enable, and receiver enable inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver enable, and receiver enable inputs)
0
0.8
V
VID
Differential input voltage
–25
25
V
Output current, driver
–60
60
mA
8
mA
IO
UNIT
Output current, receiver
–8
RL
Differential load resistance
54
CL
Differential load capacitance
1/tUI
Signaling rate
TA
Operating free-air temperature (see application section for thermal information)
–40
105
°C
TJ
Junction temperature
–40
150
°C
(1)
60
Ω
50
pF
1
Mbps
By convention, the least positive (most negative) limit is designated as minimum in this data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
|VOD|
Driver differential output voltage
magnitude
Δ|VOD|
Change in magnitude of driver
differential output voltage
TEST CONDITIONS
RS-485 with common-mode load, VCC > 4.75 V, See
Figure 1
RL = 54 Ω, 4.75 V ≤ VCC ≤ 5.25 V
MIN
TYP
MAX
UNIT
1.37
V
1.5
2
2
2.5
–0.2
0
0.2
V
Steady-state common-mode output
voltage
1
VCC/2
3
V
ΔVOC
Change in differential driver output
common-mode voltage
–100
0
100
VOC(PP)
Peak-to-peak driver common-mode
output voltage
COD
Differential output capacitance
VIT+
Positive-going receiver differential input
voltage threshold
VIT–
Negative-going receiver differential input
voltage threshold
VHYS
Receiver differential input voltage
threshold hysteresis (VIT+ – VIT–)
VOH
Receiver high-level output voltage
RL = 100 Ω, 4.75 V ≤ VCC ≤ 5.25 V
VOC(SS)
RL = 54 Ω
Center of two 27-Ω load resistors, See Figure 2
IOH = –8 mA
IOH = –400 μA
VOL
Receiver low-level output voltage
II
Driver input, driver enable, and receiver
enable input current
IOZ
Receiver output high-impedance current
IOS
Driver short-circuit output current
II
Bus input current (disabled driver)
4
500
mV
23
pF
–100
VCM = –20 V to 25 V
–10
mV
–205
–150
mV
30
50
mV
2.4
VCC
– 0.3
V
4
IOL = 8 mA
0.2
–100
VO = 0 V or VCC, RE at VCC
VCC = 4.5 to 5.5 V or
VCC = 0 V, DE at 0 V
mV
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V
100
μA
–1
1
μA
–250
250
mA
VI = 12 V
VI = –7 V
0.5
75
–100
–40
125
μA
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
Supply current (quiescent)
TEST CONDITIONS
TYP
MAX
Driver and receiver
enabled
DE = VCC,
RE = GND,
no load
4
6.3
Driver enabled, receiver
disabled
DE = VCC,
RE = VCC,
no load
3
5.2
Driver disabled, receiver
enabled
DE = GND,
RE = GND,
no load
2
4.3
Driver and receiver
disabled
DE = GND,
D = open
RE = VCC,
no load
TJ = -40°C to
105°C
0.5
5.2
TJ = 150°C
15
29
TYP
MAX
UNIT
300
ns
200
ns
29
ns
3
μs
Supply current (dynamic)
MIN
UNIT
mA
μA
See TYPICAL CHARACTERISTICS section
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
DRIVER
tr, tf
Driver differential output rise/fall time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver differential output pulse skew,
|tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
50
RL = 54 Ω, CL = 50 pF, See Figure 3
Receiver enabled
tPZH, tPZL
Driver enable time
See Figure 4 and
Figure 5
Receiver disabled
Receiver enabled
VCM > VCC
300
ns
10
μs
500
ns
RECEIVER
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver output pulse skew,
|tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)
Receiver enable time
4
15
ns
100
200
ns
6
20
Driver enabled, See Figure 7
15
100
Driver enabled, See Figure 7
80
300
ns
Driver disabled, See Figure 8
3
9
μs
CL = 15 pF, See Figure 6
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ns
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PARAMETER MEASUREMENT INFORMATION
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω.
375 W ±1%
VCC
DE
0 V or 3 V
D
A
VOD
60 W ±1%
+
_
B
–20 V < V(test) < 25 V
375 W ±1%
S0301-01
Figure 1. Measurement of Driver Differential Output Voltage With Common-Mode Load
VCC
27 W ±1%
DE
Input
A
D
A
VA
B
VB
VOC(PP)
VOC
B
DVOC(SS)
CL = 50 pF ±20%
27 W ±1%
VOC
CL Includes Fixture and
Instrumentation Capacitance
S0302-01
Figure 2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
3V
VCC
DE
D
Input
Generator
VI
CL = 50 pF ±20%
A
VOD
50 W
B
RL = 54 W
±1%
CL Includes Fixture
and Instrumentation
Capacitance
VI
50%
50%
tPLH
VOD
tPHL
»2V
90% 90%
0V
10%
0V
10%
tr
» –2 V
tf
S0303-01
Figure 3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3V
D
DE
Input
Generator
VI
50 W
A
3V
S1
B
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VO
VI
RL = 110 W
± 1%
50%
50%
0.5 V
tPZH
VO
0V
VOH
90%
50%
tPHZ
»0V
S0304-01
NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 4. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
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PARAMETER MEASUREMENT INFORMATION (continued)
3V
A
3V
D
DE
Input
Generator
RL = 110 W
±1%
S1
»3V
VI
VO
50%
50%
0V
B
tPZL
tPLZ
CL = 50 pF ±20%
VI
50 W
»3V
CL Includes Fixture
and Instrumentation
Capacitance
VO
50%
10%
VOL
S0305-01
NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 5. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load
A
Input
Generator
R
50 W
VI
1.5 V
0V
VO
B
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Capacitance
3V
VI
50%
50%
0V
tPLH
VO
tPHL
90% 90%
50%
10%
tr
50%
10%
VOH
VOL
tf
S0306-01
Figure 6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
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PARAMETER MEASUREMENT INFORMATION (continued)
3V
VCC
DE
A
0 V or 3 V D
B
RE
Input
Generator
VI
1 kW ± 1%
R VO
S1
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
50%
0V
tPZH(1)
tPHZ
VOH
90%
VO
50%
D at 3 V
S1 to GND
»0V
tPZL(1)
tPLZ
VCC
VO
50%
D at 0 V
S1 to VCC
10%
VOL
S0307-01
Figure 7. Measurement of Receiver Enable/Disable Times With Driver Enabled
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
A
0 V or 1.5 V
R VO
S1
B
1.5 V or 0 V
RE
Input
Generator
VI
1 kW ± 1%
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
0V
tPZH(2)
VOH
VO
A at 1.5 V
B at 0 V
S1 to GND
50%
GND
tPZL(2)
VCC
VO
50%
VOL
A at 0 V
B at 1.5 V
S1 to VCC
S0308-01
Figure 8. Measurement of Receiver Enable Times With Driver Disabled
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TYPICAL CHARACTERISTICS
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
HVD1787 RMS SUPPLY CURRENT
vs
SIGNALING RATE
70
50
ICC − RMS Supply Current − mA
IO − Driver Output Current − mA
60
120
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
40
30
20
10
TA = 25°C
RE at VCC
DE at VCC
RL = 54 Ω
CL = 50 pF
VCC = 5 V
100
80
60
0
−10
0.0
40
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
VCC − Supply Voltage − V
5.4
0
2
4
6
8
10
Signaling Rate − Mbps
G001
G002
Figure 9.
Figure 10.
BUS PIN CURRENT
vs
BUS PIN VOLTAGE
2.0
IIN − Bus Pin Current − mA
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−90
−60
−30
0
30
60
VIN − Bus Pin Voltage − V
90
G004
Figure 11.
10
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TYPICAL CHARACTERISTICS (continued)
VOD - Differential Output Voltage - V
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL LOAD CURRENT
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Load = 100 W
Load = 300 W
VCC = 5.5 V
VCC = 5 V
Load = 60 W
VCC = 4.5 V
0 2 4
6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
Idiff - Differential Load Current - mA
Figure 12.
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ADDITIONAL OPTIONS
The SN65HVD1792 also has options for J1708 applications, for always-enabled full-duplex versions (industrystandard SN65LBC179 footprint) and for inverting-polarity versions, which allow users to correct a reversal of the
bus wires without re-wiring. Contact your local Texas Instruments representative for information on these options.
PART NUMBER
SN65HVD1792
FOOTPRINT/FUNCTION
SLOW
MEDIUM
FAST
Half-duplex (176 pinout)
85
86
87
Full-duplex no enables (179 pinout)
88
89
90
Full-duplex with enables (180 pinout)
91
92
93
Half-duplex with cable invert
94
95
96
Full-duplex with cable invert and enables
97
98
99
J1708
08
09
10
xxx
D Package
(Top View)
1
RINV
12
2
RINV
1
14
VCC
R
2
13
VCC
RE
3
12
A
DE
4
11
B
A
R
11
B
3
RE
8
9
5
10
Y
DINV
D
5
10
Z
GND
6
9
Y
GND
7
8
DINV
D
Z
4
DE
Figure 13. SN65HVD1792 With Inverting Feature to Correct for Miswired Cables
APPLICATION INFORMATION
Hot-Plugging
The SN65HVD1792 is designed to operate in "hot swap" or "hot pluggable" applications. Key features for hotpluggable applications are power-up, power-down glitch free operation, default disabled input/output pins, and
receiver failsafe. As shown in Figure 9, an internal Power-On Reset circuit keeps the driver outputs in a highimpedance state until the supply voltage has reached a level at which the device will reliably operate. This
ensures that no spurious transitions (glitches) will occur on the bus pin outputs as the power supply turns on or
turns off.
As shown in the device FUNCTION TABLE, the ENABLE inputs have the feature of default disable on both the
driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the
R pin until the associated controller actively drives the enable pins.
12
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Receiver Failsafe
The differential receiver is “failsafe” to invalid bus states caused by:
• open bus conditions such as a disconnected connector,
• shorted bus conditions such as cable damage shorting the twisted-pair together,
• or idle bus conditions that occur when no driver on the bus is actively driving.
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the
receiver is not indeterminate.
In the SN65HVD1792, receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input
indeterminate” range does not include zero volts differential. In order to comply with the RS-422 and RS-485
standards, the receiver output must output a High when the differential input VID is more positive than 200 mV,
and must output a Low when the VID is more negative than -200 mV. The SN65HVD1792 receiver parameters
which determine the failsafe performance are VIT+ and VIT- and VHYS. In the Electrical Characteristics table, VIThas a typical value of -150 mV and a minimum (most negative) value of -200 mV, so differential signals more
negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than
200 mV will always cause a High receiver output, because the typical value of VIT+ is -100mV, and VIT+ is never
more positive than -10 mV under any conditions of temperature, supply voltage, or common-mode offset.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output
will be High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low
state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis
value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+.
For the SN65HVD1792, the typical noise immunity is typically about 150 mV, which is the negative noise level
needed to exceed the VIT- threshold (VIT- TYP = -150 mV). In the worst case, the failsafe noise immunity is never
less than 40 mV, which is set by the maximum positive threshold (VIT+ MAX = -10mV) plus the minimum
hysteresis voltage (VHYS MIN = 30 mV).
70-V Fault-Protection
The SN65HVD1792 is designed to survive bus pin faults up to ±70V. The devices designed for fast signaling rate
(10 Mbps) will not survive a bus pin fault with a direct short to voltages above 30V when:
1. the device is powered on AND
2a. the driver is enabled (DE=HIGH) AND D=HIGH AND the bus fault is applied to the A pin OR
2b. the driver is enabled (DE=HIGH) AND D=LOW AND the bus fault is applied to the B pin
Under other conditions, the device will survive shorts to bus pin faults up to 70V. Table 1 summarizes the
conditions under which the device may be damaged, and the conditions under which the device will not be
damaged.
Table 1. Device Conditions
POWER
DE
D
A
B
OFF
X
X
-70V < VA < 70V
-70V < VB < 70V
RESULTS
Device survives
ON
LO
X
-70V < VA < 70V
-70V < VB < 70V
Device survives
ON
HI
L
-70V < VA < 70V
-70V < VB < 30V
Device survives
ON
HI
L
-70V < VA < 70V
30V < VB
ON
HI
H
-70V < VA < 30V
-70V < VB < 30V
Device survives
ON
HI
H
30V < VA
-70V < VB < 30V
Damage may occur
Damage may occur
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: SN65HVD1792-EP
13
PACKAGE OPTION ADDENDUM
www.ti.com
17-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
SN65HVD1792TDEP
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1792EP
SN65HVD1792TDREP
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1792EP
V62/13620-01XE
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1792EP
V62/13620-01XE-T
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1792EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Sep-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD1792-EP :
• Catalog: SN65HVD1792
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65HVD1792TDREP
Package Package Pins
Type Drawing
SOIC
D
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
9.0
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD1792TDREP
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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