Texas Instruments | Low-Voltage High-Speed Quadruple Differential Line Reciever. (Rev. A) | Datasheet | Texas Instruments Low-Voltage High-Speed Quadruple Differential Line Reciever. (Rev. A) Datasheet

Texas Instruments Low-Voltage High-Speed Quadruple Differential Line Reciever. (Rev. A) Datasheet
AM26LV32E-EP
www.ti.com
SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
LOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH ±15-kV IEC ESD PROTECTION
Check for Samples: AM26LV32E-EP
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
Meets or Exceeds Standard TIA/EIA-422-B and
ITU Recommendation V.11
Operates From a Single 3.3-V Power Supply
ESD Protection for RS422 Bus Pins
– ±15-kV Human-Body Model (HBM)
– ±8-kV IEC61000-4-2, Contact Discharge
– ±15-kV IEC61000-4-2, Air-Gap Discharge
Switching Rates up to 32 MHz
Low Power Dissipation: 27 mW Typ
Open-Circuit, Short-Circuit, and Terminated
Fail-Safe
±7-V Common-Mode Input Voltage Range With
±200-mV Sensitivity
Accepts 5-V Logic Inputs With 3.3-V Supply
(Enable Inputs)
Input Hysteresis: 35 mV Typ
Pin-to-Pin Compatible With AM26C32,
AM26LS32
Ioff Supports Partial-Power-Down Mode
Operation
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
D PACKAGE
(TOP VIEW)
1B
1A
1Y
G
2Y
2A
2B
GND
(1)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
Additional temperature ranges are available – contact factory
DESCRIPTION/ORDERING INFORMATION
The AM26LV32E consists of quadruple differential line receivers with 3-state outputs. These differential receivers
have ±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact
Discharge) protection for RS422 bus pins.
This device is designed to meet TIA/EIA-422-B and ITU recommendation V.11 drivers with reduced supply
voltage. The device is optimized for balanced bus transmission at switching rates up to 32 MHz. The 3-state
outputs permit connection directly to a bus-organized system.
The AM26LV32E has an internal fail-safe circuitry that prevents the device from putting an unknown voltage
signal at the receiver outputs. In the open fail-safe, shorted fail-safe, and terminated fail-safe, a high state is
produced at the respective output.
This device is supported for partial-power-down applications using Ioff. Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The AM26LV32EM is characterized for operation from –55°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
AM26LV32E-EP
SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
www.ti.com
Table 1. ORDERING INFORMATION
TA
–55°C to 125°C
(1)
(2)
PACKAGE
SOIC – D
(1) (2)
ORDERABLE PART NUMBER
Tape and reel
AM26LV32EMDREP
TOP-SIDE MARKING
A26LV32EMP
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
FUNCTION TABLE (1)
(each receiver)
ENABLES
DIFFERENTIAL
INPUT
VID ≥ 0.2 V
–0.2 V < VID < 0.2 V
G
H
X
H
X
L
H
H
X
?
X
L
?
H
X
L
X
L
L
Open, shorted, or
terminated
H
X
H
X
L
H
X
L
H
Z
VID ≤ –0.2 V
(1)
OUTPUT
G
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
LOGIC DIAGRAM (POSITIVE LOGIC)
G 4
12
G
1A 2
1B 1
2A 6
2B 7
3A 10
3B 9
4A 14
4B 15
2
3 1Y
5 2Y
11 3Y
13 4Y
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Product Folder Links: AM26LV32E-EP
AM26LV32E-EP
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SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
SCHEMATIC
EQUIVALENT OF EACH INPUT (A, B)
EQUIVALENT OF EACH
ENABLE INPUT (G, G)
VCC
TYPICAL OF EACH RECEIVER OUTPUT
VCC
VCC
2.4 kΩ
5 kΩ
7 kΩ
Enable
G, G
1.5 kΩ
A, B
200 kΩ
Output
1.5 kΩ
VCC(A)
or
GND(B)
2.4 kΩ
GND
GND
GND
All resistor values are nominal.
ABSOLUTE MAXIMUM RATINGS (1)
(2)
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
VI
Supply voltage range
(3)
Input voltage range
MAX
UNIT
–0.5
6
V
A or B inputs
–14
14
V
Enable Inputs
–0.5
6
V
–14
14
V
–0.5
6
(4)
VID
Differential input voltage
VO
Output voltage range
IIK
Input clamp current range
VI < 0
–20
mA
IOK
Output clamp current range
VO < 0
–20
mA
lO
Maximum output current
±20
mA
TJ
Operating virtual junction temperature
150
°C
θJA
Package thermal impedance (5)
73
°C/W
TA
Operating free-air temperature range
–55
125
°C
Tstg
Storage temperature range
–65
150
°C
(1)
(2)
(3)
(4)
(5)
(6)
(6)
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This device is designed to meet TIA/EIA-422-B and ITU.
All voltage values except differential input voltage are with respect to the network GND.
Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Selecting the maximum of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
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3
AM26LV32E-EP
SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
V
VIH
Enable high-level input voltage
2
5.5
V
VIL
Enable low-level input voltage
0
0.8
V
VIC
Common-mode input voltage
–7
7
V
VID
Differential input voltage
–7
7
V
IOH
High-level output current
–5
mA
IOL
Low-level output current
5
mA
TA
Operating free-air temperature
125
°C
–55
UNIT
ELECTRICAL CHARACTERISTICS
over recommended ranges of common-mode input, supply voltage, and operating free-air temperature (unless otherwise
noted)
PARAMETER
VIT+
Positive-going input threshold voltage,
differential input
VIT–
Negative-going input threshold voltage,
differential input
Vhys
Input hysteresis (VIT+ – VIT–)
VIK
Input clamp voltage, G and G
TEST CONDITIONS
MIN
–0.2
35
High-level output voltage
VOL
Low-level output voltage
IOZ
High-impedance state output current
VO = VCC or GND
Ioff
Output current with power off
VCC = 0 V, VO = 0 or 5.5 V
VID = –200 mV, IOL = 5 mA
V
0.17
VID = –200 mV, IOL = 100 μA
0.5
0.1
±50
μA
μA
1.5
VI = –10 V
–2.5
Line input current
Other input at 0 V
II
Enable input current, G and G
VI = VCC or GND
ri
Input resistance
VIC = –7 V to 7 V, Other input at 0 V
ICC
Supply current (total package)
G, G = VCC or GND, No load, Line inputs open
Cpd
Power dissipation capacitance (2)
One channel
±1
4
17
8
150
V
±100
VI = 10 V
II
V
3.2
VCC –
0.1
VID = 200 mV, IOH = –100 μA
V
mV
–1.5
2.4
UNIT
V
II = –18 mA
VOH
4
MAX
0.2
VID = 200 mV, IOH = –5 mA
(1)
(2)
TYP (1)
mA
μA
kΩ
17
mA
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
Cpd determines the no-load dynamic current consumption: IS = Cpd × VCC × f + ICC
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AM26LV32E-EP
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SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
8
16
26
ns
8
16
26
ns
UNIT
tPLH
Propagation delay time, low- to high-level output
tPHL
Propagation delay time, high- to low-level output
tt
Transition time
See Figure 1
5
tPZH
Output-enable time to high level
See Figure 2
17
40
ns
tPZL
Output-enable time to low level
See Figure 3
10
40
ns
tPHZ
Output-disable time from high level
See Figure 2
20
40
ns
tPLZ
Output-disable time from low level
See Figure 3
16
40
ns
See Figure 1
ns
tsk(p)
Pulse skew
See Figure 1
(2)
4
6
ns
tsk(o)
Pulse skew
See Figure 1
(3)
4
6
ns
tsk(pp)
Pulse skew (device to device)
See Figure 1
(4)
6
9
ns
f(max)
Maximum operating frequency
See Figure 1
(1)
(2)
(3)
(4)
32
MHz
All typical values are at VCC = 3.3 V, TA = 25°C.
tsk(p) is |tpLH – tpHL| of each channel of same device.
tsk(o) is the maximum difference in propagation delay times between any two channels of same device switching in the same direction.
tsk(pp) is the maximum difference in propagation delay times between any two channels of any two devices switching in the same
direction.
ESD PROTECTION
PARAMETER
Receiver input
TEST CONDITIONS
TYP
HBM
±15
IEC61000-4-2, Air-Gap Discharge
±15
IEC61000-4-2, Contact Discharge
±8
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UNIT
kV
5
AM26LV32E-EP
SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
www.ti.com
PARAMETER MEASUREMENT INFORMATION
A.
CL includes probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 10 MHz, duty cycle = 50%,
tr = tf ≤ 2ns.
C.
To test the active-low enable G, ground G and apply an inverted waveform G.
A
Generator
(see Note B)
Y
VO
B
50 Ω
CL = 15 pF
(see Note A)
50 Ω
A
2V
B
1V
Input
tPLH
VCC
Output
G
G
(see Note C)
tPHL
90%
50%
10%
90%
tr
VOH
50%
10% V
OL
tf
Figure 1. Test Circuit and Voltage Waveforms, tPLH and tPHL
A.
CL includes probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 10 MHz, duty cycle = 50%,
tr = tf ≤ 2ns.
C.
To test the active-low enable G, ground G and apply an inverted waveform G.
VID = 1 V
A
Y
VO
B
CL = 15 pF
(see Note A)
RL = 2 kΩ
G
Generator
(see Note B)
50 Ω
G
VCC
(see Note C)
VCC
Input
50%
50%
0V
tPZH
Output
tPHZ
VOH
VOH - 0.3 V
Voff ≈ 0
Figure 2. Test Circuit and Voltage Waveforms, tPZH and tPHZ
6
A.
CL includes probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 10 MHz, duty cycle = 50%,
tr = tf ≤ 2ns.
C.
To test the active-low enable G, ground G and apply an inverted waveform G.
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Product Folder Links: AM26LV32E-EP
AM26LV32E-EP
www.ti.com
SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 2 kΩ
A
VID = 1 V
Y
VO
B
CL = 15 pF
(see Note A)
G
Generator
(see Note B)
50 Ω
G
VCC
(see Note C)
VCC
Input
50%
50%
0V
tPZL
tPLZ
Voff ≈ V CC
Output
VOL + 0.3 V
VOL
Figure 3. Test Circuit and Voltage Waveforms, tPZL and tPLZ
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Product Folder Links: AM26LV32E-EP
7
AM26LV32E-EP
SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
www.ti.com
REVISION HISTORY
Changes from Original (November 2008) to Revision A
•
8
Page
Changed units for VIC and VID recommended operating conditions from mA to V ............................................................... 4
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AM26LV32EMDREP
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
-55 to 125
A26LV32EMP
V62/09602-01XE
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
A26LV32EMP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jun-2019
OTHER QUALIFIED VERSIONS OF AM26LV32E-EP :
• Catalog: AM26LV32E
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
AM26LV32EMDREP
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AM26LV32EMDREP
SOIC
D
16
2500
346.0
346.0
33.0
Pack Materials-Page 2
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