Texas Instruments | LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer (Rev. L) | Datasheet | Texas Instruments LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer (Rev. L) Datasheet

Texas Instruments LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer (Rev. L) Datasheet
LM2502
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SNLS176L – JANUARY 2004 – REVISED MAY 2013
Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer
Check for Samples: LM2502
FEATURES
DESCRIPTION
•
•
•
•
•
•
The LM2502 device is a dual link display interface
SERDES that adapts existing CPU / video busses to
a low power current-mode serial MPL link. The
chipset may also be used for a RGB565 application
with glue logic. The interconnect is reduced from 22
signals to only 3 active signals with the LM2502
chipset easing flex interconnect design, size and cost.
1
2
•
•
•
•
•
•
>300 Mbps Dual Link Raw Throughput
MPL Physical Layer (MPL-0)
Pin Selectable Master / Slave Mode
Frequency Reference Transport
Complete LVCMOS / MPL Translation
Interface Modes:
– 16-bit CPU, i80 or m68 Style
– RGB565 with Glue Logic
−30°C to 85°C Operating Range
Link Power Down Mode Reduces IDDZ < 10 µA
Dual Display Support (CS1* & CS2*)
Via-less MPL Interconnect Feature
3.0V Supply Voltage (VDD and VDDA)
Interfaces to 1.7V to 3.3V Logic (VDDIO)
The Master Serializer (SER) resides beside an
application processor or baseband processor and
translates a parallel bus from LVCMOS levels to
serial MPL levels for transmission over a flex cable
and PCB traces to the Slave Deserializer (DES)
located near the display module.
Dual display support is provided for a primary and
sub display through the use of two ChipSelect
signals. A Mode pin selects either a i80 or m68 style
interface.
The Power_Down (PD*) input controls the power
state of the MPL interface. When PD* is asserted, the
MD1/0 and MC signals are powered down to save
current.
SYSTEM BENEFITS
•
•
•
•
•
Small Interface
Low Power
Low EMI
Frequency Reference Transport
Intrinsic Level Translation
The LM2502 implements the physical layer of the
MPL Standard (MPL-0). The LM2502 is offered in
NOPB (Lead-free) NFBGA and WQFN packages.
Typical Application Diagram
BBP
or
APP
Processor
Memory Port
(Display)
LM2502 MPL Master
INTR
R/W*(WR*)
E (RD*)
A/D
D[15:0]
CS2*
CS1*
LM2502 MPL Slave
MC
MD0
CLK
CLK (optional)
R/W*(WR*)
R/W*
E (RD*)
A/D
D[15:0]
CS2*
CS1*
PD*
Mode
PD*
M/S* = H
PLL_CON[2:0],
Mode are application
dependent
M/S*
PLL_Con[2:0]
Mode
GND
MD1
GND
CLKDIS*
PLL_Con
[2:0]
Primary
Display
(A)
Sub
Display
(B)
M/S*
M/S* = L
PLL_CON[2:0], Mode, CLKDIS* are application
dependent, PD* = GPIO
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LM2502
SNLS176L – JANUARY 2004 – REVISED MAY 2013
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NFBGA Connection Diagram
Ball A1
A
B
C
D
E
F
G
1
2
3
4
5
6
7
TOP VIEW
(not to scale)
Table 1. Ball Assignment (1)
(1)
2
Ball #
Master
Slave
Ball #
Master
Slave
A1
D0
D0
D5
NC
NC
A2
D1
D1
D6
VSScore
VSScore
A3
D2
D2
D7
VDDcore
VDDcore
D8
A4
VDDA
VDDA
E1
D8
A5
INTR
CLKDIS*
E2
D9
D9
A6
MD1
MD0
E3
NC
NC
A7
MC
MC
E4
NC
NC
B1
D3
D3
E5
NC
NC
B2
D4
D4
E6
CS1*
CS1*
B3
D5
D5
E7
PLLCON2
PLLCON2
B4
VSSA
VSSA
F1
D10
D10
B5
M/S*
M/S*
F2
D11
D11
B6
Mode
Mode
F3
D12
D12
VSSIO
B7
MD0
MD1
F4
VSSIO
C1
D6
D6
F5
MF0
MF0
C2
D7
D7
F6
PLLCON1
PLLCON1
C3
NC
NC
F7
PD*
PD*
C4
NC
NC
G1
D13
D13
C5
NC
NC
G2
D14
D14
C6
CS2*
CS2*
G3
D15
D15
VDDIO
C7
MF1
MF1
G4
VDDIO
D1
VDDIO
VDDIO
G5
A/D
A/D
D2
VSSIO
VSSIO
G6
PLLCON0
PLLCON0
D3
NC
NC
G7
CLK
CLK
D4
NC
NC
NC = Not Connected
Note: Three pins are different between Master and Slave configurations - see also Figure 17
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WQFN Connection Diagram
D11
D10
D9
D8
VDDIO
VSSIO
D6
D7
D3
D0
10
9
8
7
6
5
4
3
2
1
D13
11
40
D4
D14
12
39
D1
D12
13
38
D5
D15
14
37
D2
VSSIO
15
36
VDDA
VDDIO
16
35
VSSA
A/D
17
34
LM2502SQ
TOP VIEW
40 Lead WQFN
5mm x 5mm x 0.8mm
0.4mm pitch
(not to scale)
INTRM /
CLKDIS*S
MF0
18
PLLCON0
PLLCON1
(DAP connection, center pad = GND)
33
M/S*
19
32
MD1M / MD0S
20
31
MC
27
28
29
30
MF1
CS2*
MD0M / MD1S
MODE
PLLCON2
VDDcore
24
CS1*
26
23
PD*
VSScore
22
CLK
25
21
TOP VIEW
(not to scale)
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Table 2. Pad Assignment (1)
(1)
Pin #
Master
Slave
Ball #
Master
Slave
1
D0
D0
21
CLK
CLK
2
D3
D3
22
PD*
PD*
3
D7
D7
23
CS1*
CS1*
4
D6
D6
24
PLLCON2
PLLCON2
5
VSSIO
VSSIO
25
VSScore
VSScore
6
VDDIO
VDDIO
26
VDDcore
VDDcore
7
D8
D8
27
MF1
MF1
8
D9
D9
28
CS2*
CS2*
9
D10
D10
29
MD0M
MD1S
10
D11
D11
30
MODE
MODE
11
D13
D13
31
MC
MC
12
D14
D14
32
MD1M
MD0S
13
D12
D12
33
M/S*
M/S*
14
D15
D15
34
INTRM
CLKDIS*S
15
VSSIO
VSSIO
35
VSSA
VSSA
16
VDDIO
VDDIO
36
VDDA
VDDA
17
A/D
A/D
37
D2
D2
18
MF0
MF0
38
D5
D5
19
PLLCON0
PLLCON0
39
D1
D1
20
PLLCON1
PLLCON1
40
D4
D4
DAP
GND
GND
DAP
GND
GND
Note: Three pins are different between Master and Slave configurations.
Pin Descriptions
Pin Name
No.
of Pins
I/O, Type (1)
Description
Master (SER)
Slave (DES)
MPL SERIAL BUS PINS
MD[1:0]
2
IO, MPL
MPL Data Line Driver/Receiver
MPL Data Receiver/Line Driver
MC
1
IO, MPL
MPL Clock Line Driver
MPL Clock Receiver
Ground
MPL Ground - see Power/Ground Pins
MPL Ground - see Power/Ground Pins
VSSA
CONFIGURATION/PARALLEL BUS PINS
M/S*
1
I,
LVCMOS
Master/Slave* Input,
M/S* = H for Master
Master/Slave* Input
M/S* = L for Slave
PD*
1
I,
LVCMOS
Power_Down* Input,
H = Active
L = Power Down Mode
Power_Down* Input,
H = Active
L = Power Down Mode
MF0
(E or RD*)
1
IO,
LVCMOS
Multi-function Input Zero (0):
If MODE = L (m68 mode), E input pin, data is
latched on E High-to-Low transition or E may
be static High and Data is latched on CS*
Low-to-High edge
If MODE = H (i80 mode), Read Enable input
pin, active low. Read data is driven when both
RD* and CS* are Low.
Multi-function Output Zero (0):
If MODE = L (m68 mode),
E output pin, static High.
If MODE = H (i80 mode),
Read Enable output pin, active Low.
MF1
(R/W* or
WR*)
1
IO,
LVCMOS
Multi-function Input One (1):
If Mode = L (m68 mode), Read/Write* pin,
Read High, Write* Low
If Mode = H (i80 mode), Write* enable input
pin, active Low. Write data is latched on the
Low-to-High transition of either WR* or CS*
(which ever occurs first).
Multi-function Output One (1):
If Mode = L (m68 mode)
Read/Write* pin,
Read High, Write* Low
If Mode = H (i80 mode)
Write* enable output pin, active Low.
(1)
4
Note: I = Input, O = Output, IO = Input/Output, VDDIO ≤ VDD (VDDA = VDDcore). Do not float input pins.
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Pin Descriptions (continued)
Description
Pin Name
No.
of Pins
I/O, Type (1)
CS1*
1
IO,
LVCMOS
ChipSelect1* – Input
H = Ignored
L = Active
ChipSelect1* – Output
H = Ignored
L = Active
CS2*
1
IO,
LVCMOS
ChipSelect2* – Input
H = Ignored
L = Active
ChipSelect2* – Output
H = Ignored
L = Active
A/D (RS or
A0)
1
IO,
LVCMOS
Address/Data – Input
H = Data
L = Address (Command)
Address/Data – Output
H = Data
L = Address (Command)
D[15:0]
16
IO,
LVCMOS
Data Bus – Inputs/Outputs
Data Bus – Outputs/Inputs
INTR
or
CLKDIS*
1
O or I,
LVCMOS
INTR is asserted when the read data is ready
and de-asserted upon a second CPU Read
cycle.
Clock Disable - CLKDIS*:
H = CLK output ON
L = CLK output LOW, allows for the Slave
clock output to be held static if not used.
CLK
1
IO,
LVCMOS
Clock Input
Clock Output (Frequency Reference) – no
phase relationship to data – frequency
reference only.
Mode
1
I,
LVCMOS
Mode Input Pin
H = i80 Mode,
L = m68 Mode
Mode Input Pin
H = i80 Mode,
L = m68 Mode
PLL_CON
[2:0]
3
I,
LVCMOS
PLL Configuration Input Pins – see Table 12
Clock Divisor Configuration Input Pins – see
Table 12
Master (SER)
Slave (DES)
POWER/GROUND PINS
VDDA
1
Power
Power Supply Pin for the MPL Interface. 2.9V to 3.3V
VSSA
1
Ground
Ground Pin for the MPL Interface, a low impedance ground path is required between the
Master and the Slave device - see Applications Information section.
VDDcore
1
Power
Power Supply Pin for the digital core. 2.9V to 3.3V
VSScore
1
Ground
Ground Pin for the digital core.
VDDIO
2
Power
Power Supply Pin for the parallel interface. 1.7V to 3.3V
VSSIO
2
Ground
Ground Pin for the parallel interface.
9
NC
1
Ground
Not Connected (C3-5, D3-5, E3-5). NFBGA Package only.
DAP = Ground. WQFN Package only.
Table 3. Master Pinout - NFBGA Package
MST
1
2
3
4
5
6
7
A
D0
D1
D2
VDDA
INTR
MD1
MC
B
D3
D4
D5
VSSA
M/S*
Mode
MD0
C
D6
D7
NC
NC
NC
CS2*
MF1
D
VDDIO
VSSIO
NC
NC
NC
VSScore
VDDcore
E
D8
D9
NC
NC
NC
CS1*
PLLCON2
F
D10
D11
D12
VSSIO
MF0
PLLCON1
PD*
G
D13
D14
D15
VDDIO
A/D
PLLCON0
CLK
6
7
Table 4. Slave Pinout - NFBGA Package
SLV
1
2
3
4
5
A
D0
D1
D2
VDDA
CLKDIS*
MD0
MC
B
D3
D4
D5
VSSA
M/S*
Mode
MD1
C
D6
D7
NC
NC
NC
CS2*
MF1
D
VDDIO
VSSIO
NC
NC
NC
VSScore
VDDcore
E
D8
D9
NC
NC
NC
CS1*
PLLCON2
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Table 4. Slave Pinout - NFBGA Package (continued)
SLV
1
2
3
4
5
6
7
F
D10
D11
D12
VSSIO
MF0
PLLCON1
PD*
G
D13
D14
D15
VDDIO
A/D
PLLCON0
CLK
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Supply Voltage (VDDA)
−0.3V to +4.0 V
Supply Voltage (VDD)
−0.3V to +4.0 V
−0.3V to +4.0 V
Supply Voltage (VDDIO)
LVCMOS Input/Output Voltage
−0.3V to (VDDIO +0.3) V
MPL Input/Output Voltage
−0.3V to (VDDA +0.3) V
Junction Temperature
+150 °C
Storage Temperature
−65°C to +150 °C
Lead Temperature Soldering,
40 Seconds
+260 °C
ESD Ratings:
≥±2 kV
HBM, 1.5 kΩ, 100pF
≥±200 V
EIAJ, 0Ω, 200 pF
Maximum Package Power Dissipation
Capacity at 25°C
NFBGA Package
(3)
2.5 W
Derate NFBGA Package above 25°C
25 mW/°C
Theta JA
45 °C/W
WQFN Package
(3)
1.39 W
Derate WQFN Package above 25°C
11 mW/°C
Theta JA
(1)
(2)
(3)
90 °C/W
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
NFBGA assumes 4 layer PCB, WQFN assumes 2 layer PCB for thermal calculations.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Min
Typ
Max
Units
VDDA to VSSA and VDDcore to VSScore
2.9
3.0
3.3
V
VDDIO to VSSIO
1.7
3.3
V
Clock Frequency
3.0
26
MHz
Ambient Temperature
−30
85
°C
6
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ELECTRICAL CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
3.67 IB
5.0 IB
6.33 IB
µA
MPL
IOLL
Logic Low Current (5X IB)
IOMS
Mid Scale Current
IOLH
Logic High Current (1X IB)
IB
Current Bias
IOFF
MPL Leakage Current
3.0 IB
0.7 IB
1.0 IB
µA
1.3 IB
150
PD* = L (PowerDown mode)
−2
0
µA
µA
+2
µA
VDDIO +0.3
V
0.3 VDDIO
V
LVCMOS (1.7V to 3.3V Operation)
VIH
Input Voltage High Level
VDDIO = 2.0V to 3.3V
0.7 VDDIO
VDDIO = 1.7V to <2.0V
0.8 VDDIO
VDDIO = 2.0V to 3.3V
−0.3
VDDIO = 1.7V to <2.0V
−0.3
VIL
Input Voltage Low Level
VHY
Input Hysteresis
IIN
Input Current (includes IOZ)
LVCMOS IO Signals
−2
0
+2
µA
IIH
Input Current High Level
LVCMOS Input Only Signals (i.e. Mode)
−1
0
+1
µA
IIL
Input Current Low Level
−1
0
+1
µA
VOH
Output Voltage High Level
VDDIO = 3.0V
VDDIO = 1.8V
IOH = −2 mA
VDDIO = 3.3V
IOS
Output Voltage Low Level
Output Short-Circuit Current
IOL = 2 mA
0.8 VDDIO
mV
2.8
V
1.6
VDDIO = 3.3V
0.08
VDDIO = 1.7V
0.12
V
mV
300
VDDIO = 1.7V
VOL
0.2 VDDIO
500
0.2 VDDIO
V
VOUT = 0V, VDDIO = 1.7 V
−5
mA
VOUT = 0V, VDDIO = 3.3 V
−30
mA
SUPPLY CURRENT
IDD
Total Supply
Current—Enabled
Conditions: MC = 76.8 MHz,
MD = 1010-0101 pattern
(worse case toggle, rail-to-rail
levels), CLK = 19.2 MHz
(4X) (3)
Master
VDDIO
Slave, CL = 10 pF
IDDZ
(1)
(2)
(3)
Supply Current—Disabled
220
µA
VDD = VDDA
14
25
mA
VDDIO
1.5
9.0
mA
9.0
13.0
mA
VDD = VDDA
Total Supply
Master
Current—Enabled
Conditions: MC = 20 MHz, MD
Slave, CL = 10 pF
= 1010-0101 pattern (worse
case toggle, rail-to-rail levels),
CLK = 5 MHz (4X)
15
VDDIO = 1.8V
10
µA
VDD = VDDA = 3V
5
mA
VDDIO = 1.8V
1
mA
VDD = VDDA = 3V
4
mA
Power_Down Mode, PD* = 0V
1
10
µA
Typical values are given for VDDIO = 1.8V and VDD = VDDA = 3.0V and TA = 25°C.
Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground
unless otherwise specified.
Typical supply condition is VDDIO = 1.8V and VDD = VDDA = 3.0V, Maximum supply condition is VDDIO = VDD = VDDA = 3.3V for the IDD
parameter.
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SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified. (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PARALLEL BUS TIMING
tSET
Set Up Time, Data to Edge
tHOLD
Hold Time, Edge to Data
tRISE
Rise Time
tFALL
Fall Time
CLKDC
Output Clock Duty Cycle
Inputs
5
ns
5
See Figure 2,
Outputs,
CL = 10 pF
Edge sensitive
outputs tested only:
m68 mode: CS1*,
CS2* and CLKout
i80 mode: RD*,
WR*, and CLKout
ns
VDDIO = 1.7V
2
7
14
ns
VDDIO = 3.3V
1
2
10
ns
VDDIO = 1.7V
2
6
14
ns
1
2
10
ns
VDDIO = 3.3V
CLKDIS* = H, Slave (DES)
50
%
Parallel Bus Timing - See Figure 13 Figure 14 Figure 15 Figure 16 and
Table 7, Table 8, Table 9, and Table 10
SERIAL BUS TIMING
tDVBC
Data Valid before Clock
tDVAC
Data Valid after Clock
Master-to-Slave
(2)
2.0
ns
0.5
ns
POWER UP TIMING (2)
t0
Master PLL Lock Counter
t1
MC Pulse Width Low (Master)
t2
MC Pulse Width HIGH
(Master)
t3
MC Pulse Width Low (Master)
t4
CLK-Out Delay (Slave)
t5
Power Up Total delay
(t0 + t1 + t2 + t3 + t4)
See Figure 6
4096
CLK
cycles
11
CLK
cycles
11
CLK
cycles
11
CLK
cycles
7
MC
cycles
4133
CLK
cycles
MPL POWER OFF TIMING
tPAZ
Disable Time to Power Down
See Figure 7, This parameter is
functionally tested by the IDDZ parameter.
50
ms
Max
Units
3
26
MHz
38.5
333
ns
60
%
14
ns
(3)
(1)
(2)
(3)
Typical values are given for VDDIO = 1.8V and VDD = VDDA = 3.0V and TA = 25°C.
This parameter is specified by design based on simulation or bench characterization.
This parameter is specified by a ATE tester delay, actual turn off time is faster.
RECOMMENDED INPUT TIMING REQUIREMENTS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
(1)
Typ
MASTER REFERENCE CLOCK (CLK)
See Table 12 (2)
fCLK
Clock Frequency
tCP
Clock Period
CLKDC
Clock Duty Cycle
40
tT
Clock Transition Times (Rise
or Fall, 20%–80%)
1
(1)
(2)
8
50
Typical values are given for VDDIO = 1.8V and VDD = VDDA = 3.0V and TA = 25°C.
This parameter is specified by design based on simulation or bench characterization.
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TIMING DIAGRAMS
MC
MD0 /
MD1
tDVBC
tDVAC
tDVBC
tDVAC
Figure 1. Serial Data Valid—Master to Slave
80%
SLV
Outputs
20%
tRISE
tFALL
Figure 2. Slave Output Rise and Fall Time
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FUNCTIONAL DESCRIPTION
BUS OVERVIEW
The LM2502 is a dual link Transceiver configurable part that supports a 16-bit CPU (m68 or i80) style interface.
The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while
requiring the fewest number of signal lines. No external line components are required, as termination is provided
internal to the MPL receiver. A maximum raw throughput of 307 Mbps (raw) is possible with this chipset. When
the protocol overhead is taken into account, a maximum data throughput of 245 Mbps is possible. The MPL
interface is designed for use with common 50Ω to 100Ω lines using standard materials and connectors. Lines
may be microstrip or stripline construction. Total length of the interconnect is expected to be less than 20cm.
LM2502
LM2502
MC
MD0
MD1
Master
Slave
GND
Figure 3. MPL Point-to-Point Bus
SERIAL BUS TIMING
Data valid is relative to both edges for a WRITE as shown in Figure 4. Data valid is specified as: Data Valid
before Clock, Data Valid after Clock, and Skew between data lines should be less than 500ps.
MC
MD0
MD1
Figure 4. Dual Link Timing (WRITE)
MC
MD0
MD1
Figure 5. Dual Link Timing (READ)
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Data is strobed out on the rising edge by the Slave for a READ as shown in Figure 5. The Master monitors for
the start bit transition (Low to High) and selects the best strobe to sample the incoming data on. This is done to
account for the round trip delay of the interconnect and application data rate.
SERIAL BUS PHASES
There are four bus phases on the MPL serial bus. These are determined by the state of the MC and MD lines.
The MPL bus phases are shown in Table 5.
Table 5. Link Phases (1)
Name
OFF (O)
IDLE (I)
Active (A)
LINK-UP (LU)
(1)
MC State
MDn State
0
0
Link is Off
Phase Description
Pre-Phase
Post-Phase
A, I or LU
LU
A
L
Data is Static (Low)
A or LU
A or O
Data Out
WRITE
A
X
Data Out (Write) — includes command,
Data Out Phases
LU, A, or I
A, I, or O
Data In READ
A
X
Data In (Read) — includes command,
TA', Data In, and TA” phases
LU, A, or I
A, I, or O
Master
H
-
Master initiated Link-Up
O
A, I, or O
Notes on MC/MD Line State:
0 = no current (off)
L = Logic Low—The higher level of current on the MC and MD lines
H = Logic High—The lower level of current on the MC and MD lines
X = Low or High
A = Active Clock
SERIAL BUS START UP TIMING
In the Serial Bus OFF phase, Master transmitters for MD0, MD1 and MC are turned off such that zero current
flows over the MPL lines. In addition, both the Master and the Slave are internally held in a low power state.
When the PD* input pins are de-asserted (driven High) the Master enables its PLL and waits for enough time to
pass for its PLL to lock. After the Master’s PLL is locked (t0 = 4,096 CLK Cycles), the Master will perform an
MPL start up sequence. The Slave will also power up and await the start up sequence from the Master.
The MPL start up sequence gives the Slave an opportunity to optimize the current sources in its transceiver to
maximize noise margins. The Master begins the sequence by driving the MC line logically Low for 11 CLK cycles
(t1). During this part of the sequence the Slave’s transceiver samples the MC current flow and adjusts itself to
interpret that amount of current as a logical Low. Next the Master drives the MC line logically HIGH for 11 CLK
cycles (t2). On the Low-to-High transition of the MC – point B – the Slave latches the current source
configuration. This optimized configuration is held as long as the MPL remains up. Next, the Master drives both
the MC and the MD lines to a logical Low for another 11 CLK cycles (t3), after which it begins to toggle the MC
line at a rate determined by its PLL Configuration pins. The Master will continue to toggle the MC line as long as
its PD* pin remains de-asserted (High). At this point the MPL bus may remain in IDLE phase, enter the ACTIVE
phase or return to the OFF phase. Active data will occur at the Slave output latency delays (Master + line +
Slave) after the data is applied to the Master input. Possible start points are shown by the “C” arrow in Figure 6.
After seven subsequent MC cycles the Slave will start toggling its CLK pin at a rate configured by its CLK Divisor
pins.
In the Figure 6 example, an IDLE bus phase is shown until point C, after which the bus is active and the High
start bit on MD initiates the transfer of information.
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Link
Off
Link-Up
Idle
active
Bus
Phase
PD*-in
(MST)
H
CLK
(MST)
H
L
L
t0
t2
t1
t3
H
MC-out (MST) /
MC-in (SLV)
L
O
A
B
H
PD*-in
(SLV)
L
t4
H
CLK-out
(SLV)
L
H
MD0 / MD1 -out
(MST) / MDn-in
(SLV)
L
C
O
Figure 6. MPL Power Up Timing
OFF PHASE
In the OFF phase, both Master and Slave MPL transmitters are turned off with zero current flowing on the MC
and MD lines. Figure 7 shows the transition of the MPL bus into the OFF phase. If an MPL line is driven to a
logical Low (high current) when the OFF phase is entered it may temporarily pass through as a logical High (low
current) before reaching the zero line current state.
Active
Power-Off
Bus Phase
H
MC
L
1
O
H
MD0/
MD1
L
O
Figure 7. MPL Power Down Timing
The link may be powered down by asserting both the Master’s and Slaves’s PD* input pins (Low). This causes
the devices to immediately put the link to the OFF Phase and internally enter a low power state. To avoid loss of
data the Master’s PD* input should only be asserted after the MPL bus has been in the IDLE state for at least 20
MC clock cycles. This gives the Slave enough time to complete any write operations received from the MPL bus.
CPU INTERFACE COMPATIBILITY
The CPU Interface mode provides compatibility between a CPU Interface and a small form factor (SFF) Display
or other fixed I/O port application. Two options are allowed:
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Table 6. Modes
Mode
Description
0
m68 Interface
(E, R/W*), 16-bit support
1
i80 Interface
(WR*, RD*), 16-bit support
It is not required that both the Master and the Slave to be configured in the same mode. For example the Master
may be configured as an 80xx (i80) interface while the Slave is configured for an 68xx (m68) interface.
Control information is carried over both MD lines. MD0 carries the D0–7 data bits while MD1 the D8–15 data bits.
See Figure 8.
WRITE TRANSACTION
The WRITE transaction consists of two MC edges of control information followed by 8 MC edges of write data.
Since WRITE transactions transfer information on both edges of MC it takes 5 MC cycles to complete a write
transaction. The MD0 line carries the Start bit (High), the A/D (Address/Data) bit and then the data payload of 8
bits (D0–7). The MD1 line carries the R/W* bit (Read/Write*), the CS1/2 bit and then the data payload of 8 bits
(D8–15). The data payload is sent least significant bit (LSB) first. The CS1/2 bit denotes which Chipset pin was
active. CS1/2 = HIGH designates that CS1* is active (Low). CS1/2 = LOW designates that CS2* is active (Low).
CS1* and CS2* LOW is not allowed.
MC
MD0
Start
H
A/D
D0
D1
D2
D3
D4
D5
D6
D7
Start
H
MD1
R/
W*
CS1
/2
D8
D9
D10
D11
D12
D13
D14
D15
R/
W*
Figure 8. Dual MD Link WRITE Transaction
READ TRANSACTION
The READ transaction is variable in length. It consists of four sections.
In the first section the Master sends a READ_Command to the slave. This command is sent in a single MC cycle
(2 edges) and uses a similar format to the 1st cycle of the WRITE transaction. The MD0 line carries the Start bit
(High) and the A/D (Address/Data) bit. The MD1 line carries the R/W* bit (High for reads) and the CS1/2 bit.
In the second section (TA’) the MD lines are turned around, such that the Master becomes the receiver and
Slave becomes the transmitter. The Slave must drive the MD lines low by the 14th clock edge. It may then idle
the line at the Logic Low state or drive the line High to indicate that read data transmission is starting. This
ensures that the MD lines are a stable LOW state and that the Low-to-High transition of the “Start” bit is seen by
the Master.
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READ
Command
TA'
READ Data
MC
MD0
A/D
R/
W*
CS1/
2
2
3
|
1
Start
H
>=17
(27)
15
L
L
Bus Undetermined
DO
LSB
Start
H
D8
LSB
|
Start
H
MD1
L
L
Bus Undetermined
|
MDm
MDs
Figure 9. READ_Command and TA’
The third section consists of the transfer of the read data from the Slave to the Master. Note that the READ_Data
operates on single-edge strobing (Rising Edge ONLY). Therefore the back channel data signaling rate is ½ of the
forward channel (Master-to-Slave direction). When the Slave is ready to transmit data back to the Master it drives
the MD lines High to indicate start of read data, followed by 8 MC cycles of the actual read data payload. As in
the WRITE command MD0 carries D0–7 and MD1 carries D8–5. The Master monitors for the start bit transition
(Low to High) and selects the best strobe to sample the incoming data on. This is done to account for the round
trip delay of the interconnect and application data rate.
The Master detects the location of the START bit on MD0 and selects the best strobe for data capture. Skew
between the data lines is constrained tighter in the Master-to-Slave direction (Write) than in the Read direction
due to the data rate difference. The Master uses its internal clock (multiple phases) to latch the data.
The fourth and final section (TA”) occurs after the read data has been transferred from the Slave to the Master.
In the fourth section the MD lines are again turned around, such that the Master becomes the transmitter and the
Slave becomes the receiver. The Slave drives the MD lines Low for 1 bit width and then turns off. The MD lines
are off momentarily to avoid driver contention. The Master then drives the MD line Low for 1 bit time and then
idles the bus until the next transaction is sent.
During a READ transaction (Double Read access on the Master), other MPL transactions are not allowed until
the current READ dual cycle is completed.
READ Data
TA"
Idle
MC
|
D6
D7
MSB
L
Bus
Undetermined
MD1
D14
D15
MSB
L
Bus
Undetermined
L
|
MD0
L
|
MDs
5 MC
Cycles
MDm
Figure 10. READ_Data and TA”
To account for the latency through the MPL link, a dual READ operation is required by the host. The first read
returns invalid data (all Low). Once data has returned to the Master LM2502, the INTR signal is asserted to
inform the host to initiate a second read operation. When the Master LM2502 sees the Read signal/CS*
combination, it will de-assert the INTR signal and Valid data is presented.
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Display
Set Time
LM2502 Data
Disable
LM2502 Data
Enable
Display
Hold Time
R/W*
DATAn
CS*
WRITE
READ
Figure 11. Slave WRITE and Slave READ m68 mode Operation
Figure 11 illustrates a m68 mode WRITE followed by a READ operation (Slave output to Display). At the end of
the WRITE operation the SLAVE outputs are turned off. The SLAVE latches in the READ data on the rising edge
of the CS* signal as shown. The Display should disable its outputs prior to the next operation to avoid any bus
contention.
MASTER INPUT
A/D
CS1*
CS2*
E (High)
R/W* (Low))
DATA[15:0]
MPL
MC
H
A/D D
D
D
D
D
D
D
D
H A/D D
D
D
D
D
D
D
D
MD0
R/
W
CS
D
D
D
D
D
D
D
R/
W CS
D
D
D
D
D
D
D
MD1
D
D
SLAVE OUTPUT
MC
E (High)
Holds last state
R/W* (Low)
CS1*
CS2*
Holds last state
A/D
Holds last state
Data
[15:0]
Figure 12. Back-to-Back WRITE Operations—m68 Mode
Figure 12 illustrates a m68 mode WRITE operation to the main display (CS1*) followed by a WRITE operation to
the sub display (CS2*). This example shows the maximum operation rate with no idle time between the serial
transactions.
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CPU MODE—WRITE—m68
AD
MOT
16-bit
WRITE
E=HIGH
Latched
(Data
on CSn* L-to-H
Edge)
MASTER IN
R/W*
E
D[n]
CS1* or CS2*
MASTER
INPUT
T2
T1
T3
AD
MOT
16-bit
WRITE
(Data
Latched
on E H-to-L
Edge)
MASTER IN
R/W*
E
D[n]
CS1* or CS2*
T4
T1
T2
MPL
T5
T3
MC
MD0
H A D0
D7
W C D8
D15
MD1
MPL Phases
1. IDLE
2. ACTIVE (WRITE)
3. IDLE
AD
R/W*
SLAVE
OUTPUT
E
D[n]
T7
T6
CS1* or CS2*
T9
T8
Figure 13. WRITE—MOT 6800 µP Interface
Table 7. WRITE—MOT 6800 µP Interface Parameters
No.
(1)
16
Parameter
Min
T1
MasterIN
Data Setup Time before ChipSelect* Low-High (or
E High-Low)
5
ns
T2
MasterIN
Data Hold after ChipSelect*
Low-High (or E High-Low)
5
ns
T3
MasterIN
ChipSelect* Recovery Time,
T4
Master
Master Latency
5
MC Cycles
T5
Slave
Slave Latency
9
MC Cycles
T6
SlaveOUT
Data Valid before ChipSelect* High-Low
1
MC Cycles
T7
SlaveOUT
ChipSelect* Low Pulse Width
3
MC Cycles
T8
SlaveOUT
Data Valid before ChipSelect* Low-High
4
MC Cycles
(1)
Typ
6
Max
Units
MC Cycles
This parameter is specified by design based on simulation or bench characterization.
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Table 7. WRITE—MOT 6800 µP Interface Parameters (continued)
No.
Parameter
T9
SlaveOUT
Min
Typ
Data Valid after ChipSelect* Low-High
Max
Units
1
MC Cycles
A/D
RW*
R/W*
T15
E
T1
CS1* or
CS2*
CS1* or
CS2*
"D[n]"
LOW
E
T12
T13
T11
"D[n]"
VALID
T14 "INTR"
T10
"INTR"
T16
OR
A/D
A/D
RW*
T2
R/W*
T13
T15
E
E
CS1* or
CS2*
T1
T12
T11
CS1* or
CS2*
"D[n]"
LOW
T3
"D[n]"
VALID
T14 "INTR"
T10
"INTR"
5 MC cyc.
T9
T4
MASTER Parallel Input - w/E
T2
A/D
MASTER Parallel Input - w/E High
CPU MODE—READ—m68
MC
MPL
MD0
HA L
L H D0
D7 L
U
L
RC L
L H D8
D15 L
U
L
MD1
MOT
16-bit
READ
(Data Strobed
on CS*
L-to-H
(E=High)
SLAVE
OUT/
Din
Bus Idle
"A/D"
NOTE: "BOLD" denotes LM2502 output signal
"R/W*"
"E"
T5
T6
"CS1*
or CS2*"
D[n]
T7
T8
Figure 14. READ—6800 µP Interface
Table 8. READ—6800 µP Interface Parameters
No.
Parameter
Min
Typ
20
Max
Units
T1
MasterIN
Set Up Time (A/D, R/W*) and Data On Time
T2
MasterIN
Hold Time (A/D, R/W*) and Data Off Time
15
ns
ns
T3
Master
Master Latency
5
MC Cycles
T4
Slave
Slave Latency
6
MC Cycles
T5
Slave
ChipSelect* Delay
1
MC Cycles
T6
Slave
ChipSelect Low Pulse Width
6
MC Cycles
T7
Slave
Data Set Up Time
5
T8
Slave
Data Hold Time
15
T9
Slave
Slave Read Latency
4
MC Cycles
T10
Master
MST Read Latency and INTR Delay
12
MC Cycles
ns
ns
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Table 8. READ—6800 µP Interface Parameters (continued)
No.
(1)
Parameter
T11
Master
T12
MasterOUT
Data Valid after Strobe
T13
MasterOUT
CS* or E active pulse width
T14
MasterOUT
INTR De-assert
T15
MasterOUT
Recovery Time
T16
MasterOUT
INTR Response,
Min
Typ
Data Delay
Max
ns
15
ns
5
MC Cycles
20
ns
5
(1)
Units
18.6
ns
0
MC Cycles
This parameter is specified by design based on simulation or bench characterization.
For the MOT CPU 68xx mode, the Master accepts data on the CS* Low-to-High transition or the E High-to-Low
transition, which ever come first. The Slave output only uses the CS* pin for data strobe/latch, as the E signal is
held constantly High.
CPU MODE—WRITE—i80
MASTER
INPUT
AD
Intel Mode
16-bit
WRITE
(Data
Latched
on WR* or CSn*
Low-to-High,
which ever occurs
first)
WR*
RD*
D[n]
CS1* or CS2*
T4
T1
T2
MPL
T5
T3
MC
MD0
H A D0
D7
W C D8
D15
MD1
MPL Phases
1. IDLE
2. ACTIVE (WRITE)
3. IDLE
AD
T7
T6
SLAVE
OUTPUT
WR*
RD*
T8
T9
D[n]
CS1* or CS2*
Figure 15. WRITE—80xx µP Interface
Table 9. WRITE—80xx µP Interface Parameters
No.
(1)
18
Parameter
Min
Typ
Max
Units
T1
MasterIN
Data Setup before Write* High
5
T2
MasterIN
Data Hold after Write* High
5
ns
T3
MasterIN
Write* Recovery Time,
6
MC Cycles
T4
Master
Master Latency
5
MC Cycles
T5
Slave
Slave Latency
9
MC Cycles
T6
SlaveOUT
Data Valid before Write* High-to-Low
1
MC Cycles
(1)
ns
This parameter is specified by design based on simulation or bench characterization.
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Table 9. WRITE—80xx µP Interface Parameters (continued)
No.
Parameter
Min
Typ
Max
Units
T7
SlaveOUT
WR* Pulse Width Low
3
MC Cycles
T8
SlaveOUT
Data Valid before Write* Low-to-High
4
MC Cycles
T9
SlaveOUT
Data Valid after Write* Low-to-High
1
MC Cycles
CPU MODE—READ—i80
A/D
A/D
WR*
T2
WR*
RD*
RD*
T15
T12
T11
CS1* or
CS2*
CS1* or
CS2*
T1
"D[n]"
LOW
MASTER Parallel Input
T13
"D[n]"
VALID
T16
T3
T14 "INTR"
"INTR"
T10
T9
T4
5 MC cyc.
MC
MPL
MD0
L H D0
H AL
D7 L
U
L
U
L
MD1
L H D8
R CL
Intel
16-bit
READ
(Data
Strobed
on RD*
L-to-H
SLAVE
OUT/
Din
D15 L
Bus Idle
"A/D"
NOTE: "BOLD" denotes LM2502 output signal
"RD*"
T5
"WR*"
T6
"CS1*
or CS2*"
D[n]
T7 T8
Figure 16. READ—INTEL µP Interface
Table 10. READ—Intel µP Interface Parameters
No.
Parameter
Min
Typ
20
Max
Units
T1
MasterIN
Set Up Time (A/D, RD*) and Data On Time
T2
MasterIN
Hold Time (A/D, RD*) and Data Off Time
15
ns
T3
Master
Master Latency
5
MC Cycles
T4
Slave
Slave Latency
6
MC Cycles
T5
Slave
Read* Delay
1
MC Cycles
T6
Slave
Read Low Pulse Width
6
MC Cycles
T7
Slave
Data Set Up Time
5
T8
Slave
Data Hold Time
15
T9
Slave
Slave Read Latency
4
MC Cycles
T10
Master
MST Read Latency and INTR Delay
12
MC Cycles
T11
Master
Data Delay
18.6
ns
T12
MasterOUT
Data Valid after Strobe
15
ns
T13
MasterOUT
RD* active pulse width
20
ns
ns
ns
ns
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Table 10. READ—Intel µP Interface Parameters (continued)
No.
(1)
Parameter
T14
MasterOUT
INTR De-assert
T15
MasterOUT
Recovery Time
T16
MasterOUT
INTR Response,
Min
Typ
Max
5
5
(1)
Units
MC Cycles
ns
0
MC Cycles
This parameter is specified by design based on simulation or bench characterization.
LM2502 FEATURES AND OPERATION
POWER SUPPLIES
The VDDcore and VDDA (MPL and PLL) must be connected to the same potential between 2.9V and 3.3V. VDDIO
powers the logic interface and may be powered between 1.7 and 3.3V to be compatible with a wide range of host
and target devices. VDDIO should not be powered up without VDDcore/VDDA applied as VDDcore biases the IO ring.
During power up, all rails should power up at the same time, or VDDcore/VDDA should lead.
POWER DOWN/OFF
The Master and the Slave provide a PD* pin to save power when the link is not needed. A Low on this pin will
power down the entire device and turn off the line current to MD0, MD1, and MC.
During power up, the PD* inputs should be held LOW and released once power is stable and within specification.
The Slave PD* may be released first or at the same time as the Master’s PD* pin. CLK (Master) should be
applied prior to releasing PD*. If the Powerdown state is not required, the PD* pins maybe connected to VDDIO,
however VDDIO should power up smooth through the logic threshold region.
In Powerdown (PD* = GND) the following outputs are driven to:
Master:
INTR = L
Slave depends on mode configuration - see Table 11.
Table 11. SLV Output in Powerdown
Pin
SLV
i80
SLV
m68
AD
H
H
Data[n]
L
L
CLK
L
L
CS1*
H
H
CS2*
L
H
MF0
H
H
MF1
H
H
BYPASS RECOMMENDATIONS
Bypass capacitors should be placed near the power supply pins of the device. Use high frequency ceramic
(surface mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF Tantalum capacitor is recommended near the
Master (SER) VDDA pin for PLL bypass. Connect bypass capacitors with wide traces and use dual or larger via to
reduce resistance and inductance of the feeds. Utilizing a thin spacing between power and ground planes will
provide good high frequency bypass above the frequency range where most typical surface mount capacitors are
less effective. To gain the maximum benefit from this, low inductance feed points are important. Also, adjacent
signal layers can be filled to create additional capacitance. Minimize loops in the ground returns also for
improved signal fidelity and lowest emissions.
UN-USED/OPEN PINS
Unused inputs must be tied to the proper input level—do not float them. Unused outputs should be left open to
minimize power dissipation.
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PHASE-LOCKED LOOP
When the LM2502 is configured as a Master, a PLL is enabled to generate the serial link clock. The Phaselocked loop system generates the serial data clock at several multiples of the input clock. The PLL operates with
an input clock between 3 and 26 MHz. See Table 12 below, Multiplier/Divisor times CLK rate must also be less
than 76.8 MHz. The 76.8 MHz limitation is based on the semiconductor process used on this implementation—it
is not an MPL limitation.
Line rate should also be selected such that it is faster than the input load rate when bursting data across the link.
Otherwise 8/10 X Line rate must be greater than the input load rate to the Master. At the maximum raw data rate
of 307 Mbps, the maximum information rate is 245 Mbps. Thus the parallel load rate at the Master input must not
exceed 15.4 Mega Transfers per second sustained (of 16 data bits). The Master can accommodate up to four
words at a higher rate due to internal FIFOs.
Configuration pins (PLL_CON[2:0], and M/S*) are used to determine the mode of which the part is operating in.
In the Slave configuration the PLL block is disabled. The Slave PLL_CON pins are required to set up the proper
divisor for the CLK pin. Slave PLL_CON[2:0] pins do not need to be set the same as the Master, this allows for
clock multiplication / division to be supported for the output clock reference signal.
RESET
On both the Master and the Slave, the PD* pin resets the logic. The PD* pins should be held low until the power
supply has ramped up and is stable and within specifications. The Slave PD* pin should be driven High first or at
the same time as the Master. This will ensure that the Slave sees the start up sequence from the Master.
MASTER/SLAVE SELECTION
The M/S* pin is used to configure the device as either a Master or Slave device. When the M/S* pin is a Logic
High, the Master configuration is selected. The Driver block is enabled for the MC line, and the MD lines. When
the M/S* pin is a Logic Low, the Slave configuration is selected. The Receiver block is enabled for the MC line,
and the MD lines.
Table 12. PLL_CON Settings
Multiplier
(Master)
MC out
Divisor
(Slave)
CLKout
Minimum
CLK Input
Maximum
CLK Input
(MC ≦ 76.8 MHz)
PLLCON2
PLLCON1
PLLCON0
0
0
0
CLK X 2
MC / 2
13 MHz
26 MHz
0
0
1
CLK X 4
MC / 4
6 MHz
19.2 MHz
0
1
0
CLK X 6
MC / 6
3 MHz
12.8 MHz
0
1
1
CLK X 7
MC / 7
3 MHz
10.97 MHz
1
0
0
CLK X 8
MC / 8
3 MHz
9.60 MHz
1
0
1
CLK X 9
MC / 9
3 MHz
8.53 MHz
1
1
0
CLK X 10
MC / 10
3 MHz
7.68 MHz
1
1
1
(Reserved)
APPLICATION INFORMATION
SYSTEM CONSIDERATIONS
When employing the MPL SERDES chipset in place of a parallel bus, a few system considerations must be
taken into account. Before sending commands (ie initialization commands) to the display, the SERDES must be
ready to transmit data across the link. The MPL link must be powered up, and the PLL must be locked. Also a
review of the Slave output timing should be completed to insure that the timing parameters provided by the Slave
output meet the requirements of the LCD driver input. Specifically, pulse width on CSn*, RD* / WR*, data valid
time, and bus cycle rate should be reviewed and checked for inter-operability. Additional details are provided
next:
The MPL link should be started up as follows: The chipset should be powered up first, VDDIO should not be
powered up first, it may be at the same time as VDD/VDDA or lag. During power up, the PD* inputs should be held
LOW and released once power is stable and within specification. The Slave PD* may be released first or at the
same time as the Master. CLK should be applied prior to releasing PD*.
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Before data can be sent across the MPL serial link, the link must be ready for transmission. The CLK needs to
be applied to the device, and the PLL locked. This is controlled by a keep-off counter set for 4096 cycles. After
the PLL has lock and the counter expired, an additional 40 clock cycles are required for the calibration of the
MPL link. After this, data may now be written to the device.
It takes 5MC Cycles to send a 16-bit CPU Write including the serial overhead. The MC cycle time is calculated
based on the PLL_CON[2:0] setting and also the input clock frequency. For example, a 19.2MHz input CLK and
a 4X PLLCON setting yields a MC frequency of 76.8MHz. Thus it takes 65.1ns to send the word in serial form.
To allow some idle time between transmissions (this will force a bit sync per word if the gap is long enough in
between), the load rate on the Master input should not be faster than 6MC cycles, or every 78ns in our example
to support a data pipe line. This is sometimes referred to as the bus cycle time (time between commands).
The Slave output times is also a function of MC cycles. Note that in i80 mode, the width of the WR* pulse (in
m68 mode the width of the CS*) pulse low is three MC cycles regardless of the pulse width applied to the
Master input. System designers need to check compatibility with the display driver to ensure this pulse width
meets its requirement. If it is too fast, select a lower PLLCON setting or apply a slower input clock.
The CLK input must be free running and not gapped. If the clock is stopped a RESET (PD* = Low) cycle should
be done and the link brought up again.
MPL SWAP FEATURE
The LM2502 provides a swap function of MPL MD lines depending upon the state of the M/S* pin. This facilitates
a straight through MPL interface design eliminating the needs for via and crossovers as shown on Figure 17. See
also Connection Diagram and Table 1.
Note that three pins are defined differently on the MASTER and the SLAVE configured device. Schematic
Capture device diagrams should take this into account for proper connection. The following pin
descriptions apply for the three pins given in Ball Number : Master (Slave) function
NFBGA Package
• A5 : INTR (CLKDIS*)
• A6 : MD1 (MD0)
• B7 : MD0 (MD1)
WQFN Package
• 34 : INTR (CLKDIS*)
• 32 : MD1 (MD0)
• 29 : MD0 (MD1)
FLEX CIRCUIT RECOMMENDATIONS
The three MPL lines should generally run together to minimize any trace length differences (skew). For
impedance control and also noise isolation (crosstalk), guard ground traces are recommended in between the
signals. Commonly a Ground-Signal-Ground (GSGSGSG) layout is used. Locate fast edge rate and large swing
signals further away to also minimize any coupling (unwanted crosstalk). In a stacked flex interconnect, crosstalk
also needs to be taken into account in the above and below layers (vertical direction). To minimize any coupling
locate MPL traces next to a ground layer. Power rails also tend to generate less noise than LVCMOS so they are
also good candidates for use as isolation and separation.
The interconnect from the Master to the Slave typically acts like a transmission line. Thus impedance control and
ground returns are an important part of system design. Impedance should be in the 50 to 100 Ohm nominal
range for the LM2502. Testing has been done with cables ranging from 40 to 110 Ohms without error (BER
Testing). To obtain the impedance, adjacent grounds are typically required (1 layer flex), or a ground shield /
layer. Total interconnect length is intended to be in the 20cm range, however 30cm is possible at lower data
rates. Skew should be less than 500ps to maximize timing margins.
GROUNDING
While the LM2502 employs three separate types of ground pins, these are intended to be connected together to
a common ground plane. The separate ground pins help to isolate switching currents from different sections of
the integrated circuit (IC). Also required is a nearby signal return (ground) for the MPL signals. These should be
provided next to the MPL signals, as that will create the smallest current loop area. The grounds are also useful
for noise isolation and impedance control.
22
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PCB RECOMMENDATIONS
General guidelines for the PCB design:
• Floor plan, locate MPL Master near the connector to limit chance of cross talk to high speed serial signals.
• Route serial traces together, minimize the number of layer changes to reduce loading.
• Use ground lines are guards to minimize any noise coupling (specifies distance).
• Avoid parallel runs with fast edge, large LVCMOS swings.
• Also use a GSGSG pinout in connectors (Board to Board or ZIF).
• Slave device - follow similar guidelines.
• Bypass the device with MLC surface mount devices and thinly separated power and ground planes with low
inductance feeds.
• High current returns should have a separate path with a width proportional to the amount of current carried to
minimize any resulting IR effects.
GND
A
7
B
6
C
5
MD1 (Master A6, Slave B7)
MASTER
(Top View)
D
Slave
(Top View)
4
MC (Master A7, Slave A7)
E
3
MD0 (Master B7, Slave A6)
F
2
G
1
1
2
3
4
5
6
7
A
B
C
D
E
F
G
Figure 17. MPL Interface Layout - NFBGA Example
Ball A1
A
B
C
D
E
BALL
Description
A4
VDDA
B4
VSSA
D1
VDDIO
D2
VSSIO
D6
VSScore
D7
VDDcore
F4
VSSIO
G4
VDDIO
F
G
1
2
3
4
5
6
7
Figure 18. LM2502 NFBGA Package PWR (VDD) and GND (VSS) Balls
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DISPLAY APPLICATION
The LM2502 chipset is intended for Interface between a host (processor) and a Display. It supports a 16 or 8-bit
CPU style interface and can be configured for i80 or m68 modes.
The Master side connection is shown in Figure 19. Input Clock frequency and the selection of the PLL_CON
setting are determined by system parameters. These include the required display bandwidth, the Master load
rate and the Display Driver input timing requirements. See the System Considerations section for more details.
The Display side parallel bus may be connected to one or two displays. Each display has its own chipselect
signal. If only one display is required, the unused CS signal should be tied HIGH (VDDIO) on the Master, and the
unused output left open on the Slave. The Slave provides an optional clock output. If this is desired the CLKDIS*
pin needs to be also tied HIGH. A different PLL_CON setting can be used to alter the frequency if desired. As the
Divisor setting in the Slave is not used for data recovery. For the dual display application, the multidrop bus
should be laid out to minimize any resulting stub lengths on the Data, A/D, and control signals.
If required, the Slave output clock can be enabled to provide a output frequency reference. The frequency can be
adjusted by setting different PLL_CON (divisor) settings (on the Slave). This can then be used as a frequency
reference signal to the display module or other subsystem (ie camera module). If the CLK output is not needed,
tie the Slave CLKDIS* pin Low to disable it. The Clock is available when ever the MPL link is enabled.
BBP
or
APP
Processor
Memory Port
(Display)
LM2502 MPL Master
INTR
R/W*(WR*)
E (RD*)
A/D
D[15:0]
CS2*
CS1*
LM2502 MPL Slave
MC
MD0
CLK
CLK (optional)
R/W*(WR*)
R/W*
E (RD*)
A/D
D[15:0]
CS2*
CS1*
PD*
Mode
PD*
M/S* = H
PLL_CON[2:0],
Mode are application
dependent
M/S*
PLL_Con[2:0]
Mode
MD1
GND
CLKDIS*
PLL_Con
[2:0]
Primary
Display
(A)
Sub
Display
(B)
M/S*
GND
M/S* = L
PLL_CON[2:0], Mode, CLKDIS* are application
dependent, PD* = GPIO
Figure 19. Display Interface Application
RGB565 APPLICATION
The LM2502 chipset may also be configured for a RGB565 application. This is also known as a "buffer-less" or
"dumb" display application. In this configuration 16 color bits (R[4:0], G[5:0], B[4:0]), Pixel Clock (PCLK) and two
control bits (VS and HS) are supported. An external invertor is also required.
To configure for the RGB565 mode, the i80 mode must be selected. The Pixel clock should be connected to both
the CLK input and the WR* pins on the Master. The PLL_CON pins should be configured for a 6X mode, as it
takes 5 MC cycles to transfer the RGB data, and the 6X setting will provide a 50% output PCLK from the Slave
device. The 50% duty cycle PCLK is created by the WR* signal which pulses low for 3 MC cycles and is high for
2 MC cycles and an idle MC cycle. See Figure 20 for details. Support is provided for PCLKs in the 3 to 12.8 MHz
range. PLLCON setting of X8 is also possible, however, the Slave output PCLK (WR*) will have some duty cycle
distortion (37.5%) and the CLK range is further restricted.
Slower PCLK rates maybe supported if a higher frequency multiple of the PCLK is available. For example, if a
2MHz PCLK is required, then a 6MHz CLK (freq locked, not phase) may be applied to the MST CLK input and
the 2MHz PCLK to the MST WR* signal input. The PLLCON setting should be selected as 2X (PLLCON[2:0] =
000’b). Once again 5 MC cycles are required to transfer the pixel data, and the WR* (PCLK) will be 50% duty
cycle. The applied CLK and PLLCON should be selected such that is creates a 6X multiple on MC to ensure a
50% duty cycle.
24
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BBP
or
APP
Processor
Display Port
LM2502 MPL Master
RGB[565]
MC
WR*
A/D
VS
LM2502 MPL Slave
WR*
A/D
D[15:0]
CS1*
PD*
CLK
RD*
CS2*
D[15:0]
MD0
CS2*
CS1*
CLK
PD*
INTR
HS
PCLK
MD1
PLL_Con2
PLL_Con1
PLL_Con0
M/S*
RD*
Mode
PCLK
VS
RGB[565]
HS
PLL_Con2
PLL_Con1
PLL_Con0
M/S*
Display
RGB565 Port
GPIO
Mode
GND
Figure 20. RGB565 Application
QVGA Example - For a QVGA display (320 by 240), with 16 bits of color depth and 60 frames per second, a net
bandwidth requirement is 73.728 Mbps. Maximum transfer rate for the LM2502 chipset is 245 Mbps (307 Mbps
raw - includes overhead), thus there is adequate bandwidth for this application and even larger resolution
displays.
Figure 21 shows the typical timing of the RGB application. The 6X PLL setting (PLLCON[2:0] = 010’b) is
selected. The PCLK is applied to both the WR* and CLK inputs on the Master. The rising edge on the WR*
(PCLK) signal samples the data by the Master for serialization. The CLK input can be the PCLK (if timing
requirements are met) or a synchronous clock to the PCLK signal. The HS connects to the CS1* signal and the
HS* (inverted HS) is connected to the CS2*. With this configuration there will always be a valid CS* LOW on the
Master input. The RGB information is then serialized and passed to the Slave via the MPL bus. It takes 5 MC
cycles to complete the transfer and with the 6X PLL setting, there will be two idle bits on the MD (1 MC cycle)
lines before the next transfer. Recovery of the RGB interface (RGB565, HS, VS and PCLK) is provided at the
Slave output. The PCLK is slightly shifted later in time (1 MC cycle) but adequate timing margin (increased set,
shorted hold) is still provided.
WR* -- PCLK
AD -- VS
MASTER
INPUT
RGB Application
(i80)
D[n] -- RGB565
CS1* -- HS
CS2* (not CS1*) -- HS*
MPL
MPL Transaction
MC
MD0
H A D0
D7
W C D8
D15
MD1
WR* -- PCLK
SLAVE
OUTPUT
RGB Application
(i80)
AD -- VS
D[n] -- RGB565
CS1* -- HS
Figure 21. RGB565 Application Timing
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM2502SQ/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WQFN
RSB
40
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-30 to 85
L2502SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM2502SQ/NOPB
Package Package Pins
Type Drawing
WQFN
RSB
40
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
178.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.3
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2502SQ/NOPB
WQFN
RSB
40
1000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RSB0040A
WQFN - 0.8 mm max height
SCALE 2.700
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
0.5
0.3
PIN 1 INDEX AREA
0.3
0.2
5.1
4.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
DIM A
OPT 1 OPT 1
(0.1)
(0.2)
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
2X 3.6
11
(A) TYP
EXPOSED
THERMAL PAD
20
36X 0.4
10
21
2X
3.6
41
SYMM
3.6 0.1
SEE TERMINAL
DETAIL
1
30
40X
PIN 1 ID
(OPTIONAL)
40
31
SYMM
0.5
40X
0.3
0.25
0.15
0.1
0.05
C A B
(0.2) TYP
4215000/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RSB0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.6)
SYMM
31
40
40X (0.6)
40X (0.2)
1
30
36X (0.4)
4X
(1.55)
41
SYMM
(1.23)
(4.8)
( 0.2) TYP
VIA
10
21
(R0.05)
TYP
11
(1.23) TYP
20
4X (1.55)
(4.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215000/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSB0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.23) TYP
9X ( 1.03)
40
31
40X (0.6)
1
41
30
40X (0.2)
36X (0.4)
(1.23)
TYP
SYMM
(4.8)
(R0.05) TYP
10
21
METAL
TYP
20
11
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 41
73.7% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4215000/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
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