Texas Instruments | DS92001 3.3V B/LVDS-BLVDS Buffer (Rev. F) | Datasheet | Texas Instruments DS92001 3.3V B/LVDS-BLVDS Buffer (Rev. F) Datasheet

Texas Instruments DS92001 3.3V B/LVDS-BLVDS Buffer (Rev. F) Datasheet
DS92001
www.ti.com
SNLS147F – JUNE 2002 – REVISED APRIL 2013
DS92001 3.3V B/LVDS-BLVDS Buffer
Check for Samples: DS92001
FEATURES
DESCRIPTION
•
•
The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS
input signal and provides a BLVDS output signal. In
many large systems, signals are distributed across
backplanes. One of the limiting factors for system
speed is the "stub length" or the distance between
the transmission line and the unterminated receivers
on individual cards. Although it is generally
recognized that this distance should be as short as
possible to maximize system performance, real-world
packaging concerns often make it difficult to make the
stubs as short as the designer would like.
1
2
•
•
•
•
•
•
•
•
Single +3.3 V Supply
Receiver Inputs Accept LVDS/CML/LVPECL
Signals
TRI-STATE Outputs
Receiver Input Threshold < ±100 mV
Fast Propagation Delay of 1.4 ns (typ)
Low Jitter 400 Mbps Fully Differential Data
Path
Compatible with BLVDS 10-bit SerDes (40MHz)
Compatible with ANSI/TIA/EIA-644-A LVDS
Standard
Available in SOIC and Space Saving WSON
Package
Industrial Temperature Range
The DS92001 has edge transitions optimized for
multidrop backplanes where the switching frequency
is in the 200 MHz range or less. The output edge rate
is critical in some systems where long stubs may be
present, and utilizing a slow transition allows for
longer stub lengths.
The DS92001, available in the WSON package, will
allow the receiver inputs to be placed very close to
the main transmission line, thus improving system
performance.
A wide input dynamic range allows the DS92001 to
receive differential signals from LVPECL, CML as
well as LVDS sources. This will allow the device to
also fill the role of an LVPECL-BLVDS or CMLBLVDS translator.
Connection and Block Diagrams
GND
1
8
EN
IN-
2
7
OUT-
IN+
3
6
OUT+
N/C
4
5
VCC
Figure 1. SOIC Package Number D0008A
Top View
GND
1
8
EN
IN-
2
DAP
7
OUT-
IN+
3
GND
6
OUT+
N/C
4
5
VCC
Figure 2. WSON Package Number NGK0008A
Top View
IN-
OUT-
IN+
OUT+
EN
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
DS92001
SNLS147F – JUNE 2002 – REVISED APRIL 2013
www.ti.com
Table 1. Functional Operation
BLVDS Inputs
BLVDS Outputs
[IN+] − [IN−]
OUT+
OUT−
VID ≥ 0.1V
H
L
VID ≤ −0.1V
L
H
−0.1V ≤ VID ≤ 0.1V
Undefined
Undefined
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage (VCC)
−0.3V to (VCC + 0.3V)
LVCMOS/LVTTL Input Voltage (EN)
B/LVDS Receiver Input Voltage (IN+, IN−)
−0.3V to +4V
BLVDS Driver Output Voltage (OUT+, OUT−)
−0.3V to +4V
BLVDS Output Short Circuit Current
Continuous
Junction Temperature
+150°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at D Package
25°C
Derate D Package
726 mW
5.8 mW/°C above +25°C
NGK Package
ESD Ratings
(1)
(2)
2.44 W
Derate NGK Package
19.49 mW/°C above +25°C
(HBM, 1.5kΩ, 100pF)
≥2.5kV
(EIAJ, 0Ω, 200pF)
≥250V
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Min
Typ
Max
Supply Voltage (VCC)
3.0
3.3
3.6
V
Receiver Differential Input Voltage (VID) with VCM=1.2V
0.1
2.4
|V|
Operating Free Air Temperature
−40
+25
+85
°C
2
20
ns
B/LVDS Input Rise/Fall 20% to 80%
2
Submit Documentation Feedback
Units
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
DS92001
www.ti.com
SNLS147F – JUNE 2002 – REVISED APRIL 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
LVCMOS/LVTTL DC SPECIFICATIONS (EN)
VIH
High Level Input Voltage
2.0
VCC
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = VCC or 2.0V
+20
μA
IIL
Low Level Input Current
VIN = GND or 0.8V
VCL
Input Clamp Voltage
ICL = −18 mA
+7
−10
±1
+10
μA
−0.6
−1.5
V
BLVDS OUTPUT DC SPECIFICATIONS (OUT)
|VOD|
ΔVOD
Differential Output Voltage (1)
RL = 27Ω
250
350
500
mV
RL = 50Ω
350
450
600
mV
20
mV
1.25
1.375
V
2
20
mV
Change in Magnitude of VOD
for Complimentary Output
States
RL = 27Ω or 50Ω See Figure 3 and Figure 4
VOS
Offset Voltage
RL = 27Ω or RL = 50Ω
ΔVOS
Change in Magnitude of VOS
for Complimentary Output
States
1.1
See Figure 3
IOZ
Output TRI-STATE Current
EN = 0V, VOUT = VCC or GND
−20
±5
+20
μA
IOFF
Power-Off Leakage Current
VCC = 0V or Open Circuit, VOUT = 3.6V
−20
±5
+20
μA
IOS1
Output Short Circuit
Current (3)
EN = VCC, VCM = 1.2V,VID = 200mV, VOUT+ = 0V, or
VID = −200mV, VCM = 1.2V, VOUT− = 0V
−30
−60
mA
VID = −200mV, VCM = 1.2V, VOUT+ = VCC , or
VID = 200mV, VCM =1.2V, VOUT− = VCC
53
80
mA
EN = VCC, VID = |200mV|, VCM. = 1.2V, VOD = 0V
(connect true and complement outputs through a
current meter)
|30|
|42|
mA
−30
−5
mV
IOSD
Differential Output Short
Circuit Current (3)
B/LVDS RECEIVER DC SPECIFICATIONS (IN)
VTH
Differential Input High
Threshold (4)
VTL
Differential Input Low
Threshold (4)
VCMR
Common Mode Voltage
Range (4)
IIN
Input Current
ΔIIN
Change in Magnitude of IIN
VCM = +0.05V, +1.2V or +3.25V
−70
−30
|VID|/2
mV
VCC
−|VID|/2
V
|1.5|
|20|
μA
VIN = 0V
|1.5|
|20|
μA
VIN = VCC
1
6
μA
VIN = 0V
1
6
μA
VIN = VCC
VCC = 3.6V or 0V
SUPPLY CURRENT
ICCD
Total Dynamic Supply
Current (includes load
current)
EN = VCC, RL = 27Ω or 50Ω, CL = 15 pF,
Freq. = 200MHz 50% duty cycle,
VID = 200mV, VCM = 1.2V
50
65
mA
ICCZ
TRI-STATE Supply Current
EN = 0V,Freq. = 200MHz 50% duty cycle,
VID = 200mV, VCM= 1.2V
36
46
mA
(1)
(2)
(3)
(4)
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VID, VOD, VTH, VTL, and ΔVOD. VOD has a value and direction. Positive direction means OUT+ is a more positive voltage than
OUT−.
All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
The parameters are specified by design. The limits are based on statistical analysis of the device performance over the PVT (process,
voltage and temperature) range.
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
3
DS92001
SNLS147F – JUNE 2002 – REVISED APRIL 2013
www.ti.com
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1.0
1.4
2.0
ns
1.0
1.4
2.0
ns
LVDS OUTPUT AC SPECIFICATIONS (OUT)
tPHLD
Differential Propagation Delay High
to Low (2)
tPLHD
Differential Propagation Delay Low
to High (2)
tSKD1
Pulse Skew |tPLHD − tPHLD|
(measure of duty cycle) (3) (4)
0
20
200
ps
tSKD3
Part-to-Part Skew (3) (5)
0
200
300
ps
tSKD4
Part-to-Part Skew
(3) (6)
1
ns
tLHT
Rise Time (3) (2)
20% to 80% points
0.350
0.6
1.0
ns
tHLT
Fall Time (3) (2)
80% to 20% points
0.350
0.6
1.0
ns
tPHZ
Disable Time (Active High to Z)
3
25
ns
tPLZ
Disable Time (Active Low to Z)
3
25
ns
tPZH
Enable Time (Z to Active High)
100
120
ns
tPZL
Enable Time (Z to Active Low)
100
120
ns
tDJ
LVDS Data Jitter, Deterministic
(Peak-to-Peak) (7)
VID = 300mV; PRBS = 223 − 1 data; VCM = 1.2V at
400Mbps (NRZ)
78
ps
tRJ
LVDS Clock Jitter, Random (7)
VID = 300mV; VCM = 1.2V at 200MHz clock
fMAX
Maximum specified frequency (8)
VID = 200mV, VCM = 1.2V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
4
VID = 200mV, VCM = 1.2V,
RL = 27Ω or 50Ω, CL = 15pF
See Figure 5 and Figure 6
0
RL = 50Ω or 27Ω, CL = 15pF
See Figure 5 and Figure 7
RL = 50Ω, CL = 15pF See Figure 8 and Figure 9
36
200
300
ps
MHz
All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.
Propagation delay, rise and fall times are specified by design and characterization to 200MHz. Generator for these tests: 50MHz ≤ f ≤
200MHz, Zo = 50Ω, tr, tf ≤ 0.5ns. Generator used was HP8130A (300MHz capability).
The parameters are specified by design. The limits are based on statistical analysis of the device performance over the PVT (process,
voltage and temperature) range.
tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel (a measure of duty cycle).
tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. This parameter
specified by design and characterization.
tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
The parameters are specified by design. The limits are based on statistical analysis of the device performance over the PVT range with
the following test equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A
(digital scope mainframe) with Agilent 86122A (20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24
picoseconds; tDJ measured 100 picoseconds, tRJ measured 60 picoseconds.
fMAX test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD ≥ 200mV, Duty Cycle better than 45/55%.
This specification is specified by design and characterization. A minimum is specified, which means that the device will operate to
specified conditions from DC to the minimum specified AC frequency. The typical value is always greater than the minimum
specification.
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
DS92001
www.ti.com
SNLS147F – JUNE 2002 – REVISED APRIL 2013
DC Test Circuits
Figure 3. Differential Driver DC Test Circuit
Figure 4. Differential Driver Full Load DC Test Circuit
AC Test Circuits and Timing Diagrams
Figure 5. BLVDS Output Load
Figure 6. Propagation Delay Low-to-High and High-to-Low
Figure 7. BLVDS Output Transition Time
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
5
DS92001
SNLS147F – JUNE 2002 – REVISED APRIL 2013
www.ti.com
Figure 8. TRI-STATE Delay Test Circuit
Figure 9. Output active to TRI-STATE and TRI-STATE to active output time
PIN DESCRIPTIONS
6
Pin Name
Pin #
Input/Outp
ut
GND
1
P
Ground
IN −
2
I
Inverting receiver B/LVDS input pin
IN+
3
I
Non-inverting receiver B/LVDS input pin
N/C
4
NA
Description
"NO CONNECT" pin
VCC
5
P
Power Supply, 3.3V ± 0.3V.
OUT+
6
O
Non-inverting driver BLVDS output pin
OUT -
7
O
Inverting driver BLVDS output pin
EN
8
I
Enable pin. When EN is LOW, the driver is disabled and the BLVDS outputs
are in TRI-STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL
levels.
GND
DAP
P
WSON Package Ground
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
DS92001
www.ti.com
SNLS147F – JUNE 2002 – REVISED APRIL 2013
Typical Applications
BACKPLANE
RT1
RT1
short stubs
connector
connector
connector
DS90LV001
DS92001
RT3
RT3
long stubs
RT2
Primary
Serializer
Deserializer
Redundant
Serializer
Figure 10. Backplane Stub-Hider Application
Figure 11. Cable Repeater Application
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
7
DS92001
SNLS147F – JUNE 2002 – REVISED APRIL 2013
www.ti.com
APPLICATION INFORMATION
The DS92001 can be used as a "stub-hider." In many systems, signals are distributed across backplanes, and
one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and
the unterminated receivers on the individual cards. See Figure 10. Although it is generally recognized that this
distance should be as short as possible to maximize system performance, real-world packaging concerns and
PCB designs often make it difficult to make the stubs as short as the designer would like. The DS92001,
available in the WSON package, can improve system performance by allowing the receiver to be placed very
close to the main transmission line either on the backplane itself or very close to the connector on the card.
Longer traces to the LVDS receiver may be placed after the DS92001. This very small WSON package is a 75%
space savings over the SOIC package.
The DS92001 may also be used as a repeater as shown in Figure 11. The signal is recovered and redriven at full
strength down the following segment. The DS92001 may also be used as a level translator, as it accepts LVDS,
BLVDS, and LVPECL inputs.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1μF and 0.01μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple
vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid
tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply
and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to
put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
For PC board considerations for the WSON package, please refer to application note AN-1187 “Leadless
Leadframe Package” (Literature Number SNOA401). It is important to note that to optimize signal integrity
(minimize jitter and noise coupling), the WSON thermal land pad, which is a metal (normally copper) rectangular
region located under the package as seen in Figure 12, should be attached to ground and match the dimensions
of the exposed pad on the PCB (1:1 ratio).
Figure 12. WSON Thermal Land Pad and Pin Pads
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)
and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave
the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
8
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
DS92001
www.ti.com
SNLS147F – JUNE 2002 – REVISED APRIL 2013
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result. Do not rely solely on the auto-route function for differential traces. Carefully review dimensions to
match differential impedance and provide isolation for the differential lines. Minimize the number of vias and
other discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
TERMINATION
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90Ω and 130Ω for point-to-point links. Multidrop (driver in the middle) or multipoint
configurations are typically terminated at both ends. The termination value may be lower than 100Ω due to
loading effects and in the 50Ω to 100Ω range. Remember that the current mode outputs need the termination
resistor to generate the differential voltage.
Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the
termination to the receiver inputs should be minimized. The distance between the termination resistor and the
receiver should be < 10mm (12mm MAX).
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
9
DS92001
SNLS147F – JUNE 2002 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
•
10
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS92001
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS92001TLD/NOPB
ACTIVE
WSON
NGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
92001
DS92001TMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
92001
TMA
DS92001TMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
92001
TMA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS92001TLD/NOPB
WSON
NGK
8
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
DS92001TMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS92001TLD/NOPB
WSON
NGK
8
1000
210.0
185.0
35.0
DS92001TMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NGK0008A
LDA08A (Rev C)
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising