Texas Instruments | DS96F173MQML/DS96F175MQML EIA-485/EIA-422 Quad Differential Receivers (Rev. A) | Datasheet | Texas Instruments DS96F173MQML/DS96F175MQML EIA-485/EIA-422 Quad Differential Receivers (Rev. A) Datasheet

Texas Instruments DS96F173MQML/DS96F175MQML EIA-485/EIA-422 Quad Differential Receivers (Rev. A) Datasheet
DS96F173MQML, DS96F175MQML
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SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
DS96F173MQML/DS96F175MQML EIA-485/EIA-422 Quad Differential Receivers
Check for Samples: DS96F173MQML, DS96F175MQML
FEATURES
DESCRIPTION
•
•
•
•
The DS96F173 and the DS96F175 are high speed
quad differential line receivers designed to meet the
EIA-485 standard. The DS96F173 and the DS96F175
offer improved performance due to the use of L-FAST
bipolar technology. The use of LFAST technology
allows the DS96F173 and DS96F175 to operate at
higher speeds while minimizing power consumption.
1
2
•
•
•
•
•
•
Meets EIA-485, EIA-422A, EIA-423A Standards
Designed for Multipoint Bus Applications
TRI-STATE Outputs
Common Mode Input Voltage Range: −7V to
+12V
Operates from Single +5.0V Supply
Lower Power Version
Input Sensitivity of ±200 mV Over Common
Mode Range
Input Hysteresis of 50 mV Typical
High Input Impedance
DS96F173 and DS96F175 are Lead and
Function Compatible with SN75173/175 or the
AM26LS32/MC3486
The DS96F173 and the DS96F175 have TRI-STATE
outputs and are optimized for balanced multipoint
data bus transmission at rates up to 15 Mbps. The
receivers feature high input impedance, input
hysteresis for increased noise immunity, and input
sensitivity of 200 mV over a common mode input
voltage range of −7V to +12V. The receivers are
therefore suitable for multipoint applications in noisy
environments. The DS96F173 features an active high
and active low Enable, common to all four receivers.
The DS96F175 features separate active high Enables
for each receiver pair.
Connection Diagrams
16-Lead Ceramic Dual-In-Line Package
DS96F173
Figure 1. Top View
(Package Number NFE0016A)
DS96F175
Figure 2. Top View
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DS96F173MQML, DS96F175MQML
SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
20-Lead Ceramic Leadless Chip Carrier
www.ti.com
(Package Number NAJ0020A)
*NC—No Connection
Figure 3. Top View
Figure 4. Top View
Logic Diagrams
DS96F173
2
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DS96F175
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SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
Function Tables
Table 1. (Each Receiver) DS96F173 (1)
Differential Inputs
Output
E
E
Y
VID ≥ 0.2V
H
X
H
X
L
H
H
X
L
X
L
L
X
L
X
Z
X
X
H
Z
VID ≤ −0.2V
(1)
Enable
A–B
H = High Level
L = Low Level
Z = High Impedance (off)
X = Don't Care
Table 2. (Each Receiver) DS96F175
Differential Inputs
Enable
Output
A–B
E
Y
H
VID ≥ 0.2V
H
VID ≤ −0.2V
H
L
X
L
Z
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SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
−65°C ≤ TA ≤ +175°C
Storage Temperature Range(TStg)
Lead Temperature (Soldering, 60 sec.)
300°C
Max. Package Power Dissipation at 25°C (2)
CDIP (NFE)
1,500 mW
CDIP (NAD)
1,034 mW
LCCC (NAJ)
1,500 mW
Supply Voltage
7.0V
Input Voltage, A or B Inputs
±25V
Differential Input Voltage
±25V
Enable Input Voltage
7.0V
Low Level Output Current
(1)
(2)
50 mA
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics--DC Parameters. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Above TA = 25°C derate NFE package 10 mW/°C, NAD package 6.90 mW/°C, NAJ package 11.11 mW/°C.
Recommended Operating Conditions
Min
Max
Units
4.50
5.50
V
Common Mode Input Voltage (VCM)
−7
+12
V
Differential Input Voltage (VID)
−7
Supply Voltage (VCC)
+12
V
Output Current HIGH (IOH)
−400
μA
Output Current LOW (IOL)
16
mA
125
°C
−55
Operating Temperature (TA)
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
4
Subgroup
Description
Temp (°C)
1
Static tests at
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
12
Settling time at
+25
13
Settling time at
+125
14
Settling time at
-55
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SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
Electrical Characteristics--DC Parameters
The following conditions apply, unless otherwise specified.
Symbol
ICC
Parameter
VCC = 5.0V, Outputs Enabled
Max
Units
Subgroups
50
mA
1, 2, 3
V
1, 2, 3
0.45
V
1, 2, 3
VCC = 4.5V & 5.5V, VCM = 0V, VO =
2.5V, IO = -400µA
0.20
V
1, 2, 3
VCC = 4.5V & 5.5V,
VCM = -12V, VO = 2.5V,
IO = -400µA
0.20
V
1, 2, 3
VCC = 4.5V & 5.5V, VCM = 12V, VO
= 2.5V, IO = -400µA
0.20
V
1, 2, 3
Conditions
See
(1)
Logical "1" Output Voltage
VCC = 4.5V, IOH = -400µA,
VID = 0.2V
See
(2)
Logical "0" Output Voltage
VCC = 4.5V, IOL = 8mA,
VID = -0.2V
See
(2)
Supply Current
VCC = 5.5V, VID = 2V
VOH
VOL
VTH
VTL
II
Differential-Input High Threshold
Voltage
Differential-Input Low Threshold
Voltage
2.5
-0.20
V
1, 2, 3
VCC = 4.5V & 5.5V,
VCM = -12V, VO = 0.5V,
IO = 16mA
-0.20
V
1, 2, 3
VCC = 4.5V & 5.5V, VCM = 12V, VO
= 0.5V, IO = 16mA
-0.20
V
1, 2, 3
mA
1, 2, 3
mA
1, 2, 3
µA
1, 2, 3
µA
1, 2, 3
VCC = 4.5V, VI = 12V,
Untested Inputs are 0V
Input Line Current
1.0
VCC = 5.5V, VI = -7V,
Untested Inputs are 0V
Logical "1" Enable Input Current
VCC = 5.5V, VIH = 2.7V
IIL
Logical "0" Enable Input Current
VCC = 5.5V, VIL = 0.4V
IOS
Output Short Circuit Current
VIK
Enable Input Clamp Voltage
High Impedance Output Current
VCC = 4.5V, VO = 0V
VCC = 5.5V, VO = 0V
-0.8
10
-100
See
(3)
-85
-15
mA
1, 2, 3
-85
-15
mA
1, 2, 3
V
1, 2, 3
VCC = 4.5V, II = -18mA
-1.5
VCC = 5.5V, VEn = 0.8V,
VO = 0.4V,
Outputs disabled
-20
20
µA
1, 2, 3
VCC = 5.5V, VEn = 0.8V,
VO = 2.4V,
Outputs disabled
-20
20
µA
1, 2, 3
V
1, 2, 3
V
1, 2, 3
kΩ
1, 2, 3
VIH
Logical "1" Enable Input Voltage
See
(4)
VIL
Logical "0" Enable Input Voltage
See
(5)
RI
Input Resistance
(1)
(2)
(3)
(4)
(5)
Min
VCC = 4.5V & 5.5V, VCM = 0V, VO =
0.5V, IO = 16mA
IIH
IOZ
Notes
2.0
0.8
10
ICC is tested with outputs disabled (worst case), ICC enabled is ensured by this test.
VOH & VOL are tested over common mode voltage range of +/−12V via the VTH / VTL tests.
Only one output at a time should be shorted.
Ensured by VOL & VOH tests.
Ensured by IOZ test.
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SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
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AC Parameters
The following conditions apply, unless otherwise specified.
Symbol
Parameter
Conditions
tPHL
Propagation Delay
CL = 15pF
tPLH
Propagation Delay
CL = 15pF
tPZH
Propagation Delay
CL = 15pF
tPZL
Propagation Delay
CL = 15pF
CL = 5pF
tPHZ
VCC = 5.0V
Notes
See
(1)
Propagation Delay
CL = 20pF
tPLZ
tPW
(1)
6
Propagation Delay
CL = 5pF
Propagation Delay
Min
Subgroups
Max
Units
22
ns
1
30
ns
2, 3
22
ns
1
30
ns
2, 3
16
ns
1
27
ns
2, 3
18
ns
1
27
ns
2, 3
20
ns
1
27
ns
2, 3
30
ns
1
37
ns
2, 3
18
ns
1
30
ns
2, 3
3.0
ns
1
8.0
ns
2
5.0
ns
3
Testing at 20pF assures conformance to spec at 5pF.
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SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
PARAMETER MEASUREMENT INFORMATION
Figure 5. tPLH, tPHL (2) (3)
Figure 6. tHZ, tZH (2) (3) (4) (5)
Figure 7. tZL, tLZ (2) (3) (4) (5)
(2)
(3)
(4)
(5)
The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, tr ≤ 6.0 ns, tf ≤ 6.0 ns, ZO =
50Ω.
CL includes probe and stray capacitance.
All diodes are 1N916 or equivalent.
To test the active low Enable E of DS96F173, ground E and apply an inverted input waveform to E . DS96F175 has active high enable
only.
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SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
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Typical Application
Figure 8.
NOTE
The line length should be terminated at both ends in its characteristic impedance. Stub
lengths off the main line should be kept as short as possible.
8
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SNOSAS9A – APRIL 2011 – REVISED APRIL 2013
REVISION HISTORY
Released
Revision
28–Apr-11
A
Section
New Release, Corporate format
Changes
2 MDS data sheets converted into one Corp. data
sheet format. MNDS96F173M-X Rev 0A0 &
MNDS96F175M-X Rev 0B0 will be archived.
Changes from Original (April 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9076601M2A
ACTIVE
LCCC
NAJ
20
50
TBD
Call TI
Call TI
-55 to 125
DS96F175ME
/883 Q
5962-90766
01M2A ACO
01M2A >T
5962-9076601VEA
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F175MJ-QMLV
5962-9076601VEA Q
5962-9076602M2A
ACTIVE
LCCC
NAJ
20
50
TBD
Call TI
Call TI
-55 to 125
DS96F173ME
/883 Q
5962-90766
02M2A ACO
02M2A >T
5962-9076602MEA
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F173MJ/883
5962-9076602MEA Q
DS96F173ME/883
ACTIVE
LCCC
NAJ
20
50
TBD
Call TI
Call TI
-55 to 125
DS96F173ME
/883 Q
5962-90766
02M2A ACO
02M2A >T
DS96F173MJ/883
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F173MJ/883
5962-9076602MEA Q
DS96F175ME/883
ACTIVE
LCCC
NAJ
20
50
TBD
Call TI
Call TI
-55 to 125
DS96F175ME
/883 Q
5962-90766
01M2A ACO
01M2A >T
DS96F175MJ-QMLV
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F175MJ-QMLV
5962-9076601VEA Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS96F175MQML, DS96F175MQML-SP :
• Military: DS96F175MQML
• Space: DS96F175MQML-SP
NOTE: Qualified Version Definitions:
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 2
MECHANICAL DATA
NFE0016A
J0016A
J16A (REV L)
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MECHANICAL DATA
NAJ0020A
E20A (Rev F)
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