Texas Instruments | DS90LV011A 3V LVDS Single High Speed Differential Driver (Rev. C) | Datasheet | Texas Instruments DS90LV011A 3V LVDS Single High Speed Differential Driver (Rev. C) Datasheet

Texas Instruments DS90LV011A 3V LVDS Single High Speed Differential Driver (Rev. C) Datasheet
DS90LV011A
www.ti.com
SNLS140C – MAY 2002 – REVISED APRIL 2013
DS90LV011A 3V LVDS Single High Speed Differential Driver
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FEATURES
DESCRIPTION
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The DS90LV011A is a single LVDS driver device
optimized for high data rate and low power
applications. The DS90LV011A is a current mode
driver allowing power dissipation to remain low even
at high frequency. In addition, the short circuit fault
current is also minimized. The device is designed to
support data rates in excess of 400Mbps (200MHz)
utilizing Low Voltage Differential Signaling (LVDS)
technology.
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Conforms to TIA/EIA-644-A Standard
>400Mbps (200MHz) Switching Rates
700 ps (100 ps Typical) Maximum Differential
Skew
1.5 ns Maximum Propagation Delay
Single 3.3V Power Supply
±350 mV Differential Signaling
Power Off Protection (Outputs in TRI-STATE)
Pinout Simplifies PCB Layout
Low Power Dissipation (23 mW @ 3.3V
Typical)
SOT-23 5-Lead Package
SOT-23 Version Pin Compatible with
SN65LVDS1
Fabricated with Advanced CMOS Process
Technology
Industrial Temperature Operating Range
– (−40°C to +85°C)
The device is in a 5-lead SOT-23 package. The
LVDS outputs have been arranged for easy PCB
layout. The differential driver outputs provide low EMI
with its typical low output swing of 350 mV. The
DS90LV011A can be paired with its companion single
line receiver, the DS90LV012A, or with any of TI's
LVDS receivers, to provide a high-speed LVDS
interface.
Connection Diagram
Figure 1. Top View
See Package Number DBV (R-PDSO-G5)
Functional Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
DS90LV011A
SNLS140C – MAY 2002 – REVISED APRIL 2013
www.ti.com
Absolute Maximum Ratings (1)
−0.3V to +4V
Supply Voltage (VDD)
LVCMOS input voltage (TTL IN)
−0.3V to +3.6V
LVDS output voltage (OUT±)
−0.3V to +3.9V
LVDS output short circuit current
24mA
Maximum Package Power Dissipation @ +25°C
DBV Package
902 mW
Derate DBV Package
7.22 mW/°C above +25°C
Thermal Resistance (θJA)
138.5°C/Watt
−65°C to +150°C
Storage Temperature
Lead Temperature – Soldering
+260°C (4 sec.)
Maximum Junction Temperature
+150°C
ESD Ratings
≥ 9kV
HBM (1.5 kΩ, 100 pF)
EIAJ (0 Ω, 200 pF)
≥ 900V
CDM (0 Ω, 0 pF)
≥ 2000V
IEC direct (330 Ω, 150 pF)
(1)
≥ 4kV
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
Recommended Operating Conditions
Min
Typ
Max
Supply Voltage (VDD)
3.0
3.3
3.6
V
Temperature (TA)
-40
+25
+85
°C
2
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Units
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV011A
DS90LV011A
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SNLS140C – MAY 2002 – REVISED APRIL 2013
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Conditions
RL = 100Ω
(Figure 2 and Figure 3)
Pin
Min
Typ
Max
Units
OUT+,
OUT−
250
350
450
mV
3
35
mV
1.125
1.22
1.375
V
0
1
25
mV
|VOD|
Output Differential Voltage
ΔVOD
VOD Magnitude Change
VOS
Offset Voltage
ΔVOS
Offset Magnitude Change
IOFF
Power-off Leakage
VOUT = 3.6V or GND, VDD = 0V
±1
±10
μA
IOS
Output Short Circuit Current (4)
VOUT+ and VOUT− = 0V
−6
−24
mA
IOSD
Differential Output Short Circuit
Current (4)
VOD = 0V
−5
−12
mA
COUT
Output Capacitance
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
VIN = 3.3V or 2.4V
IIL
Input Low Current
VIN = GND or 0.5V
VCL
Input Clamp Voltage
ICL = −18 mA
CIN
Input Capacitance
IDD
Power Supply Current
RL = 100Ω
(Figure 2)
3
TTL IN
VDD
V
GND
0.8
V
±2
±10
μA
±1
±10
μA
−1.5
(2)
(3)
(4)
−0.6
V
3
No Load
VIN = VDD or GND
VDD
RL = 100Ω
(1)
pF
2.0
pF
5
8
mA
7
10
mA
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD.
All typicals are given for: VDD = +3.3V and TA = +25°C.
The DS90LV011A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers
outputs.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Switching Characteristics
Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified. (1) (2) (3) (4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHLD
Differential Propagation Delay High to Low
RL = 100Ω, CL = 15 pF
0.3
1.0
1.5
ns
tPLHD
Differential Propagation Delay Low to High
(Figure 4 and Figure 5)
0.3
1.1
1.5
ns
tSKD1
Differential Pulse Skew |tPHLD − tPLHD| (5)
0
0.1
0.7
ns
tSKD3
Differential Part to Part Skew
(6)
0
0.2
1.0
ns
tSKD4
Differential Part to Part Skew (7)
0
0.4
1.2
ns
tTLH
Transition Low to High Time
0.2
0.5
1.0
ns
tTHL
Transition High to Low Time
0.2
0.5
1.0
ns
200
250
fMAX
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Maximum Operating Frequency
(8)
MHz
All typicals are given for: VDD = +3.3V and TA = +25°C.
These parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage, temperature) ranges.
CL includes probe and fixture capacitance.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, tf ≤ 1 ns (10%-90%).
tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD >
250mV. The parameter is specified by design. The limit is based on the statistical analysis of the device over the PVT range by the
transitions times (tTLH and tTHL).
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Product Folder Links: DS90LV011A
3
DS90LV011A
SNLS140C – MAY 2002 – REVISED APRIL 2013
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 2. Differential Driver DC Test Circuit
Figure 3. Differential Driver Full Load DC Test Circuit
Figure 4. Differential Driver Propagation Delay and Transition Time Test Circuit
Figure 5. Differential Driver Propagation Delay and Transition Time Waveforms
4
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Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV011A
DS90LV011A
www.ti.com
SNLS140C – MAY 2002 – REVISED APRIL 2013
APPLICATION INFORMATION
Table 1. Device Pin Descriptions
Package Pin Number
SOT-23
Pin Name
Description
5
TTL IN
LVTTL/LVCMOS driver input pins
4
OUT+
Non-inverting driver output pin
3
OUT−
Inverting driver output pin
2
GND
Ground pin
1
VDD
Power supply pin, +3.3V ± 0.3V
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Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV011A
5
DS90LV011A
SNLS140C – MAY 2002 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
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6
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 5
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90LV011ATMF
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
N01
DS90LV011ATMF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
N01
DS90LV011ATMFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
N01
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Aug-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SOT-23
DBV
5
1000
178.0
8.4
DS90LV011ATMF/NOPB SOT-23
DBV
5
1000
178.0
DS90LV011ATMFX/NOPB SOT-23
DBV
5
3000
178.0
DS90LV011ATMF
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90LV011ATMF
SOT-23
DBV
5
1000
210.0
185.0
35.0
DS90LV011ATMF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
DS90LV011ATMFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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