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Texas Instruments DS92LV1260 Six Channel 10 Bit BLVDS Deserializer (Rev. F) Datasheet
DS92LV1260
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SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
DS92LV1260 Six Channel 10 Bit BLVDS Deserializer
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FEATURES
DESCRIPTION
•
The DS92LV1260 integrates six deserializer devices
into a single chip. The chip uses a 0.25u CMOS
process
technology.
The
DS92LV1260
can
simultaneously deserialize up to six data streams that
have been serialized by the Texas Instruments
DS92LV1021 or DS92LV1023 Bus LVDS serializers.
The device also includes a seventh serial input
channel that serves as a redundant input.
1
2
•
•
•
•
•
•
•
•
•
Deserializes One to Six BusLVDS Input Serial
Data Streams with Embedded Clocks
Seven Selectable Serial Inputs to Support n+1
Redundancy of Deserialized Streams
Seventh Channel has Single Pin Monitor
Output That Reflects Input From Seventh
Channel Input
Parallel Clock Rate up to 40MHz
On Chip Filtering for PLL
Absolute Maximum Worst Case Power
Dissipation = 1.9W at 3.6V
High Impedance Inputs Upon Power Off (Vcc =
0V)
Single Power Supply at +3.3V
196-pin NFBGA Package (Low-profile Ball Grid
Array) Package
Industrial Temperature Range Operation:
−40°C to +85°C
Each deserializer block in the DS92LV1260 operates
independently with its own clock recovery circuitry
and lock-detect signaling.
The DS92LV1260 uses a single +3.3V power supply
with a typical power dissipation of 1.2W at 3.3V with
a PRBS-15 pattern. Refer to the Connection
Diagrams for packaging information.
Block Diagram
Figure 1. Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage (Vcc)
-0.3 to 4V
Bus LVDS Input Voltage (Rin +/-)
-0.3V to 3.9V
Maximum Package Power Dissipation @25°C
3.7W
Package Thermal Resistance
θJA 196 NFBGA:
34°C/W
θJC 196 NFBGA:
8°C/W
Storage Temp. Range
-65°C to +150°C
Junction Termperature
+150°C
Lead Temperature (Soldering 10 Sec)
+225°C
ESD Rating:
Human Body Model
>3KV
Machine Model
>750V
Reliability Information
Transistor Count
(1)
(2)
35,682
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Recommended Operating Conditions
Supply Voltage (VCC)
3.0V to 3.6V
Operating Free Air
Temperature (TA)
-40°C to +85°C
Operating Frequency
16-40 MHz
Electrical Characteristics (1)
Basic functionality and specifications per deserializer channel will be similar to DS92LV1212A. Over recommended operating
supply and termperature ranges unless otherwise specified. (2)
Parameter
Test Conditions
Pin/Freq.
Min
Typ
Max
Units
VCC
V
0.8
V
LVCMOS/LVTTL DC Specifications:
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VCL
Input Clamp Voltage
IIN
Input Current
Vin = 0 or 3.6V
VOH
High Level Output Voltage
IOH = -6mA
VOL
Low Level Output Voltage
IOL = 6mA
IOS
Output short Circuit Current
Vout = 0V, (3)
IOZ
TRI-STATE Output Current
PWRDWN or REN = 0.8V,
Vout = 0V or VCC
(1)
(2)
(3)
2
2.0
REN,REFCLK,PWRDWN,
SEL (0:2),ROUT
GND
-0.87
-10
Rout,
RCLK,
LOCK
-1.5
V
+10
uA
VCC
V
2
3
GND
0.18
0.4
V
-15
-46
-85
mA
-10
+/-0.2
+10
uA
Current into the device pins is defined as positive. Current out of device pins is defined as negative. Voltage are referenced to ground
except VTH and VTL which are differential voltages.
Typical values are given for Vcc = 3.3V and TA =25°C
Only one output should be shorted at a time. Do not exceed maximum package power dissipation capacity.
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Electrical Characteristics(1) (continued)
Basic functionality and specifications per deserializer channel will be similar to DS92LV1212A. Over recommended operating
supply and termperature ranges unless otherwise specified.(2)
Parameter
Test Conditions
Pin/Freq.
Min
Typ
Max
Units
+3
+50
mV
Bus LVDS DC specifications
Differential Threshold High
Voltage
VTH
Differential Threshold Low
Voltage
VTL
IIN
Input Current
VCM = 1.1V (VRI+-VRI-)
Vin = +2.4V,
Vcc = 3.6 or 0V
-50
-2
mV
-10
+/- 1
+10
uA
-10
+/- 1
+10
uA
460
530
mA
0.36
1
mA
62.5
ns
60
%
RI+, RI-
Vin =0V,
Vcc = 3.6 or 0V
Supply Current
3.6V, 40 MHz,
Checker Board
Pattern, CL=15pF
ICCR
Worst Case Supply Current
ICCXR
Supply Current when Powered PWRDN= 0.8V
Down
REN = 0.8V
Timing Requirements for REFCLK
tRFCP
REFCLK Period
25
tRFDC
REFCLK Duty Cycle
40
tRFCP/tTCP
Ratio of REFCLK to TCLK
tRFTT
REFCLK Transition Time
50
0.95
1.05
8
ns
62.5
ns
55
%
Deserializer Switching Characteristics
tRCP
RCLK Period
tRDC
RCLK Duty Cycle
tCHTST
Period of Bus LVDS signal
when CHTST is selected by
MUX
tCLH
CMOS/TTL Low-to-High
Transition Time
1.7
6
ns
tCHL
CMOS/TTL High-to-Low
Transition Time
1.6
6
ns
tROS
Rout Data Valid before RCLK
RCLK
See
(4)
See Figure 3
See Figure 3
CHTST
Rout,
LOCK,
RCLK
25
43
50
25
ns
0.4*tRCP
ns
0.4*tRCP
ns
tROH
Rout Data Valid after RCLK
tHZR
High to TRI-STATE Delay
10
ns
tLZR
Low to TRI-STATE Delay
10
ns
tZHR
TRI-STATE to High Delay
12
ns
tZLR
TRI-STATE to Low Delay
12
ns
See Figure 2
tDD
Deserializer Delay
tDSR1
(4)
(5)
Deserializer PLL LOCK Time
from PWRDN (with
SYNCPAT)
Room Temp
3.3V
40MHz
See Figure 4
See (5)
1.75*t
1.75*tR
CP+5
1.75*t
RCP+7
1.75*tR
CP+6
1.75*t
1.75*t
RCP+7
RCP+9
RCLK
RCP+1
ns
0
ns
40MHz
3
us
20MHz
10
us
Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the
data stream were switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate.
For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and
specific conditions of the incoming data stream (SYNCPATs). tDSR1 is the time required for the deserializer to indicate lock upon powerup or when leaving the power-down mode. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when
the input (RI+ and RI−) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). The time to lock
to random data is dependent upon the incoming data.
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Electrical Characteristics(1) (continued)
Basic functionality and specifications per deserializer channel will be similar to DS92LV1212A. Over recommended operating
supply and termperature ranges unless otherwise specified.(2)
Parameter
tDSR2
tRNM
(6)
Deserializer PLL Lock Time
from SYNCPAT
Deserializer Noise Margin
Test Conditions
See Figure 5
See (5)
See
(6)
Pin/Freq.
Min
Typ
40MHz
20MHz
Max
Units
2
us
5
us
40MHz
450
920
ps
20MHz
1200
1960
ps
tRNM is a measure of how much phase noise (jitter)the deserializer can tolerate in the incoming data stream before bit errors occur. The
Deserializer Noise Margin is Specified By Design (GBD) using statistical analysis.
AC Timing Diagrams and Test Circuits
Figure 2. Deserializer Delay tDD
Figure 3. Output Timing tROS and tROH
4
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Figure 4. Locktime from PWRDN* tDSR1
Figure 5. Locktime to SYNCPAT tDSR2
Figure 6. Unlock
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Figure 7. Deserializer Data Valid Out Times
Figure 8. Deserializer TRI-STATE Test Circuit and Timing
6
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Block Diagram
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Control Pins Truth Table (1)
PWRDN
REN
SEL2
SEL1
SEL0
Rout
CHTST
LOCK[0:5]
H
H
L
L
L
Din6
Decoded to
Rout 0
(0:9) (2)
Din0 (not
decoded)
Active (3)
Active (4)
(2)
H
H
L
L
H
Din6
Decoded to
Rout 1
(0:9) (2)
Din1 (not
decoded)
Active (3)
Active (4)
(2)
H
H
L
H
L
Din6
Decoded to
Rout 2
(0:9) (2)
Din2 (not
decoded)
Active (3)
Active (4)
(2)
H
H
L
H
H
Din6
Decoded to
Rout 3
(0:9) (2)
Din3 (not
decoded)
Active (3)
Active (4)
(2)
H
H
H
L
L
Din6
Decoded to
Rout 4
(0:9) (2)
Din4 (not
decoded)
Active (3)
Active (4)
(2)
H
H
H
L
H
Din6
Decoded to
Rout 5
(0:9) (2)
Din5 (not
decoded)
Active (3)
Active (4)
(2)
H
H
H
H
L
Din6 is not
Decoded
Z
Active (3)
Active (4)
(2)
H
H
H
H
H
Din6 is not
Decoded
Din6 (not
decoded)
Active (3)
Active (4)
(2)
L
X
X
X
X
Z
Z
Z
H
(1)
(2)
(3)
(4)
L
X
X
X
Z
Z
Active
RCLK[0:5]
Z
(3)
Z
The routing of the Din inputs to the Deserializers and to the CHTST outputs are dependent on the states of SEL [0:2].
Rout n[0:9] and RCLK [0:5] are Tri-Stated when LOCKn[0:5] is High.
LOCK Active indicates that the LOCK output will reflect the state of it's respective Deserializer with regard to the selected data stream.
RCLK Active indicates that the RCLK will be running if the Deserializer is locked. The timing of RCLK [0:5] with respect to Rout [0:5][0:9]
is determined by RCLK_R/F Figure 6
FUNCTIONAL DESCRIPTION
The DS92LV1260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a
BusLVDS data stream from Texas Instruments' DS92LV1021 or DS92LV1023 Serializer. The deserializers then
recover the clock and data to deliver the resulting 10-bit wide words to the outputs. A seventh serial data input
provides n+1 redundancy capability. The user can program the seventh input to be an alternative input to any of
the six deserializers. Whichever input is replaced by the seventh input is then routed to the CHANNEL TEST
(CHTST) pin on receiver output port.
Each of the 6 channels acts completely independent of each other. Each independent channel has outputs for a
10-bit wide data word, the recovered clock out, and the lock-detect output.
The DS92LV1260 has three operating states: Initialization, Data Transfer, and Resynchronization. In addition,
there are two passive states: Powerdown and TRI-STATE.
The following sections describe each operating mode and passive state.
Initialization
Before the DS92LV1260 receives and deserializes data, it and the transmitting serializer devices must initialize
the link. Initialization refers to synchronizing the Serializer's and the Deserializer's PLL's to local clocks. The local
clocks must be the same frequency or within a specified range if from different sources. After all devices
synchronize to local clocks, the Deserializers synchronize to the Serializers as the second and final initialization
step.
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Step 1: After applying power to the Deserializer, the outputs are held in TRI-STATE and the on-chip powersequencing circuitry disables the internal circuits. When Vcc reaches VccOK (2.1V), the PLL in each deserializer
begins locking to the local clock (REFCLK). A local on-board oscillator or other source provides the specified
clock input to the REFCLK pin.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. Refer to the
Serializer data sheet for the proper operation during this step of the Initialization State. The Deserializer identifies
the rising clock edge in a synchronization pattern or random data and after 80 clock cycles will synchronize to the
data stream from the serializer. At the point where the Deserializer's PLL locks to the embedded clock, the
LOCKn pin goes low and valid data appears on the output. Note that this differs from pervious deserializers
where the LOCKn signal was not synchronous to valid data appearing on the outputs.
Data Transfer
After initialization, the serializer transfers data to the deserializers. The serial data stream includes a start and
stop bit appended by the serializer, which frame the ten data bits. The start bit is always high and the stop bit is
always low. The start and stop bits also function as clock bits embedded in the serial stream.
The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if
TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial
'payload' rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data is 40 X 10 =
400 Mbps. TCLK is provided by the data source and must be in the range 20 MHz to 40 MHz nominal.
When one of six Deserializer channels synchronizes to the input from a Serializer, it drives its LOCKn pin low
and synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to
generate multiple internal data strobes, and drives the embedded clock to the RCLKn pin. The RCLKn is
synchronous to the data on the ROUT[n0:n9] pins. While LOCKn is low, data on ROUT [n0:n9] is valid.
Otherwise, ROUT[n0:n9] is invalid.
All ROUT, LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF load) with a 40 MHz
clock. This amount of drive allows bussing outputs of two Deserializers and a destination ASIC. REN controls
TRI-STATE of all the outputs.
The Deserializer input pins are high impedance during Powerdown (PWRDN low) and power-off (Vcc = 0V).
Resynchronization
Whenever one of the six Deserializers loses lock, it will automatically try to resynchronize. For example, if the
embedded clock edge is not detected two times in succession, the PLL loses lock and the LOCKn pin is driven
high. The system must monitor the LOCKn pin to determine when data is valid.
The user has the choice of allowing the deserializer to re-synch to the data stream or to force synchronization by
pulsing the Serializer SYNC1 or SYNC2 pin. This scheme is left up to the user discretion. One recommendation
is to provide a feedback loop using the LOCKn pin itself to control the sync request of the Serializer (SYNC1 or
SYNC2). Dual SYNC pins are given for multiple control in a multi-drop application.
Powerdown
The Powerdown state is a low power sleep mode that the Serializer and Deserializer typically occupy while
waiting for initialization, or to reduce power consumption when no data is transfers. The Deserializer enters
Powerdown when PWRDN is driven low. In Powerdown, the PLL stops and the outputs go into TRI-STATE,
which reduces supply current to the microamp range. To exit Powerdown, the system drives PWRDN high.
Upon exiting Powerdown, the Deserializer enters the Initialization state. The system must then allow time to
Initialize before data transfer can begin.
TRI-STATE
When the system drives REN pin low, the Deserializer enters TRI-STATE. This will TRI-STATE the receiver
output pins (ROUT[00:59]) and RCLK[0:5]. When the system drives REN high, the Deserializer will return to the
previous state as long as all other control pins remain static (PWRDN, RCLK_R/F).
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USING THE DS92LV1021 AND DS92LV1260
The DS92LV1260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a
BusLVDS data stream up to 480 Mbps from Texas Instruments' DS92LV1021 or DS92LV1023 Serializer. The
deserializers then recover the embedded two clock bits and data to deliver the resulting 10-bit wide words to the
output. A seventh serial data input provides n+1 redundancy capability. The user can program the seventh input
to be an alternative input to any of the six deserializers. Whichever input is replaced by the seventh input is then
routed to the CHANNEL TEST (CHTST) pin on receiver output port. The Deserializer uses a separate reference
clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data stream and then
deserialize the data. The Deserializer monitors the incoming clock information, determines lock status, and
asserts the LOCKn output high when loss of lock occurs.
POWER CONSIDERATIONS
An all CMOS design of the Deserializer makes it an inherently low power device.
POWERING UP THE DESERIALIZER
The DS92LV1260 can be powered up at any time by following the proper sequence. The REFCLK input can be
running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming
data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its
inputs and locks to the incoming data stream.
TRANSMITTING DATA
Once you power up the Deserializer, it must be phase locked to the transmitter to transmit data. Phase locking
occurs when the Deserializer locks to incoming data or when the Serializer sends sync patterns. The Serializer
sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCKn output of the Deserializer
remains high until it has locked to the incoming data stream. Connecting the LOCKn output of the Deserializer to
one of the SYNC inputs of the Serializer will ensure that enough SYNC patterns are sent to achieve Deserializer
lock.
The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
NOISE MARGIN
While the Deserializer LOCKn output is low, data at the Deserializer outputs (ROUT0-9) are valid, except for the
specific case of loss of lock during transmission which is further discussed in the RECOVERING FROM LOCK
LOSS section below.
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic factors include:
Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise)
Media: ISI, Large VCM shifts
Deserializer: VCC noise
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RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data transmission, up to 1 cycle of data that was previously
received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that
invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been
lost, it is possible that data was also lost during these cycles. Therefore, after the Deserializer relocks to the
incoming data stream and the Deserializer LOCKn pin goes low, at least one previous data cycle should be
suspect for bit errors.
The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as
described above, or by random locking, which can take more time, depending on the data patterns being
received.
HOT INSERTION
All the BusLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be
unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 12.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-point configurations, through PCB trace, or through
twisted pair cable. In point-to-point configurations, the transmission media need only be terminated at the
receiver end. Please note that in point-to-point configurations, the potential of offsetting the ground levels of the
Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1V common mode range at
the receiver inputs.
FAILSAFE BIASING FOR THE DS92LV1260
The DS92LV1260 has internal failsafe biasing and an improved input threshold sensitivity of +/− 50mV versus
+/− 100mV for the DS92LV1210 or DS92LV1212. This allows for greater differential noise margin in the
DS92LV1260. However, in cases where the receiver input is not being actively driven, the increased sensitivity of
the DS92LV1260 can pickup noise as a signal and cause unintentional locking . For example, this can occur
when the input cable is disconnected.
External resistors can be added to the receiver circuit board to prevent noise pick-up. Typically, the non-inverting
receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. The pull-up and
pull-down resistors (R1 and R2) provide a current path through the termination resistor (RL) which biases the
receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors
should be chosen so that enough current is drawn to provide a +15mV drop across the termination resistor.
Please see Figure 10 for the Failsafe Biasing Setup.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the DS92LV1260 should be designed to provide noise-free power to the
device. Good layout practice will separate high frequency or high level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. There are a few common practices which should be followed
when designing PCB’s for Bus LVDS Signaling. Recommended layout practices are:
• Use at least 4 PCB board layers (Bus LVDS signals, ground, power, and TTL signals).
– Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which
improves power supply filtering, especially at high frequencies, and makes the value and placement of
external bypass capacitors less critical.
• Keep Serializers and Deserializers as close to the (Bus LVDS port side) connector as possible.
– Longer stubs lower the impedance of the bus, increase the load on the Serializer, and lower the threshold
margin at the Deserializers. Deserializer devices should be placed much less than one inch from slot
connectors. Because transition times are very fast on the Serializer Bus LVDS outputs, reducing stub
lengths as much as possible is the best method to ensure signal integrity.
• Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes.
– Surface mount capacitors placed close to power and ground pins work best. External bypass capacitors
should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
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•
•
•
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range 0.001 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for
tantalum capacitors should be at least 5X the power supply voltage being used. Randomly distributed bypass capacitors should also be used.
– Package and pin layout permitting, it is also recommended to use two vias at each power pin as well as all
RF bypass capacitor terminals. Dual vias reduce the interconnect inductance between layers by up to half,
thereby reducing interconnect inductance and extending the effective frequency range of the bypass
components.
– The outer layers of the PCB may be flooded with additional ground planes. These planes will improve
shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system.
Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with
vias. Frequent via placement improves signal integrity on signal transmission lines by providing short
paths for image currents, which reduces signal distortion. Depending on which is greater, the planes
should be pulled back from all transmission lines and component mounting pads a distance equal to the
width of the widest transmission line or the thickness of the dielectric separating the transmission line from
the internal power or ground plane(s). Doing so minimizes effects on transmission line impedances and
reduces unwanted parasitic capacitances at component mounting pads.
Use a termination resistor which best matches the differential impedance of your transmission line.
Leave unused Bus LVDS receiver inputs open (floating).
– Limit traces on unused inputs to <0.5 inches.
Isolate TTL signals from Bus LVDS signals.
Use controlled impedance media.
– The backplane and connectors should have a matched differential impedance.
For a typical application circuit, please see Figure 9.
There are more common practices which should be followed when designing PCBs for LVDS signaling. General
application guidelines and hints may be found in the following application notes: AN-808 (SNLA028), AN-903
(SNLA034), AN-971 (SNLA165), AN-977 (SNLA166), and AN-1108 (SNLA008). For packaging information on
BGA's, please see AN-1126 (SNOA021).
USING TDJIT AND TRNM TO VALIDATE SIGNAL QUALITY
The parameter tRNM is calculated by first measuring how much of the ideal bit the receiver needs to ensure
correct sampling. After determining this amount, what remains of the ideal bit that is available for external
sources of noise is called tRNM.
The vertical limits of the mask are determined by the DS92LV1260 receiver input threshold of +/− 50mV.
Please refer to the eye mask pattern of Figure 11 for a graphic representation of tDJIT and tRNM.
12
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SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
Serializers:
BLVDS Link
+
DS92LV1021 (16-40 MHz)
or
DS92LV1023 (40-66 MHz)
or
DS92LV8028 (25-66 MHz)
(Serializer AGND)
RL
-
RINn
+
AVDD
0.1uF 0.01uF
+Vcc
AGND
DS92LV1260
+Vcc
0.1uF 0.01uF
(16-40 MHz)
DVDD
0.3uF 0.1uF 1.0uH
PVDD
DGND
0.1uF
(Optional)
+Vcc
PGND
Figure 9. Typical Applications Circuit
Figure 10. Failsafe Biasing Setup
Figure 11. Using tDJIT and tRNM to Generate an Eye Pattern Mask and Validate Signal Quality
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DS92LV1260
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
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Figure 12. Random Lock Hot Insertion
Pin Diagram
Figure 13. Top View of DS92LV1260 (196-pin NFBGA package, see Package Number NZH0196A)
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SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
PIN DESCRIPTIONS
Pin No.
Pin Name
Type
GND
GND
C12,C13,B13
SEL (0:2)
3.3V
CMOS
I
These pins control which Bus LVDS input is steered to the CHTST output
A4-A3, C6-C5, A7-A6, C9-C8,
A10-A9, C11-C10, A13-A12
Rin(n) +/-
Bus
LVDS
I
Bus LVDS differential input pins
B2,B14
Description
GND pins for ESD structures
D12
PVdd
Supply voltage for PLL circuitry
F12
AVdd
Supply voltage for input buffer circuitry
B12,A14,D10
PGND
GND pin for PLL circuitry
B11
AGND
GND pin for input buffer circuitry
C7
AVdd
Supply voltage for LVDS REC.
B9
AVdd
Supply voltage for LVDS REC.
A11
AVdd
Supply voltage for Band Gap reference.
B7
AGND
GND pin for AVDD.
A8
AGND
GND pin for AVDD1.
B8
AGND
GND pin for BGVDD.
A5
AGND
GND pin for VDDI.
B6
AVdd
Supply voltage for input logic circuitry.
D7
DGND
Tie to digital ground.
B5
PWRDN
3.3V
CMOS
I
C4
RCLK_R/F
3.3V
CMOS
I
Controls the relation of Rout data to RCLK edge: RCLK_R/F = H setup and
hold times are referred to the rising RCLK edge; RCLK_R/F = L setup and hold
times are referenced to the falling RCLK edge.
A2
REN
3.3V
CMOS
I
Enables the Routn, RCLKn, and SYNCCLK outputs.
B4
REFCLK
3.3V
CMOS
I
Frequency reference clock input.
D5
DGND
GND pin for VDDO
A1
DGND
GND for digital section.
B1
N/C
D6
DVdd
B3
DVdd
C3
F3,P1,N3,P12,P13,D13
E6,J5,K5,K10,J10,E9
Controls whether the device is active or in 'sleep' mode
Do not connect.
Supply voltage for digital section.
Supply voltage for digital section.
CHTST
3.3V
CMOS
O
Allows low speed testing of the Rin inputs under control of the SEL (0:2) pins.
LOCK (0:5)
3.3V
CMOS
O
Indicates the status of the PLLs for the individual deserializers: LOCK= L
indicates locked, LOCK= H indicates unlicked.
DVdd
K3, K4, H3, H4, H2, G4, G3,
F4, E4, E2, J3, L3, J2 ,L1 ,K2
,M1 ,N1 ,N2 ,M2 ,M3 ,M7 ,L6
,N6 ,M6 ,P4, M5, P3, N4, P2,
M4, M8, L8, N9, M9, L9, M10,
M11, N11, P11, N12, K13,
L12, L14, M14, L13, L11, M12,
N13, N14, P14, K12, J12, J11,
H12, H11, G11, G12, E12,
E13, E14
Rout nx
E5,G5,J6,K8,H9,F8
DGND
Supply voltage for the logic circuitry.
3.3V
CMOS
O
Outputs for the ten bit deserializers, n = deserializer number, x = bit number
GND pins for digital section.
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DS92LV1260
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
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PIN DESCRIPTIONS (continued)
Pin No.
F2,L2,N5,N10,M13,F13
Pin Name
Type
RCLK (0:5)
3.3V
CMOS
O
Description
Recovered clock for each deserializer's output data.
D6, F7, E7, G6, H6, K7, K6,
J8, J9, G10, H10, F10, E10
DVdd
Supply voltage for output buffers.
D5, F6, F5, G7, H5, J7, H7,
H8, K9, G9, G8, F9, E8
DGND
GND pins for output buffers.
F1, E1, J1, K1, P6, P5, P9,
P10, J14, K14, G14, F14
PVdd
Supply voltages for PLL circuitry.
G2, G1, H1, J4, N7, P7, P8,
N8, J13, H14, H13, G13
PGND
GND pins for PLL circuitry.
C2,C1,D1,D2,D3,
L4, L5, L7, L10, K11, D11,
B10, D9, E3, D4, E11, F11,
D8, D14, C14
16
JTL (1:5)
N/C
Reserved pins for JTAG access port.
Unused solder ball location. Do not connect.
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SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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17
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
DS92LV1260TUJB/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
NFBGA
NZH
196
119
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
DS92LV1260T
UJB
>B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
MECHANICAL DATA
NZH0196A
UJB196A (Rev C)
www.ti.com
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