Texas Instruments | DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz (Rev. H) | Datasheet | Texas Instruments DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz (Rev. H) Datasheet

Texas Instruments DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz (Rev. H) Datasheet
DS92LV16
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DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz
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FEATURES
DESCRIPTION
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The DS92LV16 Serializer/Deserializer (SERDES) pair
transparently translates a 16–bit parallel bus into a
BLVDS serial stream with embedded clock
information. This single serial stream simplifies
transferring a 16-bit, or less bus over PCB traces and
cables by eliminating the skew problems between
parallel data and clock paths. It saves system cost by
narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins.
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25–80 MHz 16:1/1:16 Serializer/Deserializer
(2.56Gbps Full Duplex Throughput)
Independent Transmitter and Receiver
Operation With Separate Clock, Enable, Power
Down Pins
Hot Plug Protection (Power Up High
Impedance) and Synchronization (Receiver
Locks To Random Data)
Wide +/−5% Reference Clock Frequency
Tolerance for Easy System Design Using
Locally-Generated Clocks
Line and Local Loopback Modes
Robust BLVDS Serial Transmission Across
Backplanes and Cables for Low EMI
No External Coding Required
Internal PLL, No External PLL Components
Required
Single +3.3V Power Supply
Low Power: 104mA (typ) Transmitter, 119mA
(typ) Receiver at 80MHz
±100mV Receiver Input Threshold
Loss of Lock Detection and Reporting Pin
Industrial −40 to +85°C Temperature Range
>2.5kV HBM ESD
Compact, Standard 80-Pin LQFP Package
This SERDES pair includes built-in system and
device test capability. The line loopback and local
loopback features provide the following functionality:
the local loopback enables the user to check the
integrity of the transceiver from the local parallel-bus
side and the system can check the integrity of the
data transmission line by enabling the line loopback.
The DS92LV16 incorporates BLVDS signaling on the
high-speed I/O. BLVDS provides a low power and low
noise environment for reliably transferring data over a
serial transmission path. The equal and opposite
currents through the differential data path control EMI
by coupling the resulting fringing fields together.
Block Diagram
Figure 1. DS92LV16
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1) (2)
−0.3V to +4V
Supply Voltage (VCC)
LVCMOS/LVTTL Input Voltage
−0.3V to (VCC +0.3V)
LVCMOS/LVTTL Output Voltage
−0.3V to (VCC +0.3V)
Bus LVDS Receiver Input Voltage
−0.3V to +3.9V
Bus LVDS Driver Output Voltage
−0.3V to +3.9V
Bus LVDS Output Short Circuit Duration
10ms
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity
Package Derating:
23.2 mW/°C above
LQFP
+25°C
θJA
43°C/W
θJC
11.1°C/W
ESD Rating (HBM)
(1)
(2)
>2.5kV
Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. The table of ELECTRICAL CHARACTERISTICS specifies conditions of device operation.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
RECOMMENDED OPERATING CONDITIONS
Min
Nom
Max
Units
Supply Voltage (VCC)
3.15
3.3
3.45
V
Operating Free Air Temperature (TA)
−40
+25
+85
°C
Clock Rate
25
80
MHz
2
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ELECTRICAL CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
2.0
VCC
V
GND
0.8
V
-0.7
−1.5
V
±2
+10
μA
V
LVCMOS/LVTTL DC Specifications
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VCL
Input Clamp Voltage
TCLK_R/F,DEN,
TCLK, TPWDN, DIN,
ICL = −18 mA
IIN
Input Current
VOH
High Level Output Voltage
IOH = −9 mA
VOL
Low Level Output Voltage
IOL = 9 mA
IOS
Output Short Circuit Current
VOUT = 0V
IOZ
TRI-STATE Output Current
PWRDN or REN =
0.8V, VOUT = 0V or
VCC
SYNC, RCLK_R/F,
REN, REFCLK,
PWRDN
−10
VIN = 0V or 3.6V
ROUT, RCLK, LOCK
ROUT, RCLK,
2.3
3.0
VCC
GND
0.33
0.5
V
−15
−48
−85
mA
−10
±0.4
+10
μA
+100
mV
Bus LVDS DC specifications
VTH
Differential Threshold High
Voltage
VTL
Differential Threshold Low
Voltage
IIN
Input Current
VOD
Output Differential Voltage
(DO+) - (DO-)
ΔVOD
Output Differential Voltage
Unbalance
VOS
Offset Voltage
ΔVOS
Offset Voltage Unbalance
IOS
Output Short Circuit Current
IOZ
VCM = +1.1V
−100
RI+, RIVIN = +2.4V,
VCC = 3.6V or 0V
−10
±5
+10
μA
VIN = 0V,
VCC = 3.6V or 0V
−10
±5
+10
μA
RL = 100Ω,
See Figure 18
350
500
550
mV
2
15
mV
1.2
1.25
V
2.7
15
mV
-35
-50
-70
mA
TXPWDN or DEN =
0.8V, DO = 0V OR
VDD
-10
±1
10
µA
VDD = 0V, DO = 0V or
3.6V
-10
±1
10
µA
1.05
Tri-State Output Current
IOX
Power-Off Output Current
ICCT
Total Supply Current (includes
load current)
mV
DO = 0V, Din = H,
TXPWDN and DEN =
2.4V
DO+, DO-
SER/DES SUPPLY CURRENT (DVDD, PVDD and AVDD pins)
ICCX
Supply Current Powerdown
CL = 15 pF, RL = 100 Ω
f = 80 MHz, PRBS15
pattern
209
CL = 15 pF, RL = 100 Ω
f = 80 MHz, Worse
case pattern
(Checker-board
pattern)
225
320
mA
0.35
1.0
mA
PWRDN = 0.8V,
REN = 0.8V
mA
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SERIALIZER TIMING REQUIREMENTS FOR TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tTCP
Transmit Clock Period
12.5
T
40
ns
tTCIH
Transmit Clock High Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock Low Time
0.4T
0.5T
0.6T
ns
tCLKT
TCLK Input Transition Time
3
6
ns
tJIT
TCLK Input Jitter
80
ps (rms)
SERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
(1)
Symbol
Parameter
tLLHT
Bus LVDS Low-to-High
Transition Time
tLHLT
Bus LVDS High-to-Low
Transition Time
tDIS
DIN (0-15) Setup to TCLK
tDIH
DIN (0-15) Hold from TCLK
tHZD
DO ± HIGH to
TRI-STATE Delay
tLZD
DO ± LOW to
TRI-STATE Delay
tZHD
DO ± TRI-STATE to
HIGH Delay
tZLD
DO ± TRI-STATE to
LOW Delay
tSPW
SYNC Pulse Width
tPLD
Serializer PLL Lock Time
tSD
Serializer Delay
tRJIT
Random Jitter
tDJIT
Deterministic Jitter
See Figure 16
Conditions
Min
RL = 100Ω
See Figure 4
CL=10pF to GND
RL = 100Ω
See Figure 7
CL=10pF to GND
Typ
Max
Units
0.2
0.4
ns
0.2
0.4
ns
2.4
ns
0
ns
RL = 100Ω
See Figure 8 (1)
CL=10pF to GND
2.3
10
ns
1.9
10
ns
1.0
10
ns
1.0
10
ns
RL = 100Ω
See Figure 9
5*tTCP
6*tTCP
ns
510*tTCP
513*tTCP
ns
RL = 100Ω
See Figure 10
tTCP + 1.0
tTCP + 4.0
ns
tTCP + 2.0
10
ps (rms)
35 MHz
-240
140
ps
80 MHz
-75
100
ps
Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
DESERIALIZER TIMING REQUIREMENTS FOR REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
4
Parameter
Conditions
Min
Typ
Max
Units
tRFCP
REFCLK Period
12.5
T
40
ns
tRFDC
REFCLK Duty Cycle
40
50
60
%
tRFCP / tTCP
Ratio of REFCLK to TCLK
0.95
tRFTT
REFCLK Transition Time
1.05
6
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DESERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tRCP
Receiver out Clock
Period
tRDC
RCLK Duty Cycle
tCLH
CMOS/TTL
Low-to-High
Transition Time
tCHL
tROS
CMOS/TTL
High-to-Low
Transition Time
ROUT (0-9) Setup
Data to RCLK
tROH
ROUT (0-9) Hold
Data to RCLK
tHZR
HIGH to TRI-STATE
Delay
tLZR
LOW to TRI-STATE
Delay
Conditions
tRCP = tTCP
See Figure 10
Pin/Freq.
Min
RCLK
12.5
RCLK
45
Typ
Max
Units
40
ns
50
55
%
2
4
ns
2
4
ns
CL = 15 pF
See Figure 5
Rout(0-9),
LOCK,
RCLK
0.35*tRCP
0.5*tRCP
ns
−0.35*tRCP
−0.5*tRCP
ns
See Figure 12
See Figure 13
Rout(0-9),
LOCK
2.2
10
ns
2.2
10
ns
2.3
10
ns
2.9
10
ns
1.75*tRCP + 7
ns
tZHR
TRI-STATE to HIGH
Delay
tZLR
TRI-STATE to LOW
Delay
tDD
Deserializer Delay
RCLK
tDSR1
Deserializer PLL
Lock Time from
PWRDWN (with
SYNCPAT)
35MHz
3.7
10
μs
80 MHz
1.9
4
μs
35MHz
1.5
5
μs
80 MHz
0.9
See (1)
tDSR2
Deserializer PLL
Lock time from
SYNCPAT
tRNMI-R
Ideal Deserializer
Noise Margin Right
See Figure 17 (2)
tRNMI-L
Ideal Deserializer
Noise Margin Left
See Figure 17 (2)
(1)
(2)
1.75*tRCP + 2 1.75*tRCP + 5
35 MHz
80 MHz
2
μs
+630
ps
+230
ps
35 MHz
−630
ps
80 MHz
−230
ps
Sync pattern is a fixed pattern with 8-bit of data high followed by 8-bit of data low.
tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It
is a measurement in reference with the ideal bit position, please see Tl’s AN-1217(SNLA053) for detail.
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AC TIMING DIAGRAMS AND TEST CIRCUITS
Figure 2. “Worst Case” Serializer ICC Test Pattern
Figure 3. “Worst Case” Deserializer ICC Test Pattern
Figure 4. Serializer Bus LVDS Output Load and Transition Times
Figure 5. Deserializer CMOS/TTL Output Load and Transition Times
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Figure 6. Serializer Input Clock Transition Time
Figure 7. Serializer Setup/Hold Times
Figure 8. Serializer TRI-STATE Test Circuit and Timing
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Figure 9. Serializer PLL Lock Time, SYNC Timing and PWRDN TRI-STATE Delays
Figure 10. Serializer Delay
Figure 11. Deserializer Delay
Figure 12. Deserializer Setup and Hold Times
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Figure 13. Deserializer TRI-STATE Test Circuit and Timing
Figure 14. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
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Figure 15. Deserializer PLL Lock Time from SyncPAT
Figure 16. Deterministic Jitter and Ideal Bit Position
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tRNMI-L is the noise margin on the left of the above figure. It is a negative value to indicate early with respect to ideal.
tRNMI-R is the noise margin on the right of the above figure. It is a positive value to indicate late with respect to ideal.
Figure 17. Deserializer Noise Margin (tRNMI) and Sampling window
VOD = (DO+)–(DO−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
Figure 18. VOD Diagram
Figure 19. Icc vs Freq
Figure 20. Icc vs Freq (Rx only)
Figure 21. Icc vs Freq (Tx only)
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FUNCTIONAL DESCRIPTION
The DS92LV16 combines a serializer and deserializer onto a single chip. The serializer accepts a 16-bit
LVCMOS or LVTTL data bus and transforms it into a BLVDS serial data stream with embedded clock
information. The deserializer then recovers the clock and data to deliver the resulting 16-bit wide words to the
output.
The device has a separate Transmit block and Receive block that can operate independent of each other. Each
has a power down control to enable efficient operation in various applications. For example, the transceiver can
operate as a standby in a redundant data path but still conserve power. The part can be configured as a
Serializer, Deserializer, or as a Full Duplex SER/DES.
The DS92LV16 serializer and deserializer blocks each has three operating states. They are the Initialization,
Data Transfer, and Resynchronization states. In addition, there are two passive states: Powerdown and TRISTATE.
The following sections describe each operation mode and passive state.
INITIALIZATION
Before the DS92LV16 sends or receives data, it must initialize the links to and from another DS92LV16.
Initialization refers to synchronizing the Serializer's and Deserializer's PLL's to local clocks. The local clocks must
be the same frequency or within a specified range if from different sources. After the Serializers synchronizes to
the local clocks, the Deserializers synchronize to the Serializers as the second and final initialization step.
Step 1: When VCC is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE
and internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.2V) the PLL in each
device begins locking to a local clock. For the Serializer, the local clock is the transmit clock, TCLK. For the
Deserializer, the local clock is applied to the REFCLK pin. A local on-board oscillator or other source provides
the specified clock input to the TCLK and REFCLK pin.
The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the
Serializer block is now ready to send data or synchronization patterns. If the SYNC pin is high, then the Serializer
block generates and sends the synchronization patterns (sync-pattern).
The Deserializer output will remain TRI-STATE while its PLL locks to the REFCLK. Also, the Deserializer LOCK
output will remain high until its PLL locks to an incoming data or sync-pattern on the RIN pins.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. The Serializer that
is generating the stream to the Deserializer must send random (non-repetitive) data patterns or sync-patterns
during this step of the Initialization State. The Deserializer will lock onto sync-patterns within a specified amount
of time. The lock to random data depends on the data patterns and therefore, the lock time is unspecified.
In order to lock to the incoming LVDS data stream, the Deserializer identifies the rising clock edge in a syncpattern and after 150 clock cycles will synchronize. If the Deserializer is locking to a random data stream from
the Serializer, then it performs a series of operations to identify the rising clock edge and locks to it. Because this
locking procedure depends on the data pattern, it is not possible to specify how long it will take. At the point
where the Deserializer's PLL locks to the embedded clock, the LOCK pin goes low and valid data appears on the
output. Note that the LOCK signal is synchronous to valid data appearing on the outputs.
The user's application determines whether sync-pattern or lock to random data is the preferred method for
synchronization. If sync-patterns are preferred, the associated deserializers LOCK pin is a convenient way to
provide control of the SYNC pin.
DATA TRANSFER
After initialization, the DS92LV16 Serializer is able to transfer data to the Deserializer. The serial data stream
includes a start bit and stop bit appended by the serializer, which frame the sixteen data bits. The start bit is
always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the
serial stream.
The Serializer block accepts data from the DIN0-DIN15 parallel inputs. The TCLK signal latches the incoming
data on the rising edge. If the SYNC input is high for 6 TCLK cycles, the DS92LV16 does not latch data on the
DIN0-DIN15.
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The Serializer transmits the data and clock bits (16+2 bits) at 18 times the TCLK frequency. For example, if
TCLK is 60 MHz, the serial rate is 60 X 18 = 1080 Mbps. Since only 16 bits are from input data, the serial
'payload' rate is 16 times the TCLK frequency. For instance, if TCLK = 60 MHz, the payload data rate is 60 X 16
= 960 Mbps. TCLK is provided by the data source and must be in the range of 25 MHz to 80 MHz.
When the Deserializer channel synchronizes to the input from a Serializer, it drives its LOCK pin low and
synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to
generate multiple internal data strobes, and then drives the recovered clock on the RCLK pin. The RCLK is
synchronous to the data on the ROUT[0:15] pins. While LOCK is low, data on ROUT[0:15] is valid. Otherwise,
ROUT[0:15] is invalid.
ROUT[0:15], LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF total load) at a 80
MHz clock rate. This drive capacity allows bussing outputs of multiple Deserializers and multiple destination
ASIC inputs. REN controls TRI-STATE of the all outputs.
The Deserializer input pins are high impedance during Receiver Powerdown (RPWDN* low) and power-off (VCC
= 0V).
RESYNCHRONIZATION
Whenever the Deserializer loses lock, it will automatically try to resynchronize. For example, if the embedded
clock edge is not detected two times in succession, the PLL loses lock and the LOCK pin is driven high. The
Deserializer then enters the operating mode where it tries to lock to random a data stream. It looks for the
embedded clock edge, identifies it and then proceeds through the synchronization process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is low, the data is valid.
The system must monitor the LOCK pin to determine whether data on the ROUT is valid. Because there is a
short delay in the LOCK signals response to the PLL losing synchronization to the incoming data stream, the
system must determine the validity of data for the cycles before the LOCK signal goes high.
The user can choose to resynchronize to the random data stream or to force fast synchronization by pulsing the
Serializer SYNC pin. Since lock time varies due to data stream characteristics, we cannot possibly predict exact
lock time. The primary constraint on the "random" lock time is the initial phase relation between the incoming
data and the REFCLK when the Deserializer powers up. An advantage of using the SYNC pattern to force
synchronization is the ability for user to predict the delay for PLL to regain lock. This scheme is left up to the user
discretion. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync
request of the Serializer, which is the SYNC pin.
If a specific pattern is repetitive, the Deserializer’s PLL will not lock in order to prevent the Deserializer to lock to
the data pattern rather than the clock. We refer to such pattern as a repetitive multi-transition, RMT. This occurs
when more than one Low-High transition takes places in a clock cycle over multiple cycles. This occurs when
any bit, except DIN 15, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. The
internal circuitry accomplishes this by detecting more than one potential position for clocking bits. Upon
detection, the circuitry will prevent the LOCK output from becoming active until the RMT pattern changes. Once
the RMT pattern changes and the internal circuitry recognized the clock bits in the serial data stream, the PLL of
the Deserializer will lock, which will drive the LOCK output to low and the output data ROUT will become valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the Serializer and Deserializer will occupy while waiting for
initialization. You can also use TPWDN* and RPWDN* to reduce power when there are no pending data
transfers. The Deserializer enters Powerdown when RPWDN* is driven low. In Powerdown, the PLL stops and
the outputs go into TRI-STATE, which reduces supply current to the μA range.
To bring the Deserializer block out of the Powerdown state, the system drives RPWDN* high. When the
Deserializer exits Powerdown, it automatically enters the Initialization state. The system must then allow time for
Initialization before data transfer can begin.
The TPWDN* driven to a low condition forces the Serializer block into low power consumption where the supply
current is in the μA range. The Serializer PLL stops and the output goes into a TRI-STATE condition.
To bring the Serializer block out of the Powerdown state, the system drives TPWDN* high. When the Serializer
exits Powerdown, its PLL must lock the TCLK before it is ready for the Initialization state. The system must then
allow time for Initialization before data transfer can begin.
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LOOPBACK TEST OPERATION
The DS92LV16 includes two Loopback modes for testing the device functionality and the transmission line
continuity. Asserting the Line Loopback control signal connects the serial data input (RIN+/−) to the serial data
output (DO+/−) and to the parallel data output (ROUT[0:15]). The serial data goes through deserializer and
serializer blocks.
Asserting the Local Loopback control signal connects the parallel data input (DIN[0:15]) back to the parallel data
output (ROUT[0:15]). The connection route includes all the functional blocks of the SER/DES Pair. The serial
data output (DO+/−) is automatically disabled during the Local Loopback operating mode.
TRI-STATE
When the system drives the REN pin low, the Deserializer output enter TRI-STATE. This will TRI-STATE the
receiver output pins (ROUT[0:15]) and RCLK. When the system drives REN high, the Deserilaizer will return to
the previous state as long as all other control pins remain static (RPWDN*).
When the system drives the DEN pin low, the Serializer output enters TRI-STATE. This will TRI-STATE the
LVDS output. When the system drives the DEN signal high, the Serializer output will return to the previous state
as long as all other control and data input pins remain in the same condition as when the DEN was driven low.
APPLICATION INFORMATION
Using the DS92LV16
The DS92LV16 combines a Serializer and a Deserializer into a single chip that sends 16 bits of parallel TTL data
over a serial Bus LVDS link up to 1.28 Gbps. Serialization of the input data is accomplished using an onboard
PLL at the Serializer which embeds two clock bits with the data. The Deserializer uses a separate reference
clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data stream and
deserialize the data. The Deserializer monitors the incoming clock information to determine lock status and will
indicate loss of lock by raising the LOCK output.
Power Considerations
All CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the
constant current source nature of the LVDS outputs minimize the slope of the speed vs. ICC curve of CMOS
designs.
Powering Up the Deserializer
The REFCLK input can be running before the Deserializer is powered up and it must be running in order for the
Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the Deserializer
detects data transmission at its inputs and locks to the incoming stream.
Noise Margin
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic factors include:
•
Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise)
•
Media: ISI, VCM noise
•
Deserializer: VCC noise
For typical receiver noise margin, please see Figure 17.
Recovering from LOCK Loss
In the case where the Serializer loses lock during data transmission up to 5 cycles of data that was previously
received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that
invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been
lost it is possible that data was also lost during these cycles. When the Deserializer LOCK pin goes low, data
from at least the previous 5 cycles should be resent upon regaining lock.
Lock can be regained at the Deserializer by causing the Serializer to resend SYNC patterns as described above
or by random lock which can take more time depending upon the data patterns being received.
14
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Input Failsafe
In the event that the Deserializer is disconnected from the Serializer, the failsafe circuitry is designed to reject
certain amount of noise from being interpreted as data or clock. The outputs will be tri-stated and the Deserializer
will lose lock.
Hot Insertion
All the LVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), then the I/O pins. When removing, the I/O pins should be unplugged
first, then the VCC, then the Ground.
PCB Layout and Power System Considerations
Circuit board layout and stack-up for the BLVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high-frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitic, especially proven effective at high frequencies above
approx 50MHz, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals.
Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and
extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to
the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are
recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller
value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the
50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and
ground pin straight to the power and ground plane, with the bypass capacitors connected to the plane with via on
both ends of the capacitor. Connecting power or ground pin to an external bypass capacitor will increase the
inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. User must pay attention to the resonance frequency of these
external bypass capacitors, usually in the range of 20-30MHz range. To provide effective bypassing, very often,
multiple capacitors are used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two via from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate CMOS (TTL) swings away from the LVDS
lines to prevent coupling from the CMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms
are typically recommended for LVDS interconnect. The closely-coupled lines help to ensure that coupled noise
will appear as common-mode and thus is rejected by the receivers. Also the tight coupled lines will radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications termination should be located at
the load end. Nominal value is 100 Ohms to match the line's differential impedance. Place the resistor as close
to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver.
Additional general guidance can be found in the LVDS Owner's Manual - available in PDF format from the Texas
Instruments web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
Specific guidance for this device is provided next:
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DS92LV16
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
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DS92LV16 BLVDS SER/DES PAIR
General device specific guidance is given below. Exact guidance can not be given as it is dictated by other board
level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated
circuit power supply needs.
DVDD = Digital section power supply
These pins supply the digital portion of the device and also receiver output buffers. The TX DVDD is less critical.
The RX DVDD requires more bypass to power the outputs under synchronous switching conditions. The receiver
DVDD pins power 4 outputs from each DVDD pin. An estimate of local capacitance required indicates a minimum
of 22nF is required. This is calculated by taking 4 times the maximum short current (4 X 70 = 280mA) multiplying
by the rise time of the part (4ns) and dividing by the maximum allowed droop in VDD (assume 50mV) yields
22.4nF. Rounding up to a standard value, 0.1uF is selected for each DVDD pin.
PVDD = PLL section power supply
The PVDD pin supplies the PLL circuit. Note that the DS92LV16 has two separate PLLs and supply pins. The
PLL(s) require clean power for the minimization of Jitter. A supply noise frequency in the 300kHZ to 1MHz range
can cause increased output jitter. Certain power supplies may have switching frequencies or high harmonic
content in this range. If this is the case, filtering of this noise spectrum may be required. A notch filter response is
best to provide a stable VDD, suppression of the noise band, and good high-frequency response (clock
fundamental). This may be accomplished with a pie filter (CRC or CLC). If employed, a separate pie filter is
recommended for each PLL to minimize drop in potential due to the series resistance. The pie filter should be
located close to the PVDD power pin. Separate power planes for the PVDD pins is typically not required.
AVDD = LVDS section power supply
The AVDD pin supplies the LVDS portion of the circuit. The DS92LV16 has four AVDD pins. Due to the nature of
the design, current draw is not excessive on these pins. A 0.1uF capacitor is sufficient for these pins. If space is
available it 0.01uF may be used in parallel with the 0.1uF capacitor for additional high frequency filtering.
GROUNDs
The AGND pin should be connected to the signal common in the cable for the return path of any common-mode
current. Most of the LVDS current will be odd-mode and return within the interconnect pair. A small amount of
current may be even-mode due to coupled noise, and driver imbalances. This current should return via a low
impedance known path.
A solid ground plane is recommended for both DVDD, PVDD or AVDD. Using a split plane may have potential
problem of ground loops, or difference in ground potential at various ground pins of the device.
16
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PIN DIAGRAM
Figure 22. DS92LV16TVHG (Top View)
PIN DESCRIPTIONS
Pin #
(1)
Pin Name
I/O
1
RPWDN*
CMOS, I
RPWDN* = Low will put the Receiver in low power, stand-by, mode.
Note: The Receiver PLL will lose lock. (1)
2
REN
CMOS, I
REN = Low will disable the Receiver outputs. Receiver PLL remains
locked. (See LOCK pin description) (1)
3
CONFIG1
4
REFCLK
5, 10, 11, 15
AVDD
6,9,12,16
AGND
7
RIN+
Description
Configuration pin - strap or tie this pin to High with pull-up resistor. Noconnect or Low reserved for future use.
CMOS, I
Frequency reference clock input for the receiver.
Analog Voltage Supply
Analog Ground
LVDS, I
Receiver LVDS True Input
8
RIN-
LVDS, I
Receiver LVDS Inverting Input
13
DO+
LVDS, O
Transmitter LVDS True Output
Input defaults to "low" state when left open due to internal pull-device.
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DS92LV16
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS (continued)
Pin #
Pin Name
I/O
14
DO-
LVDS, O
Transmitter LVDS Inverting Output
17
TCLK
CMOS, I
Transmitter reference clock. Used to strobe data at the DIN Inputs and
to drive the transmitter PLL. See SERIALIZER TIMING
REQUIREMENTS FOR TCLK
18
CONFIG2
19
DEN
CMOS, I
DEN = Low will disable the Transmitter outputs. The transmitter PLL will
remain locked. (1)
20
SYNC
CMOS, I
SYNC = High will cause the transmitter to ignore the data inputs and
send SYNC patterns to provide a locking reference to receiver(s). See
Functional Description. (1)
DIN (0:15)
CMOS, I
Transmitter data inputs. (1)
21, 22, 23, 24, 25, 26, 27,
28, 33, 34, 35, 36, 37, 38,
39, 40
29,32
Description
Configuration pin - strap or tie this pin to High with pull-up resistor. Noconnect or Low reserved for future use.
PGND
PLL Ground.
30,31
PVDD
PLL Voltage supply.
41, 44, 51, 52, 59, 60, 61,
68, 80
DGND
Digital Ground.
42
43, 50, 53, 58, 62, 69
45, 46, 47, 48, 54, 55, 56,
57, 64, 65, 66, 67, 70, 71,
72, 73
(2)
18
TPWDN*
CMOS, I
DVDD
TPWDN* = Low will put the Transmitter in low power, stand-by mode.
Note: The transmitter PLL will lose lock. (2)
Digital Voltage Supplies.
ROUT (0:15)
CMOS, O
Receiver Outputs.
49
RCLK
CMOS, O
Recovered Clock. Parallel data rate clock recovered from embedded
clock. Used to strobe ROUT (0:15). LVCMOS Level output.
63
LOCK*
CMOS, O
LOCK* indicates the status of the receiver PLL. LOCK = H - receiver
PLL is unlocked, LOCK = L - receiver PLL is locked.
74,76
PGND
PLL Grounds.
75,77
PVDD
PLL Voltage Supplies.
78
LINE_LE
CMOS, I
LINE_LE = High enables the receiver loopback mode. Data received at
the RIN+/- inputs is fed back through the DO+/- outputs. (2)
79
LOCAL_LE
CMOS, I
LOCAL_LE = High enables the transmitter loopback mode. Date
received at the DIN inputs is fed back through the ROUT outputs. (2)
Input defaults to "low" state when left open due to internal pull-device.
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SNLS138H – JANUARY 2001 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision G (April 2013) to Revision H
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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19
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS92LV16TVHG
NRND
LQFP
PN
80
119
TBD
Call TI
Call TI
-40 to 85
DS92LV16TVHG
>B
DS92LV16TVHG/NOPB
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
DS92LV16TVHG
>B
DS92LV16TVHGX/NOPB
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
DS92LV16TVHG
>B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS92LV16TVHGX/NOPB
Package Package Pins
Type Drawing
LQFP
PN
80
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
14.65
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
14.65
2.15
24.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS92LV16TVHGX/NOPB
LQFP
PN
80
1000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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