Texas Instruments | 5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to FPD-Link II LVDS Converter (Rev. D) | Datasheet | Texas Instruments 5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to FPD-Link II LVDS Converter (Rev. D) Datasheet

Texas Instruments 5-43 MHz FPD-Link LVDS (3 Data   1 Clock) to FPD-Link II LVDS Converter (Rev. D) Datasheet
DS99R421
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SNLS264D – JUNE 2007 – REVISED APRIL 2013
5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DCBalanced) Converter
Check for Samples: DS99R421
FEATURES
DESCRIPTION
•
The DS99R421 converts a FPD-Link input with 4
non-DC Balanced LVDS (3 LVDS Data + LVDS
Clock) plus 3 over-sampled low speed control bits
into a single LVDS DC-balanced serial stream with
embedded clock information. This single serial stream
simplifies transferring the 24-bit bus over a single
differential pair of PCB traces and cable by
eliminating the skew problems between the 3 parallel
LVDS data inputs and LVDS clock paths. It saves
system cost by narrowing 4 LVDS pairs to 1 LVDS
pair that in turn reduce PCB layers, cable width,
connector size, and pins.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
5 MHz–43 MHz Embedded Clock & DCBalanced Data Transmission (21 Total LVDS
Data Bits Plus 3 Low Speed LVCMOS Data
Bits)
User Adjustable Pre-Emphasis Driving Ability
Through External Resistor on LVDS Outputs
and Capable to Drive up to 10 Meters Shielded
Twisted-Pair Cable
Supports AC-Coupling Data Transmission
100Ω Integrated Termination Resistor at LVDS
Input
Power-Down Control
Available @SPEED BIST to DS90UR124 to
Validate Link Integrity
All LVCMOS Inputs & Control Pins Have
Internal Pulldown
Schmitt Trigger Inputs on OS[2:0] to Minimize
Metastable Conditions
Outputs Tri-Stated Through DEN
On-Chip Filters for PLLs
Power Supply Range 3.3V ± 10%
Automotive Temperature Range −40°C to
+105°C
Greater Than 8kV ESD Tolerance
Meets ISO 10605 ESD and AEC-Q100
Compliance
The DS99R421 incorporates a single serialized LVDS
signal on the high-speed I/O. Embedded clock LVDS
provides a low power and low noise environment for
reliably transferring data over a serial transmission
path. By optimizing the converter output edge rate for
the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding is used to support
AC-Coupled interconnects.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS99R421
SNLS264D – JUNE 2007 – REVISED APRIL 2013
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Block Diagram
VODSEL
PRE
DEN
3
OS[2:0]
DC Balance Encoder
100:
RxIN1-
100:
RxIN1+
DeSerializer
RxIN0+
RxIN2-
100:
21 Bits
Parallel
Data
Parallel to Serial
(5 MHz to 43 MHz)
LVDS NON-DC Balanced
RxIN0-
DOUT+
DOUT-
RxIN2+
RxCLKINPLL
100:
RxCLKIN+
PWDNB
DS99R421
Standard 4 LVDS - to - 1 LVDS Tx ± Converter
Figure 1. Block Diagram
Application Overview
3
100:
100:
LVDS
DATA2
100:
LVDS
CLK
100:
RIN+
DOUTRINSTP
(Up to 10 meters)
DS90UR124
DOUT+
LVDS
DATA1
RT = 100:
GUI
(5 MHz to 43 MHz)
LVDS NON-DC Balanced
LVDS
DATA0
RT = 100:
OS[2:0]
DS99R421
100:
Differential
PCB Traces
Rx - DESERIALIZER
Figure 2. Typical Application Diagram
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
−0.3V to +4V
Supply Voltage (VDD)
LVCMOS Input Voltage
−0.3V to (VDD +0.3V)
LVCMOS Output Voltage
−0.3V to (VDD +0.3V)
LVDS Receiver Input Voltage
−0.3V to +3.9V
LVDS Driver Output Voltage
−0.3V to +3.9V
LVDS Output Short Circuit Duration
10 ms
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 4 seconds)
+260°C
Package De-rating: DS99R421 − 36L WQFN
Maximum Package Power Dissipation
Capacity
θJC
3.1 (2/4L (3)) °C/W
≥±8 kV
ISO10605
RD = 2 kΩ, CS = 150/330 pF
(2)
(3)
37.6 (4L (3)); 83.7 (2L (3))°C/W
HBM
ESD Rating
(1)
1/θJA °C/W above +25°C
θJA
DS99R421 meets ISO10605
Contact Discharge, DOUT±
±10 kV
Air Discharge, DOUT±
±25 kV
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
JEDEC
Recommended Operating Conditions
Min
Nom
Max
Supply Voltage (VDD)
3.0
3.3
3.6
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
Input Clock Rate, RxCLKIN±
5
Supply Noise (VDDp-p)
Receiver Input Range
0
Units
43
MHz
±100
mVP-P
VDD
V
Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
VDD
V
0.8
V
LVCMOS & SCHMITT-TRIGGER INPUT DC SPECIFICATIONS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
VIN = 0V or 3.6V
VTH+
High Level Input Voltage
VTH−
High Level Input Voltage
VH
Hysteresis Voltage
(1)
(2)
(3)
PWDNB, DEN, VODSEL,
BISTEN
2.0
GND
−0.9
−10
OS[2:0]
(Schmitt-triggered Inputs)
VTH+ – VTH−
−1.5
V
+10
µA
2.0
200
V
400
0.8
V
600
mV
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
+100
mV
LVDS DC SPECIFICATIONS
VTH
Differential Threshold High
Voltage
VTL
Differential Threshold Low
Voltage
|VID|
Differential Input Voltage
Swing
VCM
Common Mode Voltage
IIN
Input Current
VOD
Output Differential Voltage
(Figure 10)
VCM = 1.2V
LVDS differential Inputs:
RxIN0±, RxIN1±, RxIN2±,
RxCLKIN±
−100
mV
100
0.525
1.2
600
mV
VDD −
(VID/2)
mV
VIN = +2.4V,
VDD = 3.6V
−10
+10
µA
VIN = 0V,
VDD = 3.6V
-10
+10
µA
RT = 100Ω
VODSEL = L
LVDS differential Outputs:
DOUT±
RT = 100Ω
VODSEL = H
380
500
630
mV
650
900
1150
mV
10
50
mV
1.2
1.5
V
5
50
mV
ΔVOD
Output Differential Voltage
Unbalance
RT = 100Ω
VOS
Output Voltage Offset
RT = 100Ω
PRE = H (off)
ΔVOS
Output Voltage Offset
Difference
RT = 100Ω
PRE = H (off)
IOS
Output Short Circuit Current
DOUT± = 0V
VODSEL = L
PRE = H (off)
−2
−8
mA
DOUT± = 0V
VODSEL = H
PRE = H (off)
−7
−13
mA
PWDNB = 0V,
DOUT± = 0V OR VDD
(inputs not toggling)
−10
±1
+10
µA
90
105
130
Ω
95
130
mA
2
50
µA
Max
IOZ
TRI-STATE Output Current
RT
1.0
Internal Input Termination
Resistance
RxIN:
across RxIN(2:0)+ &
RxIN(2:0)−, and across
RxCLKIN+ & RxCLKIN−
CONVERTER SUPPLY CURRENT
IDD
Total Supply Current
(includes load current)
IDDTZ
RT = 100Ω
CHECKERBOARD pattern
PRE = 6 KΩ (Figure 3)
f = 43 MHz
Supply Current Power-down PWDNB = 0V
(inputs not toggling)
Receiver Input Timing Requirements
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
0.35T
0.57T
tRCIH
Receiver Clock Input High Time
Referenced to rising edge of RxCLKIN
tRCIL
Receiver Clock Input Low Time
Referenced to rising edge of RxCLKIN
4
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0.43T
Units
ns
0.65T
ns
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Receiver Input Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
RITOL-L
Receiver Input Tolerance Left
(Figure 7 Figure 8) (1) (2)
5 MHz–43 MHz
RITOL-R
Receiver Input Tolerance
Right
(Figure 7 Figure 8) (1) (2)
5 MHz–43 MHz
UI
Unit Interval
(1)
(1)
Typ
5 MHz–43 MHz
Max
Units
0.3
UI
0.3
UI
1/7th of
RxCLKIN
ns
UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.For the input, it is 1/7th the input clock
period. Example 43 MHz = 23.26 ns. 1/7th of this is 3.32 ns. This is 1 UI of the input at 43 MHz.For the output, it is 1/28th of the input
clock period. Example 43 MHz = 23.26 ns. 1/28th of this is 831 ps. This is 1 UI of the output at 43 MHz.
Receiver Input Tolerance is defined as the valid data sampling region at the receiver inputs. This margin takes into account the
transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window – RSPos). This
margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter.
(2)
Input Timing Requirements for OS[2:0]
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
FOS[2:0]
Parameter
Conditions
Maximum Frequency
Limitation of OS[2:0]
Pin/Freq.
Min
Typ
OS[2:0]
Max
Units
FRxCLKIN / 5
MHz
Input to Output Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
RCTCD
RxCLK IN to DOUT Delay
(Figure 5), (1)
5 MHz–43 MHz
PDD
Power Down Delay
5 MHz–43 MHz
(1)
Min
Typ
Max
Units
4T + 1.0
4T + 5.0
4T + 10.0
ns
1
µs
A Clock Unit Symbol (T) is defined as 1/ (Line rate of RxCLKIN).
Serializer Output Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
tLLHT
LVDS Low-to-High Transition Time
tLHLT
LVDS High-to-Low Transition Time
tPLT
PLL Lock Time
TxOUT_E_O
TxOUT_Eye_Opening (1)
UI
(1)
(2)
Unit Interval
Min
RT = 100Ω,
CL = 10 pF to GND
(Figure 4)
Typ
Max
Units
0.3
0.5
ns
0.3
0.5
ns
10
ms
5 MHz–43 MHz
(2)
(Figure 9)
(1)
5 MHz–43 MHz
(respect to ideal)
5 MHz–43 MHz
0.78
UI
1/28th of
DOUT
ns
UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.For the input, it is 1/7th the input clock
period. Example 43 MHz = 23.26 ns. 1/7th of this is 3.32 ns. This is 1 UI of the input at 43 MHz.For the output, it is 1/28th of the input
clock period. Example 43 MHz = 23.26 ns. 1/28th of this is 831 ps. This is 1 UI of the output at 43 MHz.
TxOUT_E_O is affected by pre-emphasis value.
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AC TIMING DIAGRAMS AND TEST CIRCUITS
RxCLKIN
(Differential)
Vdiff = 0V
Vdiff = 0V
Vdiff = 0V
Previous Cycle
RxIN0
0V
RxIN1
0V
RxIN2
0V
Next
Cycle
Current Cycle
Figure 3. LVDS Input Checkerboard Pattern
10 pF
DOUT+
Differential
Signal
100:
80%
80%
20%
20%
Vdiff = 0V
DOUT10 pF
tLLHT
tLHLT
Vdiff = (DOUT+) - (DOUT-)
RxIN
SYMBOL N
SYMBOL N+1
SYMBOL N+2
| |
Figure 4. Serializer LVDS Output Load and Transition Times
SYMBOL N+3
SYMBOL N+4
RCTCD
RxCLKIN
|
23
0
1
2
23
0
1
2
23
0
1
2
23
0
1
2
| |
2
SYMBOL N
| |
1
SYMBOL N-1
| |
0
SYMBOL N-2
| |
DOUT
SYMBOL N-3
| |
SYMBOL N-4
23
Figure 5. RxIN to DOUT Delay – RCTCD
6
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RxCLKIN
(Differential)
SNLS264D – JUNE 2007 – REVISED APRIL 2013
Vdiff = 0V
Vdiff = 0V
Previous Cycle
Vdiff = 0V
Next
Cycle
Current Cycle
RxIN0
R1-1
R0-1
G0
R5
R4
R3
R2
R1
R0
RxIN1
G2-1
G1-1
B1
B0
G5
G4
G3
G2
G1
RxIN2
B3-1
B2-1
DE
VSYNC
HSYNC
B5
B4
B3
B2
Figure 6. Receiver LVDS Input Mapping
RxCLKIN
(Differential)
Vdiff = 0V
Vdiff = 0V
Previous Cycle
Vdiff = 0V
Next
Cycle
Current Cycle
RxIN0
R1-1
R0-1
G0
R5
R4
R3
R2
R1
R0
RxIN1
G2-1
G1-1
B1
B0
G5
G4
G3
G2
G1
RxIN2
B3-1
B2-1
DE
VSYNC
HSYNC
B5
B4
B3
B2
RITOL1 min
RITOL1 max
RITOL0 min
RITOL0 max
RITOL6 min
RITOL6 max
RITOL5 min
RITOL5 max
RITOL4 min
RITOL4 max
RITOL3 min
RITOL3 max
RITOL2 min
RITOL2 max
Figure 7. Receiver RITOL Min and Max
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Sampling
Window
Ideal Bit Start
RITOL
(Left)
Ideal Bit Stop
RITOL
(Right)
Ideal Strobe Position
(1/2 UI)
(1 UI)
Figure 8. Receiver RITOL Left and Right
Ideal Data Bit
Beginning
DS99R421 Output
Eye Opening
Ideal Data Bit
End
Ideal Center Position (tBIT)/2
tBIT (1 UI)
Figure 9. Serializer Output Eye Opening
DOUT+
RT
VDD = (DOUT+) - (DOUT-)
DOUT-
Figure 10. Serializer VOD Diagram
8
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PIN DESCRIPTIONS
Pin #
Pin Name
I/O/PWR
Description
FPD-LINK LVDS RECEIVER INPUT PINS
28, 30, 32
RxIN[2:0]−
LVDS_I
LVDS Receiver inverted Data Inputs (−)
29, 31, 33
RxIN[2:0]+
LVDS_I
LVDS Receiver true Data Inputs (+)
34
RxCLKIN−
LVDS_I
LVDS Receiver inverted reference Clock Inputs.
Used to strobe data at the RxIN inputs and to drive the receiver PLL
35
RxCLKIN+
LVDS_I
LVDS Receiver true reference Clock Inputs.
Used to strobe data at the RxIN inputs and to drive the receiver PLL
LVCMOS_I
Over Sampled Receiver Data Inputs with Schmitt trigger
OVER SAMPLED INPUT PINS
3-1
OS[2:0]
CONTROL AND CONFIGURATION PINS
4
PWDNB
LVCMOS_I
Power Down Bar
PWDNB = H; Device is Enabled and ON
PWDNB = L; Device is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are
in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
15
DEN
LVCMOS_I
Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Serializer LVDS Driver DOUT (+/-)
Outputs are in TRI-STATE, PLL still operational and locked to TCLK.
10
PRE
LVCMOS_I
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor RPRE. Resistor
value determines pre-emphasis level. Recommended value RPRE ≥ 6 kΩ; Imax = [48 /
RPRE], RPREmin = 6 kΩ
See Applications Information section for more details.
18
VODSEL
LVCMOS_I
VOD Level Select
VODSEL = L; LVDS Driver Output is ±500 mV (RT = 100Ω)
VODSEL = H; LVDS Driver Output is ±900 mV (RT = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger
VOD is required, set this pin HIGH.
See Applications Information section for more details.
36, 24, 21, 9
RESRVD
LVCMOS_I/O
Reserved. This pin MUST be tied LOW.
LVCMOS_I
Control Pin for BIST Mode Enable (ACTIVE H)
BISTEN = L; Default at Low, Normal Mode
BISTEN = H; BIST mode active
Note: Sequence order for proper function of BIST mode:
1) DS99R421 BISTEN = H.
2) DS99R421 PLL must be locked (10 ms).
3) DS90UR124 PLL must be locked.
4) Select BISTM error reporting mode on DS90UR124.
5) DS90UR124 switch BISTEN from L to H.
BIST MODE PINS
27
BISTEN
LVDS SERIALIZER OUTPUT PINS
14
DOUT+
LVDS_O
Serializer LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the DOUT+ pin. The interconnect
should be AC Coupled to this pin with a 100 nF capacitor.
13
DOUT−
LVDS_O
Serializer LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the DOUT-pin. The interconnect
should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
5
VDDP1
VDD
Analog Power supply, PLL POWER
6
VSSP1
GND
Analog Ground, PLL GROUND
7
VDDP0
VDD
Analog Power supply, VCO POWER
8
VSSP0
GND
Analog Ground, VCO GROUND
11
VDDDR
VDD
Analog Power supply, LVDS OUTPUT POWER
12
VSSDR
GND
Analog Ground, LVDS OUTPUT GROUND
17
VDDSER
VDD
Digital Power supply, SERIALIZER POWER
16
VSSSER
GND
Digital Ground, SERIALIZER GROUND
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PIN DESCRIPTIONS (continued)
Pin #
Pin Name
I/O/PWR
Description
19
VDDD
VDD
Digital Power supply, LOGIC POWER
20
VSSD
GND
Digital Ground, LOGIC GROUND
22
VDDDES
VDD
Digital Power supply, RECEIVER POWER
23
VSSDES
GND
Digital Ground, RECEIVER GROUND
25
VDDIN
VDD
Analog Power supply, LVDS INPUT POWER
26
VSSIN
GND
Analog Ground, LVDS INPUT GROUND
BISTEN
VSSIN
VDDIN
RESRVD
VSSDES
VDDDES
RESRVD
VSSD
VDDD
27
26
25
24
23
22
21
20
19
PIN DIAGRAM — DS99R421
RxIN0-
28
18
VODSEL
RxIN0+
29
17
VDDSER
RxIN1-
30
16
VSSSER
RxIN1+
31
DS99R421
15
DEN
RxIN2-
32
36 pin WQFN
(No Pullback)
14
DOUT+
6
7
8
9
VSSP1
VDDP0
VSSP0
RESRVD
PRE
5
10
VDDP1
36
4
VDDDR
RESRVD
PWDNB
11
3
35
OS2
VSSDR
RxCLKIN+
2
DOUT-
12
1
13
34
OS1
33
OS0
RxIN2+
RxCLKIN-
Figure 11. TOP VIEW
10
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FUNCTIONAL DESCRIPTION
The DS99R421 is a Video Interface converter. It converts an FPD-Link interface (3 LVDS data channels + 1
LVDS Clock, e.g. DS90C365A or equivalent) plus up to three (3) LVCMOS additional signals into a single highspeed LVDS serial Interface (see Figure 13).
The 21 bits of data from the FPD-Link Interface are serialized along with the 3 additional over-sampled bits
(OS[2:0]) into a randomized, scrambled and DC Balanced data stream to support AC coupling and to enhance
the signal eye opening. Four (4) additional overhead bits are sent per clock which provides the embedded clock
and serial link control information. The embedded clock LVDS serial stream has an effective data throughput of
120 Mbps (5MHz X 24) to 1.03 Gbps (43MHz X 24). The DS99R421 Line Driver is designed to transmit data up
to 10 meters over shielded twisted pair (STP) at signaling rates up to 1.2Gbps (43MHz X 28).
The DS90UR124 receiver converts the embedded clock LVDS stream back into a 24-bit wide LVCMOS parallel
bus and the recovered low-speed clock.
Note: The DS90C124 is not compatible with the DS99R421.
LINK START UP
The start up of the DS99R421 involves only one PLL Lock time. The FPD-Link Receiver side must lock to its
incoming LVDS RxCLKIN. The Serializer side then extracts its reference clock from the incoming LVDS clock. At
the far end of the link, the Deserializer (DS90UR124) also needs to detect the LVDS signals and lock to the
incoming serial stream, drives the LOCK pin HIGH, before outputting valid data. Note that when using a Bus
Converter (FPD-Link to Serial) additional time is required in the start up to account for the additional PLLs in the
path.
TYPICAL START UP SEQUENCE
1. FPD-Link Stream is applied to the DS99R421 inputs.
2. With power applied and the DS99R421 enabled, it will lock to the incoming FPD-Link clock. Until the
DS99R421 is ready, it will hold its outputs in TRI-STATE. Once the locking is complete, valid serial payloads
are sent across the link to the DES (DS90UR124).
3. With power applied and the device enabled, the DS90UR124 will lock to the incoming serial stream. Until the
DS90UR124 is locked, outputs are in TRI-STATE and its LOCK output pin is held Low. After Lock, the
DS90UR124 outputs are active and LOCK is HIGH.
DATA TRANSFER
After the link start up, the DS99R421 provides a streaming video interface. For each Pixel Clock (PCLK) received
from the FPD-Link Interface 21 bits of information are recovered along with the PCLK. The 21 bits of information
include the 18-bits of RGB information and the three video control signals (HS, VS and DE). The over-sample
control bits are also sampled in this PCLK domain and appended to the 21 bits of information for a 24-bit total
payload. The Serializer side now takes this data and performs four operations to it. First the data is randomized,
second the data is scrambled, third the data is balanced, and finally the serial link control and clock embedding is
done. The Serializer transmits 28 bits of information per payload to the Deserializer per PCLK. See DS90UR241
datasheet for additional information on the Serializer’s description and operation.
The chipset supports PCLK frequency ranges of 5 MHz to 43 MHz. At the 43MHz PCLK rate, 28 bits are sent
across the serial link at 1.2Gbps. The link is very efficient, sending 25 bits of information (18 RGB, 3 control, 3
over-sample control, and PCLK) with 28 serial bits. This yields 89% efficiency.
DS99R421 LINE DRIVER
The DS99R421 output (DOUT±) is used to drive a point-to-point connection as shown in Figure 14. The Line
driver transmits data when the data enable pin (DEN) is HIGH, the power down bar (PWDNB) is HIGH, and the
device is locked to the incoming FPD-Link stream. If the DEN is set LOW, the device remains locked, but the
driver outputs are placed in TRI-STATE. This maybe used to provide a fast start up since a lock time is not
required.
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PRE-EMPHASIS
The DS99R421 features a Pre-Emphasis function used to compensate for extra long or lossy transmission
media. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output
current during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media.
To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to Vss in order to set
the additional current level. Options include:
Normal Output (no pre-emphasis) – Leave the PRE pin open
Enhanced Output (pre-emphasis enabled) – connect a resistor on the PRE pin to Vss. Values of the PRE
Resistor should be between 6K Ohm and 100M Ohm. Values less than 6K Ohm should not be used. The amount
of Pre-Emphasis for a given media will depend on the transmission distance and Fmax of the application. In
general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in
excessive noise, crosstalk, reduced Fmax, and increased power dissipation. For shorter cables or distances, PreEmphasis is typically not be required. Signal quality measurements should be made at the end of the application
cable to confirm the proper amount of Pre-Emphasis for the specific application.
The Pre-Emphasis circuit increases the drive current to I = 48 / (Rpre). For example if Rpre = 15K Ohm, then the
Pre-Emphasis current is increased by an additional 3.2 mA.
The duration of the current is controlled to precisely one bit by another circuit. If more than one bit value is
repeated in the next cycle(s), the next bit(s) is “de-emphasized”; Pre-Emphasis is turned off (back to the normal
output current level, hence output level is also reduced). This is done to reduce power, and to reduce ISI (InterSymbol Interference).
VOD SELECT
The Serializer Line Driver Differential Output Voltage (VOD) magnitude is selectable. Two levels are provided
and are determined by the state of the VODSEL pin. When this pin is LOW, normal output levels are obtained.
For most application set the VODSEL pin LOW. When this pin is HIGH, the output current is increased to
increase the VOD level. Use this setting only for extra long cable or high-loss interconnects.
OVER-SAMPLED BITS – OS[2:0]
Up to three additional signals maybe sent across the serial link per PCLK. The over-sampled bits are restricted to
be low speed signals and should be less than 1/5 of the frequency of the PCLK. The DS99R421 OS[2:0]
LVCMOS Inputs have wide hysteresis to help prevent glitches. Signals should convey level information only, as
pulse width distortion will occur by the over sampling technique and location of the sampling clock. The three
over sampled bits are mapped to DS90UR124 bits as: OS0 = bit 21, OS1 = bit 22, and OS2 = bit 23. If the OS
bits are not required, internal pull-down will bias the input to a LOW.
COLOR MAPPING
Color mapping is application specific. It is very important to properly match the Pixel bit to the correct data
channel on the DS90UR124 to properly recover the color and control information. See Figure 13. In this example,
the G0 color bit is placed in the RxIN0 channel and is the first bit. The Serializer in the DS99R421 will place this
bit as bit number 6. Thus G0 will be recovered by the DS90UR124 on bit 6. The three over sampled bits are
mapped to DS90UR124 bits as: OS0 = bit 21, OS1 = bit 22, and OS2 = bit 23.
POWERDOWN (SLEEP) MODE
The Powerdown state is a low power sleep mode that the DS99R421 and DS90UR124 may use to reduce power
when no data is being transferred. The PWDNB on the DS99R421 and RPWDNB on the DS90UR124 are used
to set each device into power down mode, which reduces supply current to the µA range. The DS99R421 enters
powerdown when the PWDNB pin is driven LOW. In powerdown, the PLL stops and the outputs go into TRISTATE, disabling load current and reducing current supply. To powerup, the DS99R421, PWDNB must be driven
HIGH. When the DS99R421 exits powerdown, its PLL must lock to RxCLKIN before it is ready for the
initialization state. The system must then allow time for initialization before data transfer can begin.
12
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SERIAL INTERFACE
The serial link between the DS99R421 and the DS90UR124 is intended for a balanced 100 Ohm interconnect.
The link is expected to be terminated at both ends with 100 Ohms and AC coupled.
To establish a source termination and the correct levels, a Driver side termination is required. This is typically
located close to the device pins and is 100 Ohm resistor connected across the driver outputs.
The AC coupling capacitors should be place close to the 100 Ohm termination resistor at both ends of the
interface. For the high-speed LVDS transmission, small footprint packages should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. NPO class 1 or X7R
class 2 type capacitors are recommended. 50 WVDC should be the minimum used for best system-level ESD
performance. The most common used capacitor value for the interface is 100 nF (0.1 uF) capacitor.
The DS90UR124 input stage is designed for AC-coupling by providing a built-in AC bias network which sets the
internal VCM to +1.8V. Therefore multiple termination options are possible.
Receiver Termination Option 1
A single 100 Ohm termination resistor is placed across the RIN± pins (see Figure 14). This provides the signal
termination at the Receiver inputs. Other options may be used to increase noise tolerance.
Receiver Termination Option 2
For additional EMI tolerance, two 50 Ohm resistors may be used in place of the single 100 Ohm resistor. A small
capacitor is tied from the center point of the 50 Ohm resistors to ground (see Figure 16). This provides a highfrequency low-impedance path for noise suppression. Value is not critical, 4.7nF maybe used with general
applications.
Receiver Termination Option 3
For high noise environments an additional voltage divider network may be connected to the center point. This
has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the
range of 100Ω-1KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.8V. For
example (see Figure 17): VDD=3.3V, Rpullup=1KΩ, Rpulldown=1.2KΩ; or Rpullup=100Ω, Rpulldown=120Ω
(strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression.
FPD LINK INTERFACE
The FPD-Link Interface supports a 3 Data + Clock (21 bit) interface. The interconnect should employ a 100 Ohm
differential pair, as termination is provided internal to the DS99R421. Note that color mapping is extremely
important to review. Color placement of the bits on the FPD-Link Interface will determine which outputs they will
be recovered on. The DS99R421 is expected to reside on the same board as the FPD-Link Serializer (e.g.
DS90C365A or GUI with Integrated FPD-Link Serializer). The DS99R421 supports a limited common mode
range of 525mV to (VDD – VID/2). Typically this is wide enough to support short interconnects.
@SPEED-BIST (BUILT IN SELF TEST)
The DS99R421/ DS90UR124 serial link is equipped with a built-in self-test (BIST) capability to support both
system manufacturing and field diagnostics.
BIST mode is intended to check the entire high-speed serial link at full link-speed, without the use of specialized
and expensive test equipment. This feature provides a simple method for a system host to perform diagnostic
testing of both DS99R421 and DS90UR124. The BIST function is easily configured through the 2 control pins
(BISTEN and BISTM) on the DS90UR124 and one control pin (BISTEN) of the DS99R421. When the BIST mode
is activated, the DS99R421 has the ability to transfer an internally generated PRBS data pattern. This pattern
traverses across interconnecting links to the DS90UR124. The DS90UR124 includes an on-chip PRBS pattern
verification circuit that checks the data pattern for bit errors and reports any errors on the data output pins on the
DS90UR124.
The @SPEED-BIST feature uses 2 control pins (BISTEN and BISTM) on the DS90UR124 Deserializer. The
BISTEN and BISTM pins together determine the functions of the BIST mode. The BISTEN signal (HIGH)
activates the test feature on the DS90UR124. After the BIST mode is enabled on the DS90UR124, toggle the
BISTEN pin HIGH on the DS99R421 for the DS90UR124 Deserializer to start accepting data. An input clock
signal (RxCLKIN) for the DS99R421 must also be applied during the entire BIST operation. Data on RxIN[2:0]
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and OS[2:0] are ignored during operation of the BIST. The BISTM pin on the DS90UR124 selects the error
reporting status mode of the BIST function. When BIST is configured in the error status mode (BISTM = LOW),
each of the ROUT[23:0] outputs of the DS90UR124 will correspond to bit errors on a cycle-by-cycle basis. The
result of bit mismatches are indicated on the respective parallel inputs on the ROUT[23:0] data output pins. In the
BIST error count accumulator mode (BISTM = HIGH), an 8-bit counter on ROUT[7:0] is used to represent the
number of errors detected (0 to 255 max). The successful completion of the BIST test is reported on the PASS
pin on the DS90UR124 Deserializer. The DS90UR124 Deserializer's PLL must first be locked to ensure the
PASS status is valid. The PASS status pin will stay LOW and then transition to HIGH once a BER of 1x10-9 is
achieved across the transmission link.
14
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APPLICATIONS INFORMATION
USING THE DS99R421 AND DS90UR124
The DS99R421 allows a FPD-Link based bus to connect to a single-channel serial LVDS interface in a Display
using the latest generation LVDS Deserializer (DS90UR124). This allows for existing hosts with FPD-Link
interfaces to be further serialized into a single pair and connect with the current generation Display Deserializer.
Systems benefit by the smaller interconnect (reduced pins, less size, lower cost).
DISPLAY APPLICATION
18-bit color depth (RGB666) and up to 1280 X 480 display formats can be supported. In a RGB666 configuration
18 color bits (R[5:0], G [5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) along with three
low speed spare bits OS[2:0] are supported across the serial link with PCLK rates from 5 to 43MHz.
TYPICAL APPLICATION CONNECTION
Figure 15 shows a typical connection to the DS99R421.
The 4 pairs of FPD-Link LVDS interface are the input interface along with the optional over-sampled control
signals. Termination of the LVDS signals is provided internally by the DS99R421 device.
The single channel LVDS serial output requires an external termination and also AC coupling capacitors.
Configuration pins for the typical application are shown:
• DEN – tie HIGH if unused.
• PWDNB – Sleep / Enable Control Input – Connect to host or tie HIGH
• BISTEN – tie LOW if not used, or connect or host
• VODSEL – tie LOW for normal VOD magnitude (application dependant)
• PRE – Leave open if not required (have a R pad option on PCB)
• RESRVD – tie LOW (4 pins)
There are 4 power rails for the device. These may be bussed together on a common 3.3V plane. At a minimum,
four 0.1uF capacitors should be used for local bypassing.
With the above configuration a FPD-Link interface along with three additional low-speed signals are converted to
a single serial LVDS channel.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with vias on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
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Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at
both ends of the devices. Nominal value is 100 Ohms to match the line’s differential impedance. Place the
resistor as close to the transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting
stub between the termination resistor and device.
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in separation
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
Functional Overview
RxCLKIN
(Differential)
Vdiff = 0V
Vdiff = 0V
Previous Cycle
Vdiff = 0V
Next
Cycle
Current Cycle
RxIN0
R1-1
R0-1
G0
(bit 6)
R5
(bit5)
R4
(bit4)
R3
(bit3)
R2
(bit2)
R1
(bit1)
R0
(bit0)
RxIN1
G2-1
G1-1
B1
(bit13)
B0
(bit12)
G5
(bit11)
G4
(bit10)
G3
(bit9)
G2
(bit8)
G1
(bit7)
RxIN2
B3-1
B2-1
DE
(bit20)
VSYNC
(bit19)
HSYNC
(bit18)
B5
(bit17)
B4
(bit16)
B3
(bit15)
B2
(bit14)
Figure 12. FPD-Link LVDS Input Mapping (3 LVDS Data + 1 LVDS Clock)
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3
(5 MHz to 43 MHz)
LVDS NON-DC Balanced
OS[2:0]
LVDS
DATA0
100:
LVDS
DATA1
100:
DOUT+
100:
LVDS
CLK
100:
RT = 100:
DOUTLVDS
DATA2
bit16
bit17
bit18
bit19
bit20
bit21
bit22
bit23
B5
HSYNC
VSYNC
DE
OS0
OS1
OS2
1 CLK cycle
CLK0
bit15
bit11
G5
B3
bit10
G4
B4
bit9
G3
bit14
bit8
G2
bit13
bit7
G1
B1
bit6
G0
B2
bit5
R5
bit12
bit4
R4
B0
bit3
DCB
bit2
R3
Previous
Cycle
DCA
bit1
R1
R2
R0
CLK1
bit0
DS99R421
Next
Cycle
* Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC
Balanced
Single Serialized LVDS Bitstream*
Figure 13. LVDS Data Mapping Diagram
DOUT+
DS99R421
100 nF RIN+
100 nF
100:
DOUT-
100:
DS90UR124
100 nF RIN-
100 nF
Figure 14. AC Coupled Application
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DS99R421
RxIN0100:
VDDIN
100:
RxIN0+
RxIN1Serial
LVDS
Interface
100:
RxIN1+
RxIN2-
VDDDES
VDDD
VDDSER
3.3V
C1
C5
C2
C6
C3
C7
100:
RxIN2+
RxCLKINVDDDR
RxCLKIN+
LVCMOS
Parallel
Interface
OS0
OS1
OS2
GPOs if
used, or tie
High (ON)
DEN
PWDNB
GPOs if
used, or tie
Low (OFF)
BISTEN
C1 to C4 = 0.1 PF
C5 to C8 = 0.01 PF
C9, C10 = 100 nF, 50WVDC, NPO
or X7R
R1 = 100:
VDDP0
VDDP1
C4
C8
C9
DOUT+
Serial
LVDS
Interface
R1
VODSEL = L (350 mV)
RESRVD = L
PRE = open (OFF) or R2 > 6 k: (ON)
(cable specific)
DOUTC10
VODSEL
RESRVD(4)
PRE
VSSIN
VSSDES
VSSD
VSSSER
VSSDR
VSSP0
VSSP1
R2
Figure 15. DS99R421 Typical Application Connection
0.1 PF
0.1 PF
RIN+
50:
DS99R421
DS90UR124
100:
4.7 nF
50:
RIN0.1 PF
0.1 PF
Figure 16. Receiver Termination Option 2
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VDD
0.1 PF
0.1 PF
RIN+
50:
RPU
DS99R421
DS90UR124
100:
RPD
4.7 nF
50:
RIN-
0.1 PF
0.1 PF
Figure 17. Receiver Termination Option 3
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
20
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS99R421ISQ/NOPB
NRND
WQFN
NJK
36
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
99R421I
DS99R421QSQ/NOPB
ACTIVE
WQFN
NJK
36
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
99R421Q
DS99R421QSQX/NOPB
ACTIVE
WQFN
NJK
36
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
99R421Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS99R421, DS99R421-Q1 :
• Catalog: DS99R421
• Automotive: DS99R421-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DS99R421ISQ/NOPB
WQFN
NJK
36
DS99R421QSQ/NOPB
WQFN
NJK
DS99R421QSQX/NOPB
WQFN
NJK
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
250
178.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
36
250
178.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
36
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS99R421ISQ/NOPB
WQFN
NJK
36
250
210.0
185.0
35.0
DS99R421QSQ/NOPB
WQFN
NJK
36
250
210.0
185.0
35.0
DS99R421QSQX/NOPB
WQFN
NJK
36
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
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