Texas Instruments | DS90UR908Q 5-65 MHz 24-bit Color FPD-Link II to FPD-Link Conv (Rev. H) | Datasheet | Texas Instruments DS90UR908Q 5-65 MHz 24-bit Color FPD-Link II to FPD-Link Conv (Rev. H) Datasheet

Texas Instruments DS90UR908Q 5-65 MHz 24-bit Color FPD-Link II to FPD-Link Conv (Rev. H) Datasheet
DS90UR908Q
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SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
DS90UR908Q 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter
Check for Samples: DS90UR908Q
FEATURES
DESCRIPTION
•
The DS90UR908Q converts FPD-Link II to FPD Link.
It translates a high-speed serialized interface with an
embedded clock over a single pair (FPD-Link II) to
four LVDS data/control streams and one LVDS clock
pair (FPD-Link). This serial bus scheme greatly eases
system design by eliminating skew problems between
clock and data, reduces the number of connector
pins, reduces the interconnect size, weight, and cost,
and overall eases PCB layout. In addition, internal
DC balanced decoding is used to support AC-coupled
interconnects.
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•
•
•
•
•
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•
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5 – 65 MHz Support (140 Mbps to 1.82 Gbps
Serial Link)
5-Channel (4 data + 1 clock) FPD-Link Driver
Outputs
AC Coupled STP Interconnect up to 10 Meters
in Length
Integrated Input Termination
@ Speed link BIST Mode and Reporting Pin
Optional I2C Compatible Serial Control Bus
RGB888 + VS, HS, DE Support
Power Down Mode Minimizes Power
Dissipation
FAST Random Data Lock; No Reference Clock
Required
Adjustable Input Receive Equalization
LOCK (Real Time Link Status) Reporting Pin
Low EMI FPD-Link Output
SSCG Option for Lower EMI
1.8V or 3.3V Compatible I/O Interface
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
>8kV HBM ESD Tolerance
Backward Compatible Mode For Operation
with Older Generation Devices
APPLICATIONS
•
•
Automotive Display for Navigation
Automotive Display for Entertainment
The DS90UR908Q converter recovers the data
(RGB) and control signals and extracts the clock from
a serial stream (FPD-Link II). It is able to lock to the
incoming data stream without the use of a training
sequence or special SYNC patterns and does not
require a reference clock. A link status (LOCK) output
signal is provided.
Adjustable input equalization of the serial input
stream provides compensation for transmission
medium losses of the cable and reduces the mediuminduced deterministic jitter. EMI is minimized by the
use of low voltage differential signaling, output
voltage level select feature, and additional output
spread spectrum generation.
With fewer wires to the physical interface of the
display, FPD-Link output with LVDS technology is
ideal for high speed, low power and low EMI data
transfer.
The DS90UR908Q is offered in a 48-pin WQFN
package and is specified over the automotive AECQ100 grade 2 temperature range of -40˚C to +105˚C.
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2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
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Applications Diagram
FPD-Link
FPD-Link II
HOST
Graphics
Processor
RGB Style Display Interface
VDDIO
(1.8V or 3.3V)
VDDIO
1.8V 3.3V (1.8V or 3.3V)
1.8V
RxIN3+/-
TxOUT3+/-
High-Speed Serial Link
1 Pair/AC Coupled
RxIN2+/-
TxOUT2+/-
DOUT+
RxIN1+/RxIN0+/-
RIN+
DOUT-
TxOUT1+/TxOUT0+/-
RIN100 ohm STP Cable
RxCLKIN+/-
DS90UR907Q
Converter
PDB
CMF
BISTEN
VODSEL
De-Emph
MAPSEL
CONFIG[1:0]
SCL
SDA
ID[x]
Optional
FPD-Link
SSC[2:0]
LFMODE
CONFIG[1:0]
MAPSEL
DS90UR908Q
Converter
TxCLKOUT+/-
LOCK
PASS
PDB
BISTEN
OEN
OSSEL
VODSEL
SCL
SDA
ID[x]
Optional
RGB Display
QVGA to XGA
24-bit Color Depth
LFMODE
OSS_SEL
MAPSEL
VODSEL
GND
VDDL
OEN
BISTEN
PASS/EQ
LOCK
GND
VDDIO
36
35
34
33
32
31
30
29
28
27
26
25
Pin Diagram
RES
37
24
TxOUT0-
VDDA
38
23
TxOUT0+
GND
39
22
TxOUT1-
RIN+
40
21
TxOUT1+
RIN-
41
20
TxOUT2-
CMF
42
19
TxOUT2+
VDDA
43
18
TxCLKOUT-
DS90UR908Q
TOP VIEW
DAP = GND
2
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11
12
CONFIG[1]
ID[x]
10
VDDTX
CONFIG[0]
13
9
48
GND
GND
8
GND
VDDP
14
7
47
SSC[2]
VDDSC
6
TxOUT3+
VDDL
15
5
46
SCL
VDDSC
4
TxOUT3-
SDA
16
3
45
SSC[1]
GND
2
TxCLKOUT+
SSC[0]
17
1
44
PDB
GND
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PIN DESCRIPTIONS (1)
Pin Name
Pin #
I/O, Type
Description
FPD-Link II Input Interface
RIN+
40
I, LVDS
True input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
RIN-
41
I, LVDS
Inverting input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
CMF
42
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
FPD-Link Output Interface
TxOUT[3:0]+
15,19, 21,
23
O, LVDS
True LVDS Data Output
TxOUT[3:0]-
16,20, 22,
24
O, LVDS
Inverting LVDS Data Output
TxCLKOUT+
17
O, LVDS
True LVDS Clock Output
TxCLKOUT-
18
O, LVDS
Inverting LVDS Clock Output
O, LVMOS
LOCK Status Output
LOCK = 1, PLL is locked, output states determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN, Table 3
May be used as a Link Status or to flag when the Video Data is active (ON/OFF).
LVCMOS Outputs
LOCK
27
Control and Configuration
PDB
1
I, LVCMOS
w/ pull-down
Power Down Mode Input
PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down, the outputs are TRI-STATE. Control registers are
RESET.
VODSEL
33
I, LVCMOS
w/ pull-down
FPD-Link Output Voltage Select, Table 4
VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ)
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
OEN
30
I, LVCMOS
w/ pull-down
Output Enable Input, Table 3
OSS_SEL
35
I, LVCMOS
w/ pull-down
Output Sleep State Select Input, Table 3
LFMODE
36
I, LVCMOS
w/ pull-down
Low Frequency Mode — Pin or Register Control
LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20-65 MHz)
MAPSEL
34
I, LVCMOS
w/ pull-down
FPD-Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on TxOUT3+/-, Figure 16
MAPSEL = 0, LSB on TxOUT3+/-, Figure 15
CONFIG[1:0]
11,10
I, LVCMOS
w/ pull-down
Operating Modes — Pin or Register Control
Determine the device operating mode and interfacing device, Table 1
CONFIG[1:0] = 00: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter
ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR241 or DS99R421
CONFIG[1:0] = 11: Interfacing to DS90C241
SSC[2:0]
7, 3, 2
I, LVCMOS
w/ pull-down
Spread Spectrum Clock Generation (SSCG) Range Select, See Table 5 and Table 6
RES
37
I, LVCMOS
w/ pull-down
Reserved
Tie Low
Control and Configuration — STRAP PIN
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon powerup and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket.
EQ
(1)
28 [PASS]
STRAP
I, LVCMOS
w/ pull-down
EQ Gain Control of FPD-Link II Input
EQ = 1, EQ gain is enabled (~13 dB)
EQ = 0, EQ gain is disabled (~1.625 dB)
1 = High, 0 = Low
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PIN DESCRIPTIONS(1) (continued)
Pin Name
Pin #
I/O, Type
Description
Optional BIST Mode
BISTEN
29
I, LVCMOS
w/ pull-down
BIST Enable Input – Optional
BISTEN = 1, BIST Mode is enabled.
BISTEN = 0, normal mode.
PASS
28
O, LVCMOS
PASS Output (BIST Mode) – Optional
PASS = 1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control Interface
SCL
5
I, LVCMOS
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO.
SDA
4
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain
SDA requires an external pull-up resistor to VDDIO.
ID[x]
12
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail, Table 7
Power and Ground
VDDL
6, 31
Power
Logic Power, 1.8 V ±5%
VDDA
38, 43
Power
Analog Power, 1.8 V ±5%
VDDP
8
Power
PLL Power, 1.8 V ±5%
VDDSC
46, 47
Power
SSC Generator Power, 1.8 V ±5%
VDDTX
13
Power
FPD-Link Power, 3.3 V ±10%
VDDIO
25
Power
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND
9, 14, 26,
32, 39, 44,
45, 48
Ground
Ground
DAP
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
Block Diagram
DS90UR908Q ± CONVERTER
SSCG
RINEQ
Serializer
RIN+
TxOUT[3]
DC Balance Decoder
Serial to Parallel
CMF
SSC[2:0]
OEN
VODSEL
TxOUT[2]
TxOUT[1]
TxOUT[0]
TxCLKOUT
Error
Detector
PDB
SCL
SCA
ID[x]
BISTEN
OSS_SEL
LFMODE
Timing and
Control
PLL
PASS
LOCK
Figure 1. FPD-Link II to FPD-Link Convertor
4
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage – VDDn (1.8V)
−0.3V to +2.5V
Supply Voltage – VDDTX (3.3V)
−0.3V to +4.0V
Supply Voltage – VDDIO
−0.3V to +4.0V
−0.3V to +(VDDIO + 0.3V)
LVCMOS I/O Voltage
−0.3V to (VDD + 0.3V)
Receiver Input Voltage
−0.3V to (VDDTX + 0.3V)
LVDS Output Voltage
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
48L WQFN Package
Maximum Power Dissipation Capacity at 25°C
1/ θJA°C/W
Derate about 25°C
θJA
27.7 °C/W
θJC
3.0 °C/W
ESD Rating (IEC, powered-up only), RD = 330Ω, CS = 150pFs
≥±15 kV
Air Discharge (RIN+, RIN−)
≥±8 kV
Contact Discharge (RIN+, RIN−)
ESD Rating (ISO10605), RD = 330Ω, CS = 150/330pF
ESD Rating (ISO10605), RD = 2kΩ, CS = 150/330pF
≥±15 kV
Air Discharge (RIN+, RIN−)
Contact Discharge (RIN+, RIN−)
≥±8 kV
ESD Rating (HBM)
≥±8 kV
ESD Rating (HBM)
≥±8 kV
ESD Rating (CDM)
≥±1.25 kV
(1)
(2)
(3)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
For soldering specifications see product folder at www.ti.com and SNOA549
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
Nom
Max
Units
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO) OR
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
3.0
3.3
3.6
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
TxCLKOUT Frequency
5
Supply Noise (1)
(1)
65
MHz
100
mVP-P
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
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DC Electrical Characteristics (1) (2) (3) (4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
VODSEL = L
100
250
400
mV
VODSEL = H
200
450
600
FPD-Link LVDS Output
|VOD|
Differential Output Voltage
VODp-p
Differential Output Voltage
A-B
ΔVOD
Output Voltage Unbalance
RL = 100Ω
Figure 8
VOS
Offset Voltage
ΔVOS
Offset Voltage Unbalance
IOS
Output Short Circuit Current
Vout = GND
IOZ
Output TRI-STATE® Current
OEN = GND,
Vout =VDDTX, or GND
VODSEL = L
500
VODSEL = H
900
VODSEL = H TxCLKOUT+,
TxCLKOUT-,
VODSEL = L TxOUT[3:0]+,
VODSEL = H TxOUT[3:0]-
1.0
mV
mVp-p
mVp-p
4
50
mV
1.2
1.5
V
50
mV
1.2
1
V
-5
mA
-10
+10
µA
2.2
VDDIO
V
GND
0.8
V
+15
μA
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
VIN = 0V or VDDIO
VOH
High Level Output Voltage
IOH = −2 mA
VOL
Low Level Output Voltage
IOL = +2 mA
IOS
Output Short Circuit Current
VOUT = 0V
IOZ
TRI-STATE® Output Current
PDB = 0V, OSS_SEL = 0V, VOUT = 0V
or VDDIO
PDB,
VODSEL,
OEN,
OSS_SEL,
MAPSEL,
LFMODE,
SSC[2:0],
BISTEN
-15
±1
VDDIO0.25
VDDIO
GND
LOCK, PASS
V
0.2
-45
V
mA
-10
+10
µA
0.7*
VDDIO
VDDIO
V
GND
0.3*
VDDIO
V
+10
μA
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
VIN = 0V or VDDIO
VOH
High Level Output Voltage
IOH = −2 mA
VOL
Low Level Output Voltage
IOL = +2 mA
IOS
Output Short Circuit Current
VOUT = 0V
IOZ
TRI-STATE® Output Current
VOUT = 0V or VDDIO
(1)
(2)
(3)
(4)
6
PDB,
VODSEL,
OEN,
OSS_SEL,
MAPSEL,
LFMODE,
SSC[2:0],
BISTEN
LOCK, PASS
-10
±1
VDDIO
- 0.2
VDDIO
GND
V
0.2
-13
-15
V
mA
+15
µA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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DC Electrical Characteristics(1)(2)(3)(4) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
+50
mV
FPD-Link II LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input Threshold
High Voltage
VTL
Differential Input Threshold Low
Voltage
VCM
Common Mode Voltage,
Internal VBIAS
RT
Input Termination
VCM = +1.2V (Internal VBIAS)
RIN+, RIN-
-50
mV
1.2
80
V
100
120
Ω
85
95
mA
SUPPLY CURRENT
IDD1
IDDTX1
Supply Current
(includes load current)
65 MHz Clock
IDDIO1
IDD2
IDDTX2
Supply Current
(includes load current)
65 MHz Clock
IDDIO2
All VDD(1.8)
VDDn= 1.89V
pins
Checker Board Pattern,
VODSEL = H
VDDTX = 3.6V VDDTX
SSC{2:0] = 000
VDDIO=1.89V
Figure 2
VDDIO
VDDIO = 3.6V
All VDD(1.8)
VDDn= 1.89V
pins
Checker Board Pattern,
VODSEL = H
VDDTX = 3.6V VDDTX
SSC[2:0] = 111
VDDIO=1.89V
Figure 2
VDDIO
VDDIO = 3.6V
IDDZ
IDDTXZ
VDD= 1.89V
Supply Current Power Down
PDB = 0V, All other
LVCMOS Inputs = 0V
IDDIOZ
All VDD(1.8)
pins
40
50
mA
0.3
0.8
mA
0.8
1.5
mA
95
mA
40
mA
0.3
mA
0.8
mA
0.15
2.00
mA
VDDTX = 3.6V VDDTX
0.01
0.10
mA
VDDIO=1.89V
0.01
0.08
mA
0.01
0.08
mA
VDDIO = 3.6V
VDDIO
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Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
FPD-Link II
tDDLT
tIJIT
Lock Time, Figure 7 (1)
Input Jitter Tolerance, Figure 10
SSC[2:0] = 000
5 MHz
7
ms
SSC[2:0] = 111
5 MHz
14
ms
SSC[2:0] = 000
65 MHz
6
ms
SSC[2:0] = 111
65 MHz
EQ = Off
SSC[2:0] = 000
TxCLKOUT± = 65 MHz
8
ms
Input Jitter Frequency <
2 MHz
>0.9
UI
Input Jitter Frequency >
6 MHz
> 0.5
UI
FPD-Link Output
tTLHT
Low to High Transition Time
tTHLT
High to Low Transition Time
tDCCJ
Cycle-to-Cycle Output
Jitter (2) (3) (4)
RL = 100Ω
5 MHz
65 MHz
0.3
TxCLKOUT±,
TxOUT[3:0]±
TxCLKOUT±
0.6
ns
0.3
0.6
ns
900
2100
ps
75
125
ps
tTTP1
Transmitter Pulse Position for
bit 1
1
UI
tTTP0
Transmitter Pulse Position for
bit 0
2
UI
tTPP6
Transmitter Pulse Position for
bit 6
3
UI
tTTP5
Transmitter Pulse Position for
bit 5
4
UI
tTTP4
Transmitter Pulse Position for
bit 4
5
UI
tTTP3
Transmitter Pulse Position for
bit 3
6
UI
tTTP2
Transmitter Pulse Position for
bit 2
7
UI
ΔtTTP
Offset Transmitter Pulse
Position (bit 6— bit 0)
65 MHz, Figure 9
< +0.1
UI
tDD
Delay-Latency
SeeFigure 4
10*T
T
tTPDD
Power Down Delay, active to
OFF
65 MHz, Figure 5
7
12
ns
tTXZR
Enable Delay, OFF to active
65 MHz, Figure 6
40
55
ns
5
15
ns
5 - 65 MHz, Figure 9
TxOUT[3:0]±
LVCMOS Outputs
tCLH
Low to High Transition Time
tCHL
High to Low Transition Time
tPASS
BIST PASS Valid Time,
BISTEN = 1, Figure 11
CL = 8 pF, Figure 3
5 MHz
65 MHz
LOCK, PASS
PASS
5
15
ns
570
580
ns
50
65
ns
SSCG Mode
fDEV
fMOD
(1)
(2)
(3)
(4)
8
Spread Spectrum
Clocking Deviation
Frequency
See (4)
TxCLKOUT = 5 to 65
MHz,
SSC[2:0] = ON
±0.5
±2
%
Spread Spectrum
Clocking Modulation
Frequency
See (4)
TxCLKOUT = 5 to 65
MHz,
SSC[2:0] = ON
8
100
kHz
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
tDCCJ is the maximum amount of jitter between adjacent clock cycles.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
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Recommended Timing for the Serial Control Bus
Over 3.3V operating supply and temperature ranges unless otherwise specified.
Symbol
fSCL
tLOW
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tSU;DAT
Parameter
SCL Clock Frequency
SCL Low Period
Conditions
Min
Typ
Max
Standard Mode
0
100
Fast Mode
0
400
Units
kHz
Standard Mode
4.7
us
Fast Mode
1.3
us
Standard Mode
4.0
us
Fast Mode
0.6
us
Hold time for a start or a
repeated start condition,
Figure 12
Standard Mode
4.0
us
Fast Mode
0.6
us
Set Up time for a start or a
repeated start condition,
Figure 12
Standard Mode
4.7
us
Fast Mode
0.6
us
Data Hold Time, Figure 12
Standard Mode
0
3.45
us
Fast Mode
0
0.9
us
SCL High Period
Standard Mode
250
ns
Fast Mode
100
ns
Set Up Time for STOP
Condition, Figure 12
Standard Mode
4.0
us
Fast Mode
0.6
us
Bus Free Time Between STOP
and START, Figure 12
Standard Mode
4.7
us
Fast Mode
1.3
tr
SCL & SDA Rise Time,
Figure 12
Standard Mode
1000
ns
Fast Mode
300
ns
tf
SCL & SDA Fall Time,
Figure 12
Standard Mode
300
ns
Fast mode
300
ns
tSU;STO
tBUF
Data Set Up Time, Figure 12
us
DC and AC Serial Control Bus Characteristics
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
Parameter
VIH
Input High Level
VIL
Input Low Level Voltage
VHY
Input Hysteresis
Conditions
Max
Units
SDA and SCL
0.7*
VDDIO
VDDIO
V
SDA and SCL
GND
0.3*
VDDIO
V
SDA, IOL = 0.5mA
Iin
SDA or SCL, Vin = VDDIO or GND
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time — READ
tHD;DAT
Hold Up Time — READ
tSP
Input Filter
Cin
Input Capacitance
Typ
>50
VOL
tR
Min
SDA, RPU = X, Cb ≤ 400pF, Figure 12
See Figure 12
SDA or SCL
mV
0
0.36
V
-10
+10
µA
800
ns
50
ns
540
ns
600
ns
50
ns
<5
pF
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AC Timing Diagrams and Test Circuits
+VOD
TxCLKOUT
-VOD
+VOD
TxOUT[odd]
-VOD
+VOD
TxOUT[even]
-VOD
Cycle N
Cycle N+1
Figure 2. Checkerboard Data Pattern
VDDIO
80%
20%
GND
tCLH
tCHL
Figure 3. LVCMOS Transition Times
0
1
2
2
3
0
1
2
|
|
2
3
2
3
0
1
2
|
2
|
1
|
0
|
|
RIN0-23
DCA, DCB
|
START
STOP START
STOP START
STOP START
STOP
BIT SYMBOL N BIT BIT SYMBOL N+1 BIT BIT SYMBOL N+2 BIT BIT SYMBOL N+3 BIT
2
3
tDD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Delay – Latency
PDB
VILmax
RIN
X
tTPDD
LOCK
Z
PASS
Z
TxCLKOUT
Z
TxOUT[3:0]
Z
Figure 5. FPD-Link & LVCMOS Powerdown Delay
10
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PDB
LOCK
tTXZR
OEN
VIHmin
Z
TxCLKOUT
Z
TxOUT[3:0]
Figure 6. FPD-Link Outputs Enable Delay
VIH(min)
PDB
RIN±
tDDLT
LOCK
VOH(min)
TRI-STATE
SINGLE-ENDED
Figure 7. PLL Lock Times
|VOD|
VOS
GND
DIFFERENTIAL
+VOD
0V
VODp-p
-VOD
tTLHT
tTHLT
Figure 8. FPD-Link (LVDS) Single-ended and Differential Waveforms
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Cycle N
TxCLKOUT±
bit 1
TxOUT[3:0]±
tTTP1
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1UI
tTTP2
2UI
tTTP3
'tTTP
3UI
tTTP4
4UI
tTTP5
5UI
tTTP6
tTTP7
6UI
7UI
Figure 9. FPD-Link Transmitter Pulse Positions
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tIJIT
= RxIN_TOL (Left + Right)
- tIJIT
Sampling Window = 1 UI
Figure 10. Receiver Input Jitter Tolerance
BISTEN
VILMAX
tPASS
PASS
(w/ errors)
VOLMAX
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 11. BIST PASS Waveform
12
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tr
tf
tBUF
SDA
tHD;STA
tSU;DAT
tLOW
tf
tSU;STO
tSP
tSU;STA
tHD;DAT
SCL
tHD;STA
tHIGH
tr
S
Sr
P
S
Figure 12. Serial Control Bus Timing Diagram
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Functional Description
The DS90UR908Q receives 27-bits of data (24-high speed bits and 3 low speed bits) over a single serial FPDLink II pair operating at 140Mbps to 1.82Gbps. The serial stream contains an embedded clock, video control
signals and the DC-balance information which enhances signal quality and supports AC coupling. The receiver
converts the serial stream into a 5-channel (4 data and 1 clock) FPD-Link LVDS Interface. The device is intended
to be used with the DS90UR907Q or the DS90UR905Q FPD-Link II serializers, but is backward compatible with
previous generation of FPD-Link II as well.
The device converts a single input serial data stream to a FPD-Link output bus, and also provides a signal check
for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or through the
optional serial control bus. It features enhance signal quality on the link by supporting the FPD-Link II data
coding that provides randomization, scrambling, and DC balancing of the data. It also includes multiple features
to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data, FPD-Link LVDS Output interface, and also the output spread spectrum clock generation (SSCG) support.
The power saving features include a power down mode, and optional LVCMOS (1.8 V) interface compatibility.
The DS90UR908Q can lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. It also synchronizes to the serializer regardless of the data pattern,
delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need
of special training patterns or sync characters. The DS90UR908Q recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream.
The DS90UR907Q / DS90UR908Q chipset supports 24-bit color depth, HS, VS and DE video control signals and
up to three over-sampled low-speed (general purpose) data bits.
DATA TRANSFER
The DS90UR908Q will receive a pixel of data in the following format: C1 and C0 represent the embedded clock
in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled data. DCB is the
DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit
determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data
stream. Both DCA and DCB coding schemes are generated by the Ser and decoded by the Des automatically.
Figure 13 illustrates the serial stream per PCLK cycle.
Note: The figure only illustrates the bits but does not actually represent the bit location as the bits are scrambled
and balanced continuously.
C
1
b
0
b
1
D
C
B
b
2
b
1
2
b
3
b
1
3
b
4
b
1
4
b
5
b
1
5
b
6
b
1
6
b
7
b
1
7
b
8
b
1
8
b
9
b
1
9
b
1
0
b
2
0
b
1
1
b
2
1
D
C
A
b
2
2
b
2
3
C
0
Figure 13. FPD-Link II Serial Stream
The device supports clocks in the range of 5 MHz to 65 MHz. With every clock cycle 24 bits of payload are
received along with the four overhead bits. Thus, the line rate is 1.82 Gbps maximum (140 Mbps minimum) with
an effective data rate of 1.56 Gbps maximum. The link is extremely efficient at 86% (24/28).
OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0])
The DS90UR908Q is backward compatible with previous generations of FPD-Link II serializers. Configuration
modes are provided for backwards compatibility with the DS90C241 FPD-Link II Generation 1, and also the
DS90UR241 or DS99R421 FPD-Link II Generation 2 serializer by setting the respective mode with the
CONFIG[1:0] pins as shown in Table 1. The selection also determine whether the Video Control Signal filter
feature is enabled or disabled in Normal mode. This feature may be controlled by pin or by Register.
14
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Table 1. DS90UR908Q Configuration Modes
CONFIG1
CONFIG0
Mode
Des Device
L
L
Normal Mode, Control Signal Filter disabled
DS90UR907Q, DS90UR905Q
L
H
Normal Mode, Control Signal Filter enabled
DS90UR907Q, DS90UR905Q
H
L
Backwards Compatible GEN2
DS90UR241, DS99R421
H
H
Backwards Compatible GEN1
DS90C241
VIDEO CONTROL SIGNAL FILTER
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 14.
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 14. Video Control Signal Filter Wavefrom
COLOR BIT MAPPING SELECT
The DS90UR908Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs
on TxOUT[3] shown in Figure 15 or MSBs on TxOUT[3] shown in Figure 16. The user selects which mapping
scheme is controlled by MAPSEL pin or by Register.
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TxCLKOUT +/Previous cycle
Current cycle
TxOUT3 +/-
DE
(bit 20)
TxOUT2 +/-
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
VS
(bit 19)
HS
(bit 18)
B[7]
(bit 17)
R[1]
(bit 22)
R[0]
(bit 21)
B[6]
(bit 16)
B[5]
(bit 15)
B[4]
(bit 14)
G[0]
(bit 23)
TxOUT1 +/-
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
TxOUT0 +/-
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
Figure 15. 8–bit FPD-LInk Mapping: LSB's on TxOUT3
TxCLKOUT +/Previous cycle
Current cycle
B[7]
(bit 26)
TxOUT3 +/-
DE
(bit 20)
TxOUT2 +/-
VS
(bit 19)
B[6]
(bit 25)
G[7]
(bit 24)
HS
(bit 18)
B[5]
(bit 17)
R[7]
(bit 22)
R[6]
(bit 21)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
G[6]
(bit 23)
TxOUT1 +/-
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
TxOUT0 +/-
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 16. 8–bit FPD-LInk Mapping: MSB's on TxOUT3
FPD-LINK II INPUT
Common Mode Filter Pin (CMF) — Optional
The DS90UR908Q provides access to the center tap of the internal termination. A capacitor may be placed on
this pin for additional common-mode filtering of the differential pair. This can be useful in high noise
environments for additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
Input Equalizer Gain (EQ)
The DS90UR908Q can enable receiver input equalization of the serial stream to compensate the cable loss and
increase the eye opening to the input. The equalization feature may be controlled by the EQ pin (strap option)
Table 4 or by register Table 8.
16
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Table 2. EQ Pin Configuration Table
EQ (Strap Option)
Effect
L
EQ = Off
H
~12 dB
POWER SAVING FEATURES
PowerDown Feature (PDB)
The DS90UR908Q has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by
the system to save power, disabling the Des when the display is not needed. An auto detect mode is also
available. In this mode, the PDB pin is tied High and the Des will enter POWER DOWN when the serial stream
stops. When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and
output valid data. In POWER DOWN mode, the Data and PCLK output states are determined by the OSS_SEL
status. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Stop Stream SLEEP Feature
The DS90UR908Q will enter a low power SLEEP state when the input serial stream is stopped. A STOP
condition is detected when the embedded clock bits are not present. When the serial stream starts again, the
Des will then lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional
Serial Bus Control Registers values are RETAINED.
OUTPUT INTERFACES (LVCMOS & FPD-LINK)
CLOCK-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is Low and the FPD-Link
interface state is determined by the state of the OSS_SEL pin.
After the DS90UR908Q completes its lock sequence to the input serial data, the LOCK output is driven HIGH,
indicating valid data and clock recovered from the serial input is available on the FPD-Link outputs. The TxCLK
output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered
clock (or vice versa). Note that the FPD-Link outputs may be held in an inactive state (TRI-STATE) through the
use of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based
on the OSS_SEL setting (configuration pin or register).
Table 3. Output State Table
INPUTS
OUTPUTS
PDB
OEN
OSS_SEL
LOCK
OTHER OUTPUTS
L
X
X
X
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
L
X
L
L
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is HIGH
H
L
H
L
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
H
H
H
L
TxCLKOUT is TRI-STATE or OSC Output through Register bit
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
H
L
X
H
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is HIGH
H
H
X
H
TxCLKOUT is Active
TxOUT[3:0] are Active
PASS is Active
(Normal operating mode)
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LVCMOS 1.8V / 3.3V VDDIO Operation
The LVCMOS outputs can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility. The 1.8 V
levels will offer a system power savings. This applies to the following pins: PASS and LOCK.
FPD-LINK OUTPUT
VODSEL
The differential output voltage of the FPD-Link interface is controlled by the VODSEL input.
Table 4. VODSEL Configuration Table
VODSEL
Result
L
VOD is 250mV TYP (500mVp-p)
H
VOD is 400mV TYP (800mVp-p)
SSCG GENERATION — OPTIONAL
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4% total) at up
to 35kHz modulations nominally are available. See Table 5 and Table 6. This feature may be controlled by pins
or by register. The LFMODE should be set appropriately if the SSCG is being used. Set LFMODE High if the
clock frequency is between 5 MHz and 20 MHz, set LFMODE Low if the clock frequency is between 20 MHz and
65 MHz.
Table 5. SSCG Configuration (LFMODE = L) — Des Output
SSC[2:0] Inputs
LFMODE = L (20 - 65 MHz)
Result
SSC2
SSC1
SSC0
fdev (%)
fmod (kHz)
L
L
L
OFF
OFF
L
L
H
±0.9
L
H
L
±1.2
L
H
H
±1.9
H
L
L
±2.3
H
L
H
±0.7
H
H
L
±1.3
H
H
H
±1.7
CLK/2168
CLK/1300
Table 6. SSCG Configuration (LFMODE = H) — Des Output
SSC[2:0] Inputs
LFMODE = H (5 - 20 MHz)
18
Result
SSC2
SSC1
SSC0
fdev (%)
fmod (kHz)
L
L
L
OFF
OFF
L
L
H
±0.7
L
H
L
±1.3
L
H
H
±1.8
H
L
L
±2.2
H
L
H
±0.7
H
H
L
±1.2
H
H
H
±1.7
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CLK/385
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Frequency
fdev(max)
FPCLK+
FPCLK
FPCLK-
fdev(min)
Time
1/fmod
Figure 17. SSCG Waveform
OSCILLATOR OUTPUT — OPTIONAL
The DS90UR908Q provides an optional TxCLKOUT when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin and the register. See Table 3, Table 8, and Figure 18.
PDB
RIN
(Diff.)
LOCK
TxOUT[3:0]
TxCLKOUT
active serial stream
X
H
H
L
L
L
Z
Z
Z
Z
Z
f
f
Z
Z
Z
PASS
OFF
OSC Output
Active
OSC Output
Active
OFF
CONDITIONS: OEN = H, OSS_SEL = H, and OSC_SEL not equal to 000.
Figure 18. TxCLKOUT Output Oscillator Option Enabled
Built In Self Test (BIST) — Optional
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only an input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
The PASS output pin toggles to flag any payloads that are received with 1 to 24 bit errors. The BISTM pin
selects the operational mode of the PASS pin. If BISTM = L, the PASS pins reports the final result only. If BISTM
= H, the PASS pins counts payload errors and also results the result. The result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the Des BISTEN pin.
Sample BIST Sequence
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See Figure 19 for the BIST mode flow diagram.
Step 1: Place the DS90UR907Q or DS90UR905Q in BIST Mode by setting BISTEN = H. The BIST Mode is
enabled via the BISTEN pin. An RxCLKIN or PCLK is required for all the Ser options. When the DS90UR908Q
detects the BIST mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut
off.
Step 2: Place the DS90UR908Q in BIST mode by setting the BISTEN = H. The Device is now in the BIST mode
and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin
will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the DS90UR908Q BISTEN pin is set Low. It stops checking the data and the
final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one
or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the
device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set Low. The Link returns to normal
operation.
Figure 20 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
Start
Step 3: DES in Normal
Mode - check PASS
BIST
Stop
Step 4: SER in Normal
Figure 19. BIST Mode Flow Diagram
20
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SER
BISTEN
(Serializer)
DES Outputs
BISTEN
(DS90UR908Q)
Case 1 - Pass
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
Case 2a - Fail
X = bit error(s)
DATA
(internal)
X
FAIL
Prior Result
PASS
X
X
X
FAIL
Prior Result
Normal
Case 2b - Fail
X = bit error(s)
DATA
(internal)
PRBS
BIST
Result
Held
BIST Test
BIST Duration
Normal
Figure 20. BIST Waveforms
Serial Bus Control — Optional
The DS90UR908Q may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 21.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most
applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
VDDIO
10k
ID[X]
4.7k
4.7k
RID
HOST
DS90UR908Q
SCL
SCL
SDA
SDA
To other
Devices
Figure 21. Serial Control Bus Connection
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SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 22. START and STOP Conditions
The third pin is the ID[X] pin. This pin sets one of five possible device addresses. Two different connections are
possible. The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull up resistor (to
VDD1.8V, NOT VDDIO)) and a pull down resistor of the recommended value to set other three possible addresses
may be used. See Table 7 for the Des. Do not tie ID[x] directly to ground.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 22.
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 23 and a WRITE is shown in Figure 24.
If the Serial Bus is not required, the three pins may be left open (NC).
Table 7. ID[x] Resistor Value
Resistor
RID kΩ
(5%tol)
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
7b' 111 0001 (h'71)
8b' 1110 0010 (h'E2)
2.7
7b' 111 0010 (h'72)
8b' 1110 0100 (h'E4)
8.2
7b' 111 0011 (h'73)
8b' 1110 0110 (h'E6)
Open
7b' 111 0110 (h'76)
8b' 1110 1100 (h'EC)
Register Address
Slave Address
S
A
2
A
1
A
0
0
Slave Address
a
c
k
a
c
k
A
2
S
A
1
A
0
Data
1
a
c
k
a
c
k
P
Figure 23. Serial Control Bus — READ
Register Address
Slave Address
S
A
2
A
1
A
0
0
a
c
k
Data
a
c
k
a
c
k
P
Figure 24. Serial Control Bus — WRITE
22
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Table 8. Serial Bus Control Registers
ADD ADD Register Name
(dec) (hex)
0
1
2
0
1
2
Des Config 1
Slave ID
Des Features 1
Bit(s)
R/W
Defau Function
lt
(bin)
Description
7
R/W
0
LFMODE
0: 20 to 65 MHz Operation
1: 5 to 20 MHz Operation
6
R/W
0
MAPSEL
FPD-Link Map Select
0: LSB on TxOUT3+/1: MSB on TxOUT3+/-
5
R/W
0
Reserved
Reserved
4
R/W
0
Reserved
Reserved
3:2
R/W
00
CONFIG
00:
01:
10:
11:
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
R/W
0
REG Control
0: Configurations set from control pins / STRAP pin
1: Configurations set from registers (except I2C_ID)
7
R/W
0
6:0
R/W
7
R/W
0
OEN
Output Enable Input, Table 3
6
R/W
0
OSS_SEL
Output Sleep State Select, Table 3
5:4
R/W
00
Reserved
Reserved
3
R/W
0
VODSEL
Differential Driver Output Voltage Select
0: LVDS VOD is ±250 mV, 500 mVp-p (typ)
1: LVDS VOD is ±400 mV, 800 mVp-p (typ)
2:0
R/W
00
OSC_SEL
000: OFF
001: Reserved
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
Normal Mode, Control Signal Filter Disabled
Normal Mode, Control Signal Filter Enabled
Backwards Compatible (DS90UR241)
Backwards Compatible (DS90C241)
0: Address from ID[X] Pin
1: Address from Register
11100 ID[X]
00
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71); 8b ' 1110 0010 (h'E2)
7b '1110 010 (h'72); 8b ' 1110 0100 (h'E4)
7b '1110 011 (h'73); 8b ' 1110 0110 (h'E6)
7b '1110 110 (h'76); 8b ' 1110 1100 (h'EC)
All other addresses are Reserved.
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Table 8. Serial Bus Control Registers (continued)
ADD ADD Register Name
(dec) (hex)
3
24
3
Des Features 2
Bit(s)
R/W
Defau Function
lt
(bin)
7:5
R/W
000
4
R/W
3
2:0
Description
EQ Gain
000:
001:
010:
011:
100:
101:
110:
111:
~1.625 dB
~3.25 dB
~4.87 dB
~6.5 dB
~8.125 dB
~9.75 dB
~11.375 dB
~13 dB
0
EQ Enable
0: EQ = disabled
1: EQ = enabled
R/W
0
Reserved
Reserved
R/W
000
SSC
IF LFMODE = 0, then:
000: SSCG OFF
001: fdev = ±0.9%, fmod = CLK/2168
010: fdev = ±1.2%, fmod = CLK/2168
011: fdev = ±1.9%, fmod = CLK/2168
100: fdev = ±2.3%, fmod = CLK/2168
101: fdev = ±0.7%, fmod = CLK/1300
110: fdev = ±1.3%, fmod = CLK/1300
111: fdev = ±1.57%, fmod = CLK/1300
IF LFMODE = 1, then:
000: SSCG OFF
001: fdev = ±0.7%, fmod = CLK/625
010: fdev = ±1.3%, fmod = CLK/625
011: fdev = ±1.8%, fmod = CLK/625
100: fdev = ±2.2%, fmod = CLK/625
101: fdev = ±0.7%, fmod = CLK/385
110: fdev = ±1.2%, fmod = CLK/385
111: fdev = ±1.7%, fmod = CLK/385
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APPLICATIONS INFORMATION
DISPLAY APPLICATION
The DS90UR908Q, in conjunction with the DS90UR907Q or DS90UR905Q, is intended for interfacing between a
host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768
display formats. In a RGB888 application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three
control bits (VS, HS and DE) are supported across the serial link with PCLK rates from 5 to 65 MHz. The device
may also be used in 18-bit color applications. In this application three to six general purpose signals may also be
send from host to display.
TYPICAL APPLICATION CONNECTION
Figure 25 shows a typical application of the DS90UR908Q for a 65 MHz XGA Display. The LVDS inputs utilize
100 nF coupling capacitors to the line and the Receiver provides internal termination. Bypass capacitors are
placed near the power supply pins. Ferrite beads are placed on the power lines for effective noise suppression.
DS90UR908Q
1.8V
VDDL
C11
3.3V
FB4
FB1
VDDTX
C6
C3
C8
C9
C12
VDDL
FB2
VDDIO
FB5
VDDA
C4
VDDIO
C7
VDDA
C10
FB3
C13
VDDP
C5
VDDSC
VDDSC
TxCLKOUT+
TxCLKOUT-
C1
TxOUT3+
RIN+
TxOUT3-
Serial
FPD-Link II
Interface
FPD-Link
Interface
TxOUT2+
RINC2
LVDS
100 Ohm
Termination
TxOUT2TxOUT1+
CMF
TxOUT1-
C14
TxOUT0+
TxOUT0BISTEN
Host
Control
PDB
LOCK
R
C15
PASS
1.8V
10k
ID[X]
SCL
SDA
RID
C1 - C2 = 0.1 PF (50 WV)
C3 ± C10 = 0.1 PF
C11 - C14 = 4.7 PF
C15 = >10 PF
R = 10 k:
RID (See ID[x] Resistor Value Table)
FB1 - FB5: Impedance = 1 k:
Low DC resistance ( <1:)
8
RES
GND
DAP (GND)
OEN
OSS_SEL
LFMODE
VODSEL
MAPSEL
CONFIG1
CONFIG0
SSC[2]
SSC[1]
SSC[0]
Figure 25. DS90UR908Q Typical Connection Diagram
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POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn), VDDTX and VDDIO supply ramps should be faster than 1.5 ms with a monotonic rise. Supplies
may power up in any order, however device operation should be initiated only after all supplies are in their valid
operating ranges. The optional serial bus address selection is done upon power up also. Thus, if using this
optional feature, the PDB signal must be delayed to allow time for the ID setting to occur. The delay maybe done
by simply holding the PDB pin at a Low, or with an external RC delay based off the VDDIO rail which would then
need to lag the others in time. If the PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and a
10 uF cap to GND to delay the PDB input signal.
TRANSMISSION MEDIA
The FPD-Link II chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through
twisted pair cable. The serializer and deserializer provide internal terminations providing a clean signaling
environment. The interconnect for LVDS should present a differential impedance of 100 Ω. Use cables and
connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or unshielded cables may be used depending upon the noise environment and application requirements.
LIVE LINK INSERTION
The serializer and deserializer devices support live pluggable applications. The automatic receiver lock to
random data “plug & go” hot insertion capability allows the DS90UR908Q to attain lock to the active data stream
during a live insertion event.
ALTERNATE COLOR / DATA MAPPING
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit and 18-bit
Applications. When connecting to earlier generations of FPD-Link II serializer devices, a color mapping review is
recommended to ensure the correct connectivity is obtained. Table 9 provides examples for interfacing between
DS90UR908Q and different deserializers.
Table 9. Alternate Color / Data Mapping
FPD-Link
TxOUT3
TxOUT2
TxOUT1
26
Bit Number
RGB (LSB
Example)
DS90UR905Q
DS90UR241
DS99R421
DS90C241
Bit 26
B1
B1
Bit 25
B0
B0
Bit 24
G1
G1
Bit 23
G0
G0
Bit 22
R1
R1
Bit 21
R0
R0
Bit 20
DE
DE
DIN20
DIN20
Bit 19
VS
VS
DIN19
DIN19
Bit 18
HS
HS
DIN18
Bit 17
B7
B7
DIN17
Bit 16
B6
B6
DIN16
DIN16
Bit 15
B5
B5
DIN15
DIN15
Bit 14
B4
B4
DIN14
DIN14
Bit 13
B3
B3
DIN13
DIN13
Bit 12
B2
B2
DIN12
DIN12
Bit 11
G7
G7
DIN11
DIN11
Bit 10
G6
G6
DIN10
Bit 9
G5
G5
DIN9
DIN9
Bit 8
G4
G4
DIN8
DIN8
Bit 7
G3
G3
DIN7
DIN7
N/A
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DIN18
RxIN2
RxIN1
DIN17
DIN10
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Table 9. Alternate Color / Data Mapping (continued)
FPD-Link
TxOUT0
Bit Number
RGB (LSB
Example)
DS90UR905Q
DS90UR241
Bit 6
G2
G2
DIN6
DIN6
Bit 5
R7
R7
DIN5
DIN5
Bit 4
R6
R6
DIN4
DIN4
Bit 3
R5
R5
DIN3
Bit 2
R4
R4
DIN2
DIN2
Bit 1
R3
R3
DIN1
DIN1
Bit 0
R2
N/A
DS90UR908Q
Settings
MAPSEL = 0
DS99R421
RxIN0
DS90C241
DIN3
R2
DIN0
N/ADIN12
DIN23
OS2
DIN23
DIN22
OS1
DIN22
DIN21
OS0
DIN21
CONFIG [1:0] =
00
DIN0
CONFIG [1:0] = 10
CONFIG [1:0] =
11
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50µF to 100µF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ω
are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise
will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate
less.
Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).
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LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
Revision History
•
•
•
•
28
03/30/2010 —
07/26/2010 —
08/09/2010 —
04/16/2013 —
Initial Release
Update all final AC and DC parameter limits
Update Pin Description of VODSEL
Changed layout of National Data Sheet to TI format
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DS90UR908QSQ/NOPB
ACTIVE
WQFN
RHS
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
90UR908Q
DS90UR908QSQE/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
90UR908Q
DS90UR908QSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
90UR908Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS90UR908QSQ/NOPB
Package Package Pins
Type Drawing
WQFN
RHS
48
DS90UR908QSQE/NOPB WQFN
RHS
DS90UR908QSQX/NOPB WQFN
RHS
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UR908QSQ/NOPB
WQFN
RHS
48
1000
367.0
367.0
38.0
DS90UR908QSQE/NOPB
WQFN
RHS
48
250
210.0
185.0
35.0
DS90UR908QSQX/NOPB
WQFN
RHS
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHS0048A
WQFN - 0.8 mm max height
SCALE 1.800
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
A
B
PIN 1 INDEX AREA
0.5
0.3
7.15
6.85
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
(0.2)
5.1 0.1
(A) TYP
24
13
44X 0.5
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
12
25
EXPOSED
THERMAL PAD
2X
5.5
49
SYMM
SEE TERMINAL
DETAIL
1
PIN 1 ID
(OPTIONAL)
36
48
37
SYMM
48X
0.5
0.3
48X
0.30
0.18
0.1
0.05
C A B
4214990/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 5.1)
SYMM
37
48
48X (0.6)
1
36
48X (0.25)
(1.05) TYP
44X (0.5)
(1.25) TYP
49
SYMM
(6.8)
(R0.05)
TYP
( 0.2) TYP
VIA
25
12
13
24
(1.25)
TYP
(1.05)
TYP
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214990/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.625) TYP
(1.25)
TYP
37
48
48X (0.6)
1
36
49
48X (0.25)
44X (0.5)
(1.25)
TYP
(0.625) TYP
SYMM
(6.8)
(R0.05) TYP
METAL
TYP
25
12
13
16X
( 1.05)
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4214990/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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