Texas Instruments | DS26LV31QML 3V Enhanced CMOS Quad Differential Line Driver (Rev. A) | Datasheet | Texas Instruments DS26LV31QML 3V Enhanced CMOS Quad Differential Line Driver (Rev. A) Datasheet

Texas Instruments DS26LV31QML 3V Enhanced CMOS Quad Differential Line Driver (Rev. A) Datasheet
DS26LV31QML
www.ti.com
SNOSAS6A – MARCH 2006 – REVISED APRIL 2013
DS26LV31QML 3V Enhanced CMOS Quad Differential Line Driver
Check for Samples: DS26LV31QML
FEATURES
DESCRIPTION
•
The DS26lV31 is a high-speed quad differential
CMOS driver that is comparable to the TIA/EIA-422-B
and ITU-T V.11 standards. The CMOS DS26LV31
features low static ICC of 125 µA Max which makes it
ideal for battery powered and power conscious
applications. Differential outputs have the same VOD
specification (≥2V) as the 5V version. The EN and EN
inputs allow active Low or active High control of the
TRI-STATE outputs. The enables are common to all
four drivers. Protection diodes protect all the driver
inputs against electrostatic discharge. The driver and
enable inputs (DI, EN, EN) are compatible with low
voltage LVTTL and LVCMOS devices.
1
2
•
•
•
Comparable to Both TIA/EIA-422 and ITU-T
V.11 Standards.
Interoperable with Existing 5V RS-422
Networks
Low Quiescent Current
Pin Compatible with DS26C31
Connection Diagram
Figure 1. CLGA Package- Top View
See Package Number NAD0016A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS26LV31QML
SNOSAS6A – MARCH 2006 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage (VCC)
-0.5V to 7.0V
DC Input Voltage (VI)
-0.5V to VCC+0.5V
DC Output Voltage (VO) Power off
-0.5V to 7V
Clamp Diode Current (IIK, IOK)
±20mA
DC Output Current, per Pin (IO)
±150mA
-65°C ≤ TA ≤ +150°C
Storage Temperature Range (TStg)
Lead Temperature (TL) Soldering, 4 seconds
Maximum Power Dissipation +25°C
260°C
(3)
1119mW
Thermal Resistance
(1)
(2)
(3)
θJA
134°C/W
θJC
12.5°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not verify specific performance limits. For verified specifications and test conditions, see the
Electrical Characteristics. The verified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive, all currents out of device
pins are negative.
Derate W package 7.5mW/°C above +25°C.
Recommended Operating Conditions
Supply Voltage (vCC)
3.0V to 3.6V
DC input or Output Voltage (VI, VO)
0V to VCC
Operating Temperature Range (TA)
−55°C ≤ TA ≤ +125°C
Table 1. Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A
2
Subgroup
Description
Temp °C
1
Static tests at
25
2
Static tests at
125
3
Static tests at
-55
4
Dynamic tests at
25
5
Dynamic tests at
125
6
Dynamic tests at
-55
7
Functional tests at
25
8A
Functional tests at
125
8B
Functional tests at
-55
9
Switching tests at
25
10
Switching tests at
125
11
Switching tests at
-55
12
Settling time at
25
13
Settling time at
125
14
Settling time at
-55
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS26LV31QML
DS26LV31QML
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SNOSAS6A – MARCH 2006 – REVISED APRIL 2013
DS26LV31M Electrical Characteristics DC Parameters
Parameter
Test Conditions
Notes
Min
VIH
Logical "1" Input Voltage
(1)
VIL
Logical "0" Input Voltage
(1)
VOD1
Differential Output Voltage
RL = No Load, VCC = 3.0/3.6V
(2)
VOD2
Differential Output Voltage
RL = 100Ω, VCC = 3.0/3.6V
(2)
2.0
VOD2-VOD2
Difference in Differential Output
RL = 100Ω, VCC = 3.0/3.6V
(2)
-0.4
VOD3
Differential Output Voltage
RL = 3900Ω, VCC = 3.0/3.6V
(2)
VOC
Common Mode Output Voltage
RL = 100Ω, VCC = 3.0/3.6V
(2)
VOC-VOC
Difference in Common Mode
Output
RL = 100Ω, VCC = 3.0/3.6V
(2)
IIL
Low Level Input Current
VI = Gnd, VCC = 3.6V
IIH
High Level Input Current
VI = VCC, VCC = 3.6V
VCL
Input Clamp Voltage
ICC
Max
2.0
-0.4
Units
Subgroups
V
1, 2, 3
0.8
V
1, 2, 3
4.0
V
1, 2, 3
V
1, 2, 3
0.4
V
1, 2, 3
3.6
V
1, 2, 3
2.0
V
1, 2, 3
0.4
V
1, 2, 3
µA
1, 2, 3
10
µA
1, 2, 3
II = -18mA, VCC = 3.0V
-1.5
V
1, 2, 3
Quiescent Power Supply Current
IO = 0uA, VI = VCC or Gnd,
VCC = 3.6V
125
µA
1, 2, 3
IOZ
TRI-STATE Output Leakage
Current
VO = VCC or Gnd, Enable = Vil, VCC
= 3.6V, Enable = VIH
±20
µA
1, 2, 3
ISC
Output Short Circuit Current
VI = VCC or Gnd,
VCC = 3.0/3.6V, VO = 0.0V
-160
mA
1, 2, 3
IOff
Output Leakage Current "Power
Off"
VCC = 0V, VO = 6.0V or 3.0V
100
µA
1, 2, 3
VCC = 0V, VO = -0.25V
-200
µA
1, 2, 3
(1)
(2)
(3)
-10
(2) (3)
,
-30
Parameter tested Go-No-Go only.
See EIA specification RS-422 for exact test condition.
This is a current sourced when a high output is shorted to Gnd. Only one output at a time should be shorted.
DS26LV31M Electrical Characteristics AC Parameters - Propagation Delay Time
The following conditions apply to all the following parameters, unless otherwise specified.
Parameter
tPLHD
Differential Propagation Delay
(Low to High)
Test Conditions
Notes
RL = 100Ω, CL = 50pF
(1)
AC: VCC = 3.0/3.6V
Min
Max
Units
Subgroups
5.0
25
ns
9, 10, 11
5.0
25
ns
9, 10, 11
tPHLD
Differential Propagation Delay
(High to Low)
RL = 100Ω, CL = 50pF
(1)
tSKD
Differential Skew tPHLD-tPLHD
(same channel)
RL = 100Ω, CL = 50pF
(1)
5.0
ns
9, 10, 11
tSK1
Pin to Pin Skew (same device)
RL = 100Ω, CL = 50pF
(1)
5.0
ns
9, 10, 11
tPZH
Output Enable Time
RL = 110Ω to Gnd, CL = 50pF
(2)
40
ns
9, 10, 11
tPZL
Output Enable Time
RL = 110Ω to VCC, CL = 50pF
(2)
40
ns
9, 10, 11
tPHZ
Output Disable Time
RL = 110Ω to Gnd, CL = 50pF
(2)
35
ns
9, 10, 11
tPLZ
Output Disable Time
RL = 110Ω to VCC, CL = 50pF
(2)
35
ns
9, 10, 11
(1)
(2)
Generator waveform is specified as follows: ƒ = 1MHz, Duty Cycle = 50%, ZO = 50Ω, tR = tF ≤ 6nS. Driver input = 0V to 3V with
measure points equal to 1.5V. Differential output VDiff = DO - DO with measure point equal to 0V.
Generator waveform is specified as follows: ƒ = 1MHz, Duty Cycle = 50%, ZO = 50Ω, tR = tF ≤ 6nS. En/En inputs = 0V to 3V with
measure points equal to 1.5V on the inputs, to 1.3V on the outputs for ZL and ZH, and (VOL + 0.3V) for LZ, and (VOH.- 0.3V) for HZ.
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS26LV31QML
3
DS26LV31QML
SNOSAS6A – MARCH 2006 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Released
4
Revision
3/01/06
*
4/15/2013
A
Section
New Release, Corporate format
Originator
Changes
L. Lytle
1 MDS data sheets converted into one Corp.
data sheet format. MNDS26LV31-X Rev 1A0
will be archived.
TIS
Changed layout of National Data Sheet to TI
format
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS26LV31QML
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9858401QFA
ACTIVE
CFP
NAD
16
19
TBD
Call TI
Call TI
-55 to 125
DS26LV31WQML Q
5962-98584
01QFA ACO
01QFA >T
DS26LV31W-QML
ACTIVE
CFP
NAD
16
19
TBD
Call TI
Call TI
-55 to 125
DS26LV31WQML Q
5962-98584
01QFA ACO
01QFA >T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
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Addendum-Page 2
MECHANICAL DATA
NAD0016A
W16A (Rev T)
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