Texas Instruments | LMH0046 HD/SD SDI Reclocker with Dual Differential Outputs (Rev. F) | Datasheet | Texas Instruments LMH0046 HD/SD SDI Reclocker with Dual Differential Outputs (Rev. F) Datasheet

Texas Instruments LMH0046 HD/SD SDI Reclocker with Dual Differential Outputs (Rev. F) Datasheet
LMH0046
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LMH0046 HD/SD SDI Reclocker With Dual Differential Outputs
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FEATURES
DESCRIPTION
•
The LMH0046 HD/SD SDI Reclocker retimes serial
digital video data conforming to the SMPTE 292M
and SMPTE 259M (A & C) standards. The LMH0046
operates at serial data rates of 143 Mbps, 270 Mbps,
1.483 Gbps and 1.485 Gbps. The LMH0046 supports
DVB-ASI operation at 270 Mbps.
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Supports SMPTE 292M and SMPTE 259M
(A & C) Serial Digital Video Standards
Supports 143 Mbps, 270 Mbps, 1.483 Gbps,
and 1.485 Gbps Serial Data Rate Operation
Supports DVB-ASI at 270 Mbps
Single 3.3V Supply Operation
330 mW Typical Power Consumption
Two Differential, Reclocked Outputs
Choice of Second Reclocked Output or LowJitter, Differential, Data-Rate Clock Output
Single 27 MHz External Crystal or Reference
Clock Input
Manual Rate Select Input
SD/HD Operating Rate Indicator Output
Lock Detect Indicator Output
Output Mute Function for Data and Clock
Auto/Manual Reclocker Bypass
Differential LVPECL Compatible Serial Data
Inputs and Outputs
LVCMOS Control Inputs and Indicator Outputs
20-Pin HTSSOP Package
Industrial Temperature Range: -40°C to +85°C
The LMH0046 automatically detects the incoming
data rate and adjusts itself to retime the incoming
data to suppress accumulated jitter. The LMH0046
recovers the serial data-rate clock and optionally
provides it as an output. The LMH0046 has two
differential serial data outputs; the second output may
be selected as a low-jitter, data-rate clock output.
Controls and indicators are: serial clock or second
serial data output select, manual rate select input,
SD/HD rate indicator output, lock detect output,
auto/manual data bypass and output mute. The serial
data inputs, outputs, and serial data-rate clock
outputs are differential LVPECL compatible. The CML
serial data and serial data-rate clock outputs are
suitable for driving 100Ω differentially terminated
networks. The control logic inputs and outputs are
LVCMOS compatible.
The LMH0046 is powered from a single 3.3V supply.
Power dissipation is typically 330 mW. The device is
housed in a 20-pin HTSSOP package.
APPLICATIONS
•
SDTV/HDTV Serial Digital Video Interfaces For:
– Digital Video Routers and Switchers
– Digital Video Processing and Editing
Equipment
– DVB-ASI Equipment
– Video Standards and Format Converters
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LMH0046
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Typical Application
CABLE
EQUALIZER
LMH0034
HD/SD
RECLOCKER
LMH0046
SERIAL DATA
CABLE
EQUALIZER
LMH0034
HD/SD
SERIALIZER
LMH0030
HD/SD
CROSSPOINT
SWITCH
CLC018 8x8
SD
SERIALIZER
CLC021A
HD/SD
RECLOCKER
LMH0046
HD/SD
RECLOCKER
LMH0046
HD/SD
RECLOCKER
LMH0046
HD/SD
DESERIALIZER
LMH0031
CABLE DRIVER
LMH0302
CABLE DRIVER
LMH0302
PARALLEL
DATA
SERIAL
DATA
CABLE DRIVER
LMH0302
PARALLEL
DATA
Figure 1. 1.485 Gbps Signal Before Reclocking
(0.75 UI Jitter)
2
Figure 2. 1.485 Gbps Signal After Reclocking (0.05
UI Jitter)
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Block Diagram
SCO_EN
BYPASS/ AUTO BYPASS
RATE0
SD/ HD
CONTROL LOGIC
LOCK DETECT
RATE1
VCCO
BYPASS
50
50
XTAL IN/EXT CLK
XTAL OUT
LOOP FILTER 1
SCO/SDO2
VCO / PLL
SCO/SDO2
LOOP FILTER 2
VCCO
O/P MUTE
50
50
SDO
SDI
SDI
RETIMER / FIFO
SDO
Connection Diagram
1
2
3
4
5
6
7
8
9
10
20
SCO_EN
19
SD/ HD
18
V
RATE0
CCO
17
SDO
RATE1
16
SDO
SDI
LMH0046 VCCO 15
SDI
14
VCC
SCO/SDO2
13
SCO/SDO2
BP/ AUTO-BP
12
OP MUTE
LOCK DET
11
XTAL IN/EXT CLK XTAL OUT
LF1
LF2
The exposed die attach pad is the negative electrical terminal for this device. It must be connected to the negative
power supply voltage.
Figure 3. 20-Pin HTSSOP
See PWP0020A Package
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Table 1. PIN DESCRIPTIONS
Pin
Description
LF1
Loop Filter
2
LF2
Loop Filter
3
RATE 0
Data Rate Select Input
4
RATE 1
Data Rate Select Input
5
SDI
Data Input True
6
SDI
Data Input Complement
7
VCC
Positive power supply input
8
BYPASS/AUTO BYPASS
Bypass/Auto Bypass mode select
9
OUTPUT MUTE
Data and Clock Output Mute Input (active low)
10
XTAL IN/EXT CLK
Crystal or External Oscillator Input
11
XTAL OUT
Crystal Oscillator Output
12
LOCK DETECT
PLL Lock Detect Output (active high)
13
SCO/SDO2
Serial Clock or Serial Data Output 2 Complement
14
SCO/SDO2
Serial Clock or Serial Data Output 2 True
15
VCCO
Positive power supply input (Output Driver)
16
SDO
Data Output Complement
17
SDO
Data Output True
18
VCCO
Positive power supply input (Output Driver)
19
SD/HD
Data Rate Range Output
20
SCO_EN
Serial Clock or Serial Data 2 Output select (active high enables serial clock output)
VEE
Connect exposed DAP to negative power supply (ground)
DAP
4
Name
1
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage (VCC–VEE)
4.0V
VEE−0.15V to
VCC+0.15V
Logic Supply Voltage (Vi)
Logic Input Current (single input):
Vi = VEE−0.15V
−5 mA
Vi = VCC+0.15V
+5 mA
VEE−0.15V to
VCC+0.15V
Logic Output Voltage (Vo)
Logic Output Source/Sink Current
±8 mA
VCC to VCC−2.0V
Serial Data Input Voltage (VSDI)
Serial Data Output Sink Current (ISDO)
Package Thermal Resistance, HTSSOP
24 mA
θJA
θJC
26.6°C/W
2.4°C/W
−65°C to +150°C
Storage Temp. Range
Junction Temperature
+150°C
Lead Temperature (Soldering 4 Sec)
+260°C (Pb-free)
ESD Rating (HBM)
7 kV
ESD Rating (MM)
350V
ESD Rating (CDM)
(1)
(2)
1250V
“Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
The table of “Electrical Characteristics” specifies acceptable device operating conditions.
It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Supply Voltage (VCC–VEE)
3.3V ±5%
Logic Input Voltage
VEE to VCC
Differential Serial Input Voltage
800 mV ±10%
Serial Data or Clock Output Sink
Current (ISO)
16 mA max.
−40°C to +85°C
Operating Free Air Temperature (TA)
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DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2)
Symbol
(1)
(2)
Parameter
Conditions
Reference
Logic inputs
Min
Typ
Max
Units
2
VCC
V
VEE
0.8
V
VIH
Input Voltage High Level
VIL
Input Voltage Low Level
IIH
Input Current High Level
VIH = VCC
1
65
µA
IIL
Input Current Low Level
VIL = VEE
−1
−25
µA
VOH
Output Voltage High Level IOH = −2 mA
VOL
Output Voltage Low Level
Logic outputs
2
V
IOL = +2 mA
VSDID
Serial Input Voltage,
Differential
SDI
VCMI
Input Common Mode
Voltage
VSDOD
Serial Output Voltage,
Differential
100Ω differential load
VCMO
Output Common Mode
Voltage
100Ω differential load
ICC
Power Supply Current,
3.3V supply, Total
1485 Mbps, NTSC color
bar pattern
SDO, SCO
VEE + 0.6
V
200
1600
mVP-P
VCC−1.6
VCC−0.2
V
880
mVP-P
720
800
VCC −
VSDOD
V
100
mA
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to
VEE (equal to zero volts).
Typical values are stated for: VCC = +3.3V, TA = +25°C.
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1)
Symbol
SMPTE 259M, A
BRSD
Serial Data Rate
SMPTE 259M, C
BRSD
Serial Data Rate
SMPTE 292M
TOLJIT
Serial Input Jitter
Tolerance
143 or 270 Mbps (2) (3) (4)
TOLJIT
Serial Input Jitter
Tolerance
143 or 270 Mbps
(2) (5) (6)
TOLJIT
Serial Input Jitter
Tolerance
1483 or 1485 Mbps (2) (5)
Reference
Min
SDI, SDO
SDI
Typ
Max
Units
143
Mbps
270
Mbps
1483,
1485
Mbps
>6
UIP-P
>0.6
UIP-P
>6
UIP-P
>0.6
UIP-P
(3)
(2) (5) (6)
Serial Input Jitter
Tolerance
1483 or 1485 Mbps
tJIT
Serial Data Output Jitter
143 Mbps (5) (7)
0.02
0.08
UIP-P
tJIT
Serial Data Output Jitter
270 Mbps (5) (7)
0.02
0.08
UIP-P
tJIT
Serial Data Output Jitter
1483 or 1485 Mbps (5) (7)
0.05
0.1
UIP-P
Loop Bandwidth
270 Mbps,
<0.1dB Peaking
300
kHz
1485 Mbps,
<0.1dB Peaking
2.0
MHz
BWLOOP
6
Conditions
Serial Data Rate
TOLJIT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Parameter
BRSD
SDO
Typical values are stated for: VCC = +3.3V, TA = +25°C.
Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.
Refer to “A1” in Figure 1 of SMPTE RP 184-1996.
Characterized to the limitations of SDI test equipment.
This parameter is ensured by characterization over voltage and temperature limits.
Refer to “A2” in Figure 1 of SMPTE RP 184-1996.
Serial Data Output Jitter is total output jitter with 0.2 UIP-P input jitter.
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AC Electrical Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)
Symbol
Parameter
Conditions
FCO
Serial Clock Output
Frequency
143 Mbps data rate
FCO
Serial Clock Output
Frequency
270 Mbps data rate
FCO
Serial Clock Output
Frequency
1483 Mbps data rate
FCO
Serial Clock Output
Frequency
1485 Mbps data rate
tJIT
Serial Clock Output Jitter
TACQ
Reference
SCO
Typ
SDO, SCO
Serial Clock Output Duty
Cycle
SCO
Auto-Rate Detect Mode (8) (9)
Fixed Rate Mode
(8) (9)
Max
Units
143
MHz
270
MHz
1483
MHz
1485
MHz
2
Serial Clock Output
Alignment with respect to
Data Interval
Acquisition Time
Min
3
psRMS
40
60
%
45
55
%
10
16
ms
1
6
ms
1.5
3
ns
1500
ps
270
ps
tr, tf
Input rise/fall time
10%–90%
Logic inputs
tr, tf
Input rise/fall time
20%–80%, 143 or 270 Mbps
SDI
tr, tf
Input rise/fall time
20%–80%, 1483 or 1485
Mbps
tr, tf
Output rise/fall time
10%–90%
Logic outputs
1.5
3
ns
tr, tf
Output rise/fall time
20%–80% (10)
SDO, SCO
90
130
ps
FREF
Reference Clock
Frequency
27
MHz
FTOL
Reference Clock
Frequency Tolerance
±50
ppm
(8) Spec is ensured by design.
(9) Measured from first SDI transition until Lock Detect (LD) output goes high (true).
(10) RL = 100Ω differential.
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DEVICE DESCRIPTION
The LMH0046 HD/SD SDI Reclocker is used in many types of digital video signal processing equipment.
Supported serial digital video standards are SMPTE 259M (A & C) and SMPTE 292M. Corresponding serial data
rates are 143 Mbps, 270 Mbps, 1.483 Gbps and 1.485 Gbps. DVB-ASI data at 270 Mbps may also be retimed.
The LMH0046 retimes the serial data stream to suppress accumulated jitter. It provides two low-jitter, differential,
serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate
clock. Controls and indicators are: serial data-rate clock or second serial data output select, manual rate select
input, SD/HD rate output, lock detect output, auto/manual data bypass and output mute.
Serial data inputs are CML and LVPECL compatible. Serial data and data-rate clock outputs are differential CML
and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω
differential loads. The differential output level is 800 mVP-P ±10% into 100Ω AC or DC-coupled differential loads.
Logic inputs and outputs are LVCMOS compatible.
The device package is a 20-pin HTSSOP with an exposed die attach pad. The exposed die attach pad is
electrically connected to device ground (VEE) and is the negative electrical terminal for the device. This terminal
must be connected to the negative power supply or circuit ground.
Serial Data Inputs, Serial Data and Clock Outputs
SERIAL DATA INPUT AND OUTPUTS
The differential serial data input, SDI, accepts serial digital video data at the rates specified in Table 2. The serial
data input is differential LVPECL compatible. The input is intended to be DC interfaced to devices such as the
LMH0034 adaptive cable equalizer. The input is not internally terminated or biased. The input may be ACcoupled if a suitable input bias voltage is provided. Figure 4 shows the equivalent input circuit for SDI and SDI.
The LMH0046 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide
low jitter, differential, retimed data to devices such as the LMH0002 cable driver or the LMH0031 deserializer.
Output SCO/SDO2 is multiplexed and can provide either a second serial data output or a serial data-rate clock
output. Figure 5 shows the equivalent output circuit for SDO, SDI, SCO/SDO2, and SCO/SDO2.
The SCO_EN input controls the operating mode for the SCO/SDO2 output. When the SCO_EN input is high the
SCO/SDO2 output provides a serial data-rate clock. When SCO_EN is low, the SCO/SDO2 output provides
retimed serial data.
Both differential serial data outputs, SDO and SCO/SDO2, are muted when the MUTE input is a logic low level.
SCO/SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock
output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The
CML serial data outputs are differential LVPECL compatible. These outputs have internal 50Ω pull-ups and are
suitable for driving AC or DC-coupled, 100Ω center-tapped, AC grounded or 100Ω un-center-tapped, differentially
terminated networks.
8
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VCC
20 k:
1 pF
80 k:
VCC
2 k:
VCC
2 k:
SDI
SDI
Figure 4. Equivalent SDI Input Circuit (SDI, SDI)
VCC
VCC
VCC
50:
50:
SDO, SCO/SDO2
SDO, SCO/SDO2
Figure 5. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)
OPERATING SERIAL DATA RATES
This device operates at serial data rates of 143 Mbps, 270 Mbps, 1483 Mbps and 1485 Mbps. The device does
not lock to harmonics of these rates. The device does not lock and automatically enters the reclocker bypass
mode for the following data rates: 177 Mbps, 360 Mbps, and 540 Mbps.
SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT
The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second
retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being
processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the
corresponding serial data bit interval within 10% of the center of the data interval.
Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low
level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The
SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2
enabled). SCO/SDO2 is muted when the MUTE input is a logic low level. When the Bypass mode is activated
and this output is functioning as a serial clock output, the output will also be muted.
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Control Inputs and Indicator Outputs
SERIAL DATA RATE SELECTOR
The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. The pins have
internal pull-downs which maintain a logic-low input condition unless externally driven to a logic-high condition.
This input also serves to place the device in a test mode. The codes shown in Table 2 select the desired
operating serial data rate. The LMH0046 then enters either the Auto-Rate Detect mode or a single operating rate.
Selecting the 270 Mbps rate mode may also be used when reclocking DVB-ASI data. DVB-ASI data is MPEG2
coded data that is transmitted in 8B10B coding. The device will reclock this data without harmonic locking. AutoRate Detect mode may be used for any supported data rate, including DVB-ASI.
Table 2. Data Rate Select Input Codes
Rate [1:0]
Code
Data Rate
or Mode
Comments
00
Auto-Rate Detect mode
143 Mbps rate operation supported only in ARD mode
01
270 Mbps
May be used to support DVB-ASI operation
10
1483/1485 Mbps
LOCK DETECT
The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be
connected to the MUTE input to mute the data and clock outputs when no data signal is being received. See
Table 3.
MUTE
The MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock Detect or
externally driven to mute or un-mute the outputs. If MUTE is connected to LD, then the data and clock outputs
are muted when the PLL is not locked. This function overrides the Bypass function: see Table 3. MUTE has an
internal pull-up device to enable the output by default.
BYPASS/AUTO BYPASS
The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this
input is low, the device automatically bypasses the reclocking function when the device is in an unlocked
condition or the detected data rate is a rate which the device does not support. See Table 3. BYPASS/AUTO
BYPASS has an internal pull-down device.
Table 3. Control Functionality
LOCK DETECT
OUTPUT MUTE
BYPASS/AUTO BYPASS
0
1
0
PLL unlocked, reclocker bypassed
DEVICE STATUS
1
1
0
PLL locked to supported data rate, reclocker not bypassed
X
0
X
Outputs muted
0
LOCK DETECT
X
Outputs muted
1
LOCK DETECT
0
PLL locked to supported data rate, reclocker not bypassed
1
LOCK DETECT
1
PLL locked to supported data rate, reclocker bypassed
X
1
1
Outputs not muted, reclocker bypassed
SD/HD
The SD/HD output indicates whether the LMH0046 is processing SD or HD data rates. It may be used to control
another device such as the LMH0002 cable driver. When this output is high it indicates that the data rate is 270
Mbps (or 143 Mbps). When low, the indicated data rate is 1483 or 1485 Mbps. The SD/HD output is a registered
function and is only valid when the PLL is locked and the Lock Detect output is high. When the PLL is not locked
(the Lock Detect output is low), the SD/HD output defaults to HD (low). The SD/HD output is undefined for a
short time after lock detect assertion or de-assertion due to a data rate change on SDI. See Figure 6 for a timing
diagram showing the relationship between SDI, Lock Detect, and SD/HD.
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SDI
NO DATA
270 MBPS DATA
TACQ
NO DATA
1485 MBPS DATA
T2
TACQ
NO DATA
T2
Lock
Detect
T1
T1
T1
SD/HD
SDI
NO DATA
143 MBPS DATA
270 MBPS DATA
1485 MBPS DATA
TACQ
TACQ
270 MBPS DATA
TACQ
T2
TACQ
T2
T2
Lock
Detect
T1
T1
T1
T1
T1
T1
SD/HD
TACQ = Acquisition Time, defined in the AC Electrical Characteristics Table
T1 = Time from Lock Detect assertion or deassertion until SD/HD output is valid, typically 37 ns (one 27 MHz clock period)
T2 = Time from SDI input change until Lock Detect de-assertion, 1 ms maximum. SD/HD output is not valid during this time.
Figure 6. SDI, Lock Detect, and SD/HD Timing
SCO_EN
Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial data-rate clock or second
serial data output. SCO/SDO2 functions as a serial data-rate clock when SCO_EN is high. This pin has an
internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output.
CRYSTAL OR EXTERNAL CLOCK REFERENCE
The LMH0046 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel
resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins.
Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a
suitable crystal are given in Table 4.
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Table 4. Crystal Parameters
Parameter
Value
Frequency
27 MHz
Frequency Stability
±50 ppm @ recommended drive level
Operating Mode
Fundamental mode, Parallel Resonant
Load Capacitance
20 pF
Shunt Capacitance
7 pF
Series Resistance
40Ω max.
Recommended Drive Level
100 µW
Maximum Drive Level
500 µW
Operating Temperature Range
−10°C to +60°C
12
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APPLICATION INFORMATION
Figure 7 shows an application circuit for the LMH0046 along with the LMH0034 SMPTE 292M / 259M Adaptive
Cable Equalizer and LMH0002 SMPTE 292M / 259M Cable Driver.
VCC
VCC
RATE0
56 nF
RATE1
SCO_EN
1
2
Coaxial Cable
LMH0034 Adaptive
Cable Equalizer
75:
3
4
1.0 PF
5
SDI SDO
1.0 PF
10 nH
6
100:
SDI
7
8
SDO
9
37.4:
AEC-
75:
AEC+
10
20
SCO_EN
19
SD/ HD
LF2
18
VCCO
RATE0
17
SDO
RATE1
16
SDI
LMH0046 SDO 15
VCCO
SDI
14
VCC
SCO/SDO2
13
SCO/SDO2
BP/ AUTO-BP
12
OP MUTE
LOCK DET
11
XTAL IN/EXT CLK XTAL OUT
LF1
A
B
C
Additional
Outputs
DAP
27 MHz
1.0 PF
39 pF
BP/ AUTO-BP
39 pF
LOCK DET
OP MUTE
+3.3V
A
75:
75:
5.6 nH
LMH0002
Cable Driver
SD/HD
B
75:
4.7 PF
Coaxial Cable
75:
4.7 PF
Coaxial Cable
SDI
SDO
100:
C
SDO
75:
SDI
RREF
75:
+3.3V
5.6 nH
750:
Figure 7. Application Circuit
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH0046
13
LMH0046
SNLS222F – APRIL 2006 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
•
14
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH0046
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LMH0046MH/NOPB
ACTIVE
HTSSOP
PWP
20
73
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L046
LMH0046MHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L046
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMH0046MHX/NOPB
Package Package Pins
Type Drawing
SPQ
HTSSOP
2500
PWP
20
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH0046MHX/NOPB
HTSSOP
PWP
20
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
PWP0020A
MXA20A (Rev C)
www.ti.com
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