Texas Instruments | DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis (Rev. E) | Datasheet | Texas Instruments DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis (Rev. E) Datasheet

Texas Instruments DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis (Rev. E) Datasheet
DS25BR120
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DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis
Check for Samples: DS25BR120
FEATURES
DESCRIPTION
•
The DS25BR120 is a single channel 3.125
LVDS buffer optimized for high-speed
transmission over lossy FR-4 printed circuit
backplanes and balanced metallic cables.
differential signal paths ensure exceptional
integrity and noise immunity.
1
2
•
•
•
•
DC - 3.125 Gbps Low Jitter, High Noise
Immunity, Low Power Operation
Four Levels of Transmit Pre-Emphasis Drive
Lossy Backplanes and Cables
On-Chip 100Ω Input and Output Termination
Minimizes Insertion and Return Losses,
Reduces Component Count, and Minimizes
Board Space
7 kV ESD on LVDS I/O pins Protects Adjoining
Components
Small 3 mm x 3 mm 8-WSON Space Saving
Package
The DS25BR120 features four levels of pre-emphasis
(PE) for use as an optimized driver device. Other
LVDS devices with similar IO characteristics include
the following products. The DS25BR110 features four
levels of equalization for use as an optimized receiver
device, while the DS25BR100 features both preemphasis and equalization for use as an optimized
repeater device. The DS25BR150 is a buffer/repeater
with the lowest power consumption and does not
feature
transmit
pre-emphasis
nor
receive
equalization.
APPLICATIONS
•
•
•
Gbps
signal
board
Fully
signal
Clock and Data Buffering
Metallic Cable Driving
FR-4 Driving
Wide input common mode range allows the receiver
to accept signals with LVDS, CML and LVPECL
levels; the output levels are LVDS. A very small
package footprint requires minimal space on the
board while the flow-through pinout allows easy board
layout. The differential inputs and outputs are
internally terminated with a 100Ω resistor to lower
device input and output return losses, reduce
component count and further minimize board space.
Typical Application
PE
2
CML
ASIC / FPGA
LVDS
BR120
LVPECL
LVDS
ASIC / FPGA
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS25BR120
SNLS256E – MARCH 2007 – REVISED APRIL 2013
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Block Diagram
PE0 PE1
IN+
OUT+
IN-
OUT-
Pin Diagram
PE1
1
IN+
2
IN-
3
PE0
4
8
VCC
DAP
7
OUT+
GND
6
OUT-
5
NC
WSON Package
PIN DESCRIPTIONS
Pin Name
Pin Name
Pin Type
Pin Description
PE1
1
Input
Pre-emphasis select pin.
IN+
2
Input
Non-inverting LVDS input pin.
IN-
3
Input
Inverting LVDS input pin.
PE0
4
Input
Pre-emphasis select pin.
NC
5
NA
"NO CONNECT" pin.
OUT-
6
Output
Inverting LVDS output pin.
OUT+
7
Output
Non-inverting LVDS Output pin.
VCC
8
Power
Power supply pin.
GND
DAP
Power
Ground pad (DAP - die attach pad)
Pre-Emphasis Truth Table
PE1
PE0
0
0
Pre-emphasis Level
Off
0
1
Low (Approx. 3 dB at 1.56 GHz)
1
0
Medium (Approx. 6 dB at 1.56 GHz)
1
1
High (Approx. 9 dB at 1.56 GHz)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage (VCC)
−0.3V to (VCC + 0.3V)
LVCMOS Input Voltage (PE0, PE1)
LVDS Input Voltage (IN+, IN−)
−0.3V to +4V
Differential Input Voltage |VID|
1.0V
−0.3V to (VCC + 0.3V)
LVDS Output Voltage (OUT+, OUT−)
LVDS Differential Output Voltage ((OUT+) - (OUT−))
0V to 1.0V
LVDS Output Short Circuit Current Duration
5 ms
Junction Temperature
+150°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
NGQ Package
2.08W
Derate NGQ Package
16.7 mW/°C above +25°C
Package Thermal Resistance
θJA
+60.0°C/W
θJC
+12.3°C/W
ESD Susceptibility
HBM (3)
≥7 kV
MM (4)
≥250V
CDM (5)
(1)
(2)
(3)
(4)
(5)
≥1250V
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Human Body Model, applicable std. JESD22-A114C
Machine Model, applicable std. JESD22-A115-A
Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Supply Voltage (VCC)
Receiver Differential Input Voltage (VID)
Operating Free Air Temperature (TA)
Min
Typ
Max
Units
3.0
3.3
3.6
V
0
−40
+25
1.0
V
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
LVCMOS INPUT DC SPECIFICATIONS (PE0, PE1)
VIH
High Level Input Voltage
2.0
VCC
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = 3.6V
VCC = 3.6V
0
±10
μA
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
0
±10
μA
(1)
(2)
(3)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
VCL
Parameter
Conditions
Min
ICL = −18 mA, VCC = 0V
Input Clamp Voltage
Typ
Max
Units
-0.9
−1.5
V
350
450
mV
35
mV
1.375
V
35
mV
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
250
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
RL = 100Ω
IOS
Output Short Circuit Current (4)
OUT to GND
PE0 = PE1 = 0
-35
-55
mA
OUT to VCC
PE0 = PE1 = 0
7
55
mA
RL = 100Ω
-35
1.05
1.2
-35
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
LVDS INPUT DC SPECIFICATIONS (IN+, IN-)
VID
Input Differential Voltage
VTH
Differential Input High Threshold
0
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = 3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor
Between IN+ and IN-
100
Ω
PE0 = 0, PE1 = 0
35
43
mA
Typ
Max
Units
350
465
ps
350
465
ps
VCM = +0.05V or VCC-0.05V
0
−100
1
V
+100
mV
0
0.05
±1
mV
VCC 0.05
V
±10
μA
SUPPLY CURRENT
ICC
(4)
Supply Current
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
AC Electrical Characteristics (1)
Over recommended operating supply and temperature ranges unless otherwise specified. (2) (3)
Symbol
Parameter
Conditions
Min
LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-)
tPHLD
Differential Propagation Delay High to Low
tPLHD
Differential Propagation Delay Low to High
RL = 100Ω
(4)
tSKD1
Pulse Skew |tPLHD − tPHLD|
45
100
ps
tSKD2
Part to Part Skew (5)
45
150
ps
tLHT
Rise Time
80
150
ps
tHLT
Fall Time
80
150
ps
(1)
(2)
(3)
(4)
(5)
4
RL = 100Ω
Specification is ensured by characterization and is not tested in production.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
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AC Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
JITTER PERFORMANCE WITH PE = OFF
tRJ1A
tRJ2A
VID = 350 mV
VCM = 1.2V
Clock (RZ)
PE0 = 0, PE1 = 0
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
PE0 = 0, PE1 = 0
2.5 Gbps
9
31
ps
Deterministic Jitter (Peak to Peak)
No Test Channels (7)
3.125 Gbps
16
40
ps
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
PE0 = 0, PE1 = 0
2.5 Gbps
0.05
0.13
UIP-P
Total Jitter (Peak to Peak)
No Test Channels (8)
3.125 Gbps
0.09
0.16
UIP-P
Random Jitter (RMS Value)
No Test Channels
(6)
tDJ1A
tDJ2A
tTJ1A
tTJ2A
JITTER PERFORMANCE WITH PE = LOW (Figure 5 and Figure 6)
tRJ1B
tRJ2B
VID = 350 mV
VCM = 1.2V
Clock (RZ)
PE0 = 1, PE1 = 0
2.5 Gbps
0.5
1.3
ps
Random Jitter (RMS Value)
Test Channel A (6)
3.125 Gbps
0.5
1.3
ps
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
PE0 = 1, PE1 = 0
2.5 Gbps
17
31
ps
Deterministic Jitter (Peak to Peak)
Test Channel A (7)
3.125 Gbps
18
40
ps
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
PE0 = 1, PE1 = 0
2.5 Gbps
0.09
0.14
UIP-P
Total Jitter (Peak to Peak)
Test Channel A (8)
3.125 Gbps
0.12
0.19
UIP-P
tDJ1B
tDJ2B
tTJ1B
tTJ2B
JITTER PERFORMANCE WITH PE = MEDIUM (Figure 5 and Figure 6)
tRJ1C
tRJ2C
VID = 350 mV
VCM = 1.2V
Clock (RZ)
PE0 = 0, PE1 = 1
2.5 Gbps
0.5
1.2
ps
Random Jitter (RMS Value)
Test Channel B (6)
3.125 Gbps
0.5
1.2
ps
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
PE0 = 0, PE1 = 1
2.5 Gbps
21
44
ps
Deterministic Jitter (Peak to Peak)
Test Channel B (7)
3.125 Gbps
27
48
ps
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
PE0 = 0, PE1 = 1
2.5 Gbps
0.09
0.16
UIP-P
Total Jitter (Peak to Peak)
Test Channel B (8)
3.125 Gbps
0.13
0.23
UIP-P
tDJ1C
tDJ2C
tTJ1C
tTJ2C
JITTER PERFORMANCE WITH PE = HIGH (Figure 5 and Figure 6)
tRJ1D
tRJ2D
VID = 350 mV
VCM = 1.2V
Clock (RZ)
PE0 = 1, PE1 = 1
2.5 Gbps
0.5
1.2
ps
Random Jitter (RMS Value)
Test Channel C (6)
3.125 Gbps
0.5
1.2
ps
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
PE0 = 1, PE1 = 1
2.5 Gbps
30
65
ps
Deterministic Jitter (Peak to Peak)
Test Channel C (7)
3.125 Gbps
30
58
ps
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
PE0 = 1, PE1 = 1
2.5 Gbps
0.09
0.20
UIP-P
Total Jitter (Peak to Peak)
Test Channel C (8)
3.125 Gbps
0.13
0.22
UIP-P
tDJ1D
tDJ2D
tTJ1D
tTJ2D
(6)
(7)
(8)
Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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APPLICATION INFORMATION
DC TEST CIRCUITS
VOH
OUT+
IN+
Power Supply
R
D
RL
Power Supply
IN-
OUTVOL
Figure 1. Differential Driver DC Test Circuit
AC TEST CIRCUITS AND TIMING DIAGRAMS
OUT+
IN+
R
Signal Generator
D
IN-
RL
OUT-
Figure 2. Differential Driver AC Test Circuit
Figure 3. Propagation Delay Timing Diagram
Figure 4. LVDS Output Transition Times
PRE-EMPHASIS TEST CIRCUITS
CHARACTERIZATION
BOARD
50: MS
L=4"
TEST
CHANNEL
DS25BR120
50: MS
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50: MS
50: MS
Figure 5. Pre-emphasis Performance Test Circuit
6
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50: MS
50: MS
L = A, B or C
L=1"
L=1"
L=1"
50: MS
L=1"
100: Diff.
Stripline
50: MS
Figure 6. Test Channel Description
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric
constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:
Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel
Length
(inches)
Insertion Loss (dB)
500 MHz
750 MHz
1000 MHz
1250 MHz
1500 MHz
1560 MHz
A
10
-1.2
-1.7
-2.0
-2.4
-2.7
-2.8
B
20
-2.6
-3.5
-4.1
-4.8
-5.5
-5.6
C
30
-4.3
-5.7
-7.0
-8.2
-9.4
-9.7
D
15
-1.6
-2.2
-2.7
-3.2
-3.7
-3.8
E
30
-3.4
-4.5
-5.6
-6.6
-7.7
-7.9
F
60
-7.8
-10.3
-12.4
-14.5
-16.6
-17.0
Device Operation
INPUT INTERFACING
The DS25BR120 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS25BR120 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS25BR120 inputs are internally terminated with a 100Ω resistor.
100: Differential T-Line
OUT+
IN+
LVDS
DS25BR120
OUT-
IN-
Figure 7. Typical LVDS Driver DC-Coupled Interface to DS25BR120 Input
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CML3.3V or CML2.5V
VCC
50:
100: Differential T-Line
50:
OUT+
IN+
DS25BR120
IN-
OUT-
Figure 8. Typical CML Driver DC-Coupled Interface to DS25BR120 Input
LVPECL
Driver
OUT+
100: Differential T-Line
LVDS
Receiver
IN+
100:
OUT150-250:
IN150-250:
Figure 9. Typical LVPECL Driver DC-Coupled Interface to DS25BR120 Input
OUTPUT INTERFACING
The DS25BR120 outputs signals compliant to the LVDS standard. It can be DC-coupled to most common
differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
and assumes that the receivers have high impedance inputs. While most differential receivers have a common
mode input range that can accommodate LVDS compliant signals, it is recommended to check the respective
receiver's datasheet prior to implementing the suggested interface implementation.
100: Differential T-Line
OUT+
DS25BR120
IN+
CML or
LVPECL or
LVDS
100:
IN-
OUT-
Figure 10. Typical DS25BR120 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
8
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TYPICAL PERFORMANCE CHARACTERISTICS
4.50
4.50
VCC = 3.3V
3.75
MAXIMUM DATA RATE (Gbps)
MAXIMUM DATA RATE (Gbps)
w/ PE and/or EQ
w/ PE
3.00
2.25
w/o PE
1.50
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
TJ = 0.25 UI
0.75
3.00
2.25
1.50
0
3
6
9
12
w/o PE and EQ
0.75
0
0
15
0
6
CAT5e LENGTH (m)
MAXIMUM DATA RATE (Gbps)
SUPPLY CURRENT (mA)
PE = Low
35
PE = Off
30
VCC = 3.3V
3.75
3.00
2.25
w/o PE
1.50
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
TJ = 0.25 UI
0.75
TA = 25°C
0
0
0.4
0.8
1.2
30
w/ PE
40
20
24
4.50
PE = Medium
25
18
Figure 12. Maximum Data Rate as a Function of CAT5e
(Belden 1700A) Length
DS25BR120 Used as a Driver
DS25BR110 Used as a Receiver
PE = High
45
12
CAT5e LENGTH (m)
Figure 11. Maximum Data Rate as a Function of CAT5e
(Belden 1700A) Length
50
TA = 25°C
NRZ PRBS-7
TJ = 0.25 UI
3.75
1.6
2.0
0
3
6
9
12
15
CAT7 LENGTH (m)
FREQUENCY (GHz)
Figure 13. Power Supply Current as a Function of
Frequency
Figure 14. Maximum Data Rate as a Function of CAT7
(Siemon Tera) Length
4.50
Maximum Data Rate (Gbps)
w/ PE and/or EQ
3.75
3.00
2.25
w/o PE and EQ
1.50
VCC = 3.3V
0.75
0
TA =25°C
NRZ PRBS-7
TJ = 0.5 UI
0
6
12
18
24
30
CAT5e LENGTH (m)
Figure 15. Maximum Data Rate as a Function of CAT5e
(Belden 1700A) Length
DS25BR120 Used as a Driver
DS25BR110 Used as a Receiver
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
10
Figure 16. A 2.5 Gbps NRZ PRBS-7 After 40"
Differential FR-4 Stripline
V:125 mV / DIV, H:75 ps / DIV
Figure 17. A 3.125 Gbps NRZ PRBS-7 After 40"
Differential FR-4 Stripline
V:125 mV / DIV, H:50 ps / DIV
Figure 18. An Equalized (with PE) 2.5 Gbps NRZ PRBS-7
After 40"
Differential FR-4 Stripline
V:125 mV / DIV, H:75 ps / DIV
Figure 19. An Equalized (with PE) 3.125 Gbps NRZ PRBS-7
After 40"
Differential FR-4 Stripline
V:125 mV / DIV, H:50 ps / DIV
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
DS25BR120TSD/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WSON
NGQ
8
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
2R120
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS25BR120TSD/NOPB
Package Package Pins
Type Drawing
WSON
NGQ
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
178.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS25BR120TSD/NOPB
WSON
NGQ
8
1000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
NGQ0008A
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
0.8
0.7
SEATING PLANE
0.08 C
1.6 0.1
(0.1) TYP
SYMM
EXPOSED
THERMAL PAD
0.05
0.00
4
5
SYMM
9
2X
1.5
2 0.1
8
1
6X 0.5
8X
PIN 1 ID
8X
0.5
0.3
0.3
0.2
0.1
0.05
C A B
C
4214922/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NGQ0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
(0.75)
8X (0.25)
9
SYMM
(2)
6X (0.5)
5
4
(R0.05) TYP
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214922/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NGQ0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.6)
SYMM
9
METAL
TYP
8
1
8X (0.25)
SYMM
(1.79)
6X (0.5)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214922/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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