Texas Instruments | CLC006 Serial Digital Cable Driver with Adjustable Outputs (Rev. G) | Datasheet | Texas Instruments CLC006 Serial Digital Cable Driver with Adjustable Outputs (Rev. G) Datasheet

Texas Instruments CLC006 Serial Digital Cable Driver with Adjustable Outputs (Rev. G) Datasheet
CLC006
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SNLS015G – AUGUST 1998 – REVISED APRIL 2013
CLC006 Serial Digital Cable Driver with Adjustable Outputs
Check for Samples: CLC006
FEATURES
DESCRIPTION
•
•
•
•
•
•
Texas Instruments' Comlinear CLC006 is a
monolithic, high-speed cable driver designed for the
SMPTE 259M serial digital video data transmission
standard. The CLC006 drives 75Ω transmission lines
(Belden 8281 or equivalent) at data rates up to 400
Mbps. Controlled output rise and fall times (650 ps
typical) minimize transition-induced jitter. The output
voltage swing, typically 1.65V, set by an accurate,
low-drift internal bandgap reference, delivers an 800
mV swing to back-matched and terminated 75Ω
cable. Output swing is adjustable from 0.7 VP-P to 2
VP-P using external resistors.
1
2
No External Pull-down Resistors
Adjustable Output Amplitude
Differential Input and Output
Low Power Dissipation
Single +5V or −5.2V Supply
Replaces GS9008 in Most Applications
APPLICATIONS
•
•
•
•
•
•
Digital Routers and Distribution Amplifiers
Coaxial Cable Driver for Digital Transmission
Line
Twisted Pair Driver
Serial Digital Video Interfaces for the
Commercial and Broadcast Industry
SMPTE, Sonet/SDH, and ATM Compatible
Driver
Buffer Applications
The CLC006’s class AB output stage consumes less
power than other designs, 185 mW with both outputs
terminated, and requires no external bias resistors.
The differential inputs accept a wide range of digital
signals from 200 mVP-P to ECL levels within the
specified common-mode limits. All this make the
CLC006 an excellent general purpose high speed
driver for digital applications.
The CLC006 is powered from a single +5V or −5.2V
supply and comes in an 8-pin SOIC package.
KEY SPECIFICATIONS
•
•
•
•
650 ps Rise and Fall Times
Data Rates to 400 Mbps
200 mV Differential Input
Low Residual Jitter (25 pspp)
Typical Application
VCC
REXT
75:
75:
8
4
7
+
VIN-
3
1
75:
0.1 PF
75: Coax
CLC006
6
VIN+
-
V0
V0
2
75:
0.1 PF
75: Coax
75:
75:
5
154:
154:
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
CLC006
SNLS015G – AUGUST 1998 – REVISED APRIL 2013
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Connection Diagram
270 Mbps Eye Pattern
0
1
2
3
4
5
Q0 1
8 VCC
Q0 2
7 VIN+
REXT-H 3
6 VIN-
REXT-L 4
5 VEE
6
TIME (1 ns/Div)
Figure 2. 8-Pin SOIC
See Package Number D
Figure 1.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage
6V
Output Current
30 mA
Maximum Junction Temperature
+125°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature
(Soldering 10 Seconds)
+300°C
ESD Rating (Human Body Model)
Package Thermal Resistance
Reliability Information
(1)
(2)
1000V
θJA 8–pin SOIC
+160°C/W
θJC 8–pin SOIC
+105°C/W
MTTF
254 Mhr
Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Supply Voltage Range (VCC – VEE)
2
+4.5V to +5.5V
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Electrical Characteristics
(VCC = 0V, VEE = −5V; unless otherwise specified).
Parameter
Condition
Typ +25°C
Min/Max
+25°C (1)
Min/Max
0°C to
+70°C (1)
Min/Max
−40°C to
+85°C (1)
Units
37
—
—
—
mA
STATIC DC PERFORMANCE
Supply Current, Loaded
150Ω @ 270 Mbps
(2)
Supply Current, Unloaded
(3)
34
28/45
26/47
26/47
mA
Output HIGH Voltage (VOH)
(3)
−1.7
−2.0/1.4
−2.0/1.4
−2.0/1.4
V
Output LOW Voltage (VOL)
(3)
−3.3
−3.6/3.0
−3.6/3.0
−3.6/3.0
V
10
30
50
50
μA
1.65
1.55/1.75
1.53/1.77
1.51/1.79
V
1.30
—
—
—
V
Common Mode Input Range Upper Limit
−0.7
−0.8
−0.8
−0.8
V
Common Mode Input Range Lower Limit
−2.6
−2.5
−2.5
–2.5
V
Minimum Differential Input Swing
200
200
200
200
mV
26
20
20
20
dB
650
425/825
400/850
400/850
ps
Input Bias Current
(3)
Output Swing
REXT = ∞
Output Swing
REXT = 10 kΩ
Power Supply Rejection Ratio
(3)
AC PERFORMANCE
Output Rise and Fall Time
(3) (4) (2)
Overshoot
5
%
Propagation Delay
1.0
ns
Duty Cycle Distortion
50
Residual Jitter
25
ps
—
—
—
pspp
MISCELLANEOUS PERFORMANCE
Input Capacitance
1.0
Output Resistance
10
Ω
Output Inductance
6
nH
(1)
(2)
(3)
(4)
pF
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality
levels are determined from tested parameters.
Measured with both outputs driving 150Ω, AC coupled at 270 Mbps.
Spec is 100% tested at +25°C
Measured between the 20% and 80% levels of the waveform.
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Operation
INPUT INTERFACING
The CLC006 has high impedance, emitter-follower buffered, differential inputs. Single-ended signals may also be
input. Transmission lines supplying input signals must be properly terminated close to the CLC006. Either A.C. or
D.C. coupling as in Figure 4 or Figure 5 may be used. Figure 4, Figure 6 and Figure 7 show how Theveninequivalent resistor networks are used to provide input termination and biasing. The input D.C. common-mode
voltage range is 0.8V to 2.5V below the positive power supply (VCC). Input signals plus bias should be kept within
the specified common-mode range. For an 800 mVP-P input signal, typical input bias levels range from 1.2V to
2.1V below the positive supply.
Resistor to VCC (R1)
Resistor to VEE (R2)
ECL, 50Ω, 5V, VT=2V
Load Type
82.5Ω
124Ω
ECL, 50Ω, 5.2V, VT=2V
80.6Ω
133Ω
ECL, 75Ω, 5V, VT=2V
124Ω
187Ω
ECL, 75Ω, 5.2V, VT=2V
121Ω
196Ω
800 mVP-P, 50Ω, 5V, VT=1.6V
75.0Ω
154Ω
800 mVP-P, 75Ω, 5V, VT=1.6V
110Ω
232Ω
800 mVP-P, 2.2KΩ, 5Ω, VT=1.6V
3240Ω
6810Ω
VCC
VIN+
VIN-
To next
stage
VEE
Figure 3. Input Stage
VCC
VCC
ECL Output
Z0
R1
R1
0.1 PF
8
4
7
3
+
1
CLC006
6
VTT
Z0
2
-
0.1 PF
5
R2
R2
VTT
VEE
VEE
Figure 4. AC Coupled Input
4
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VCC
ECL Output
Z0
8
4
7
3
+
1
CLC006
6
Z0
= Z0
= Z0
VTT
2
5
VEE
Figure 5. DC Coupled Input
VCC
R5
75:
R4
75:
VCC
R5
75:
U1
8
4
7
J1
3
+
1
R4
75:
U1
8
4
7
J1
VIN+
CLC006
R3
154:
6
-
R1
154:
5
3
+
1
CLC006
2
J2
VINR3
154:
VEE
6
-
R1
154:
5
2
VEE
Figure 6. Single Ended 50Ω ECL input
Figure 7. Differential 50Ω ECL Input
OUTPUT INTERFACING
The CLC006’s class AB output stage, Figure 8, requires no standing current in the output transistors and
therefore requires no biasing or pull-down resistors. Advantages of this arrangement are lower power dissipation
and fewer external components. The output may be either D.C. or A.C. coupled to the load. A bandgap voltage
reference sets output voltage levels which are compatible with F100K and 10K ECL when correctly terminated.
The outputs do not have the same output voltage temperature coefficient as 10K. Therefore, noise margins will
be reduced over the full temperature range when driving 10K ECL. Noise margins will not be affected when
interfacing to F100K since F100K is fully voltage and temperature compensated.
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VCC
VEE
VCC
VEE
Figure 8. Output Stage
VCC
VCC - VEE = +5V
for 75: input:
R1 = R3 = 232:
R4 = R5 = 110:
R5
75:
C6
33 pF
C5
33 pF
R4
75:
8
4
7
J1
VIN+
75: Coax
3
+
1
R6
75:
CLC006
J2
VINR3
154:
6
-
R1
154:
5
75:
2
R7
75:
75: Coax
75:
RIN = 50:
VBIAS = VCC - 1.62V
VEE
Figure 9. Differential Input DC Coupled Output
6
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SNLS015G – AUGUST 1998 – REVISED APRIL 2013
OUTPUT AMPLITUDE ADJUSTMENT
The high and low output levels of the CLC006 are set by a circuit shown simplified in Figure 10. Output high and
low levels may be set independently with external resistor networks connected between REXT-H (pin 3), REXT-L (pin
4) and the power supplies. The resistor networks affect the high and low output levels by changing the internally
generated bias voltages, VH and VL. The nominal high and low output levels are VCC−1.7V and VCC−3.3V,
respectively, when the pins REXT-H and REXT-L are left unconnected. Though the internal components which
determine output voltage levels have accurate ratios, their absolute values may be controlled only within about
±15% of nominal. Even so, without external adjustment, output voltages are well controlled. A final design should
accommodate the variation in externally set output voltages due to the CLC006’s part-to-part and external
component tolerances.
Output voltage swing may be reduced with the circuit shown in Figure 11. A single resistance chosen with the aid
of the graph, Figure 12, is connected between pins 3 and 4. Output voltage swing may be increased with the
circuit of Figure 13. Figure 14 is used to estimate a value for resistor R. Note that both of these circuits and the
accompanying graphs assume that the CLC006 is loaded with the standard 150Ω. Be aware that output loading
will affect the output swing and the high and low levels. It may be necessary to empirically select resistances
used to set output levels when the D.C. loading on the CLC006 differs appreciably from 150Ω.
VCC
REXT-H
3.4 k:
3
VCC - 1.7V
VH
VCC - 3.3V
VL
1 k:
REXT-L
3.15 k:
1 k:
4
0.5 mA
VEE
Figure 10. Equivalent Bias Generation Circuit
VCC
VR1
10k
R5
75:
R4
75:
8
4
7
J1
VIN+
3
+
1
R6
75:
C1
0.1 PF
J3
R7
75:
C2
0.1 PF
J4
CLC006
J2
VINR3
154:
6
-
R1
154:
5
2
VEE
Figure 11. Differential Input Reduced Output
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1800
OUTPUT VOLTAGE (mV)
1600
Max.
1400
1200
Min.
1000
Typ.
800
600
1
10
100
RESISTANCE (k:)
Figure 12. Resistance Pins 3 to 4 vs Output Voltage Reduced Output @ 150Ω Load
VCC
R12
3k
R4
82.5:
7
R5
82.5:
J1
VIN+
R11
2.4k
R
VEE
8
3
4
+
1
R6
75:
C1
0.1 PF
J3
R7
75:
C2
0.1 PF
J4
CLC006
J2
VINR3
124:
6
-
R1
124:
5
2
VEE
Figure 13. Differential Input Increased Output
2500
OUTPUT VOLTAGE (mV)
Max.
2000
Min.
1500
Typ.
1000
500
0.1
1
10
100
1000
RESISTANCE (k:)
Figure 14. Resistance Pins 3 to 4 vs Output Voltage Increased Output @ 150Ω Load
8
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SNLS015G – AUGUST 1998 – REVISED APRIL 2013
OUTPUT RISE AND FALL TIMES
Output load capacitance can significantly affect output rise and fall times. The effect of load capacitance, stray or
otherwise, may be reduced by placing the output back-match resistor close to the output pin and by minimizing
all interconnecting trace lengths. Figure 15 shows the effect on risetime of parallel load capacitance across a
150Ω load.
OUTPUT CAPACITANCE (pFd)
50
40
30
20
10
0
500
1000
1500
2000
2500
3000
RISE TIME (ps)
Figure 15. Rise Time vs CL
PCB Layout Recommendations
Printed circuit board layout affects the performance of the CLC006. The following guidelines will aid in achieving
satisfactory device performance.
• Use a ground plane or power/ground plane sandwich design for optimum performance.
• Bypass device power with a 0.01 µF monolithic ceramic capacitor in parallel with a 6.8 µF tantalum
electrolytic capacitor located no more than 0.1” (2.5 mm) from the device power pins.
• Provide short, symmetrical ground return paths for:
– inputs,
– supply bypass capacitors and
– the output load.
• Provide short, grounded guard traces located
– under the centerline of the package,
– 0.1” (2.5 mm) from the package pins
– on both top and bottom of the board with connecting vias.
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REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
•
10
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
CLC006BM/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
CLC00
6BM>D
CLC006BMX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
CLC00
6BM>D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
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11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CLC006BMX/NOPB
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.4
2.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLC006BMX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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