Texas Instruments | SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor (Rev. G) | Datasheet | Texas Instruments SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor (Rev. G) Datasheet

Texas Instruments SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor (Rev. G) Datasheet
SCANSTA476
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SNLS171G – JANUARY 2005 – REVISED APRIL 2013
SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor
Check for Samples: SCANSTA476
FEATURES
DESCRIPTION
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•
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The SCANSTA476 is a low power, Analog Voltage
Monitor used for sampling or monitoring up to 8
analog/mixed-signal input channels. Analog Voltage
Monitors are valuable during product development,
environmental test, production, and field service for
verifying and monitoring power supply and reference
voltages. In a supervisory role, the 'STA476 is useful
for card or system-level health monitoring and
prognostics applications.
1
2
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Eight Selectable Analog Input Channels
Analog Full-Scale Input Range 0V to VDD
Typical Accuracy of 2 mV at Maximum VDD
Very Low Power Operation
Small Package Footprint in 16-Lead, 5 x 5 x 0.8
mm WSON
Single +2.7V to +5.5V Supply Operation
IEEE 1149.1 (JTAG) Compliant Interface
APPLICATIONS
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•
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Measurement of Point Voltages
Real-time Signal Monitoring
System Health Monitoring and Prognostics
Debug, Environmental Test, Production Test,
Field Service
Supplement In-Circuit Tester (ICT) Access
Vital in Servers, Computing,
Telecommunication and Industrial Equipment
Essential in Medical, Data Storage, and
Networking Equipment
Instead of requiring an external microcontroller with a
GPIO interface, the 'STA476 features a common
IEEE 1149.1 (JTAG) interface to select the analog
input, initiate a measurement, and access the results
- further extending the capabilities of an existing
JTAG infrastructure.
The SCANSTA476 uses the VREF input as a
reference. This enables the SCANSTA476 to operate
with a full-scale input range of 0 to VDD, which can
range from +2.7V to +5.5V.
The SCANSTA476 is packaged in a 16-lead nonpullback WSON package that provides an extremely
small footprint for applications where space is a
critical consideration. This product operates over the
industrial temperature range of −40°C to +85°C.
Block Diagram
VREF
A0
A1
A2
A3
A4
A5
A6
A7
Successive
Approximation
ADC
Control
Logic
IEEE 1149.1
TAP (JTAG)
TDI TDO TCK TMS TRST
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
SCANSTA476
SNLS171G – JANUARY 2005 – REVISED APRIL 2013
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Connection Diagram
VDD
1
16
A0
VREF
2
15
A1
VDD
3
14
A2
TRST
4
13
A3
TDO
5
12
A4
TDI
6
11
A5
TMS
7
10
A6
TCK
8
9
A7
DAP
(GND)
Figure 1. DAP = GND
(Top View)
Pin Descriptions
Pin No.
Symbol
Description
ANALOG I/O
16
A0
Analog input 0. This signal can range from 0V to VREF.
15
A1
Analog input 1. This signal can range from 0V to VREF.
14
A2
Analog input 2. This signal can range from 0V to VREF.
13
A3
Analog input 3. This signal can range from 0V to VREF.
12
A4
Analog input 4. This signal can range from 0V to VREF.
11
A5
Analog input 5. This signal can range from 0V to VREF.
10
A6
Analog input 6. This signal can range from 0V to VREF.
9
A7
Analog input 7. This signal can range from 0V to VREF.
2
VREF
Analog reference voltage input. VREF must be ≤ VDD. This pin should be connected to a quiet source
(not directly to VDD) and bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1
cm of the VREF pin.
6
TDI
Test Data Input to support IEEE 1149.1 features
5
TDO
Test Data Ouput to support IEEE 1149.1 features
7
TMS
Test Mode Select to support IEEE 1149.1 features
8
TCK
Test Clock to support IEEE 1149.1 features
4
TRST
Test Reset to support IEEE 1149.1 features
DIGITAL I/O
POWER SUPPLY
1,3
See
(1)
2
(1)
VDD
Positive supply pin. These pins should be connected to a quiet +2.7V to +5.5V source and bypassed to
GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the power pin.
GND
Ground reference for CMOS circuitry. DAP is the exposed metal contact at the bottom of the WSON
package. The DAP is used as the primary GND connection to the device. It should be connected to the
ground plane with at least 4 vias for optimal low-noise and thermal performance.
Note that GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the WSON package.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
−0.3V to +6.5V
Supply Voltage VDD
Voltage on Any Analog Pin to GND
−0.3V to VDD+0.3V
Voltage on Any Digital Pin to GND
-0.3V to VDD+0.3V
Input Current at Any Pin
(3)
±10 mA
ESD Susceptibility
Human Body Model
8000V
Machine Model
>250V
Soldering Temperature
Refer to AN-1187 (SNOA401)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Thermal Resistance, θJA
42°C/W
Thermal Resistance, θJC
14.3°C/W
(1)
(2)
(3)
Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may
affect device reliability.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Except power supply pins.
Recommended Operating Conditions
−40°C ≤ TA ≤ +85°C
Operating Temperature Range
VDD Supply Voltage
+2.7V to +5.5V
Digital Input Pins Voltage Range
Analog Input Pins Voltage Range
(1)
+0V to VDD
(1)
+0V to VREF
For valid measurements, the analog VIN < VREF ≤ VDD.
SCANSTA476 Electrical Characteristics
The following specifications apply for VDD = +2.7V to 5.5V, fTCK = 20 MHz, unless otherwise noted.
Symbol
Parameter
Conditions
Typical
Limits
Units
2.7
V (min)
5.5
V (max)
5.0
mA
POWER SUPPLY CHARACTERISTICS
VDD
IDD
PD
Supply Voltage
−40°C ≤ TA ≤ 85°C
Normal Mode (Static)
VDD = +2.7V to +5.5V,
Normal Mode (Operational)
VDD = +2.7V to +5.5V,
fTCK = 1 MSPS
5.0
mA (max)
Power Consumption, Normal Mode
(Operational)
VDD = +5.5V, fTCK = 1 MSPS
27.5
mW (max)
0 to VREF
V
3.5
ANALOG INPUT CHARACTERISTICS (A0-A7)
VIN
Analog Input Range
VREF
Reference Voltage Range
IDCL
DC Leakage Current
VMEAS
Analog Input Measurement Accuracy
VREF ≤ VDD
VDD
V
0.1
±10
µA (max)
VDD = +2.7V
1
7.5
VDD = +5.5V
2
15
mV
DIGITAL INPUT CHARACTERISTICS (TDI, TMS, TCK, TRST)
VDD = +2.7V to +3.6V
2.0
VDD = +5.5V
2.1
VIH
Input High Voltage
V (min)
VIL
Input Low Voltage
VDD = +5V
0.8
V (max)
VCL
Input Clamp Voltage
ICL = -18mA
-0.8
-1.5
V (max)
IIN
Input Current
VIN = 0V or VDD
0.2
±10
µA (max)
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SCANSTA476
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SCANSTA476 Electrical Characteristics (continued)
The following specifications apply for VDD = +2.7V to 5.5V, fTCK = 20 MHz, unless otherwise noted.
Symbol
IILR
Parameter
Conditions
Input Current
Typical
TRST, TDI, TMS only
Limits
Units
-300
µA (max)
DIGITAL OUTPUT CHARACTERISTICS (TDO)
IOH = -100 µA, 2.7V ≤ VDD ≤ 5.5V
VOH
Output High Voltage
VOL
Output Low Voltage
IOS
Output Short Circuit Current
IOZ
TRI-STATE Leakage Current
VDD −0.2
V (min)
IOH = -4 mA, 3.0V ≤ VDD ≤ 5.5V
2.4
V (min)
IOH = -4 mA, VDD = 2.7V
2.2
V (min)
IOL = 100 µA, 2.7V ≤ VDD ≤ 5.5V
0.2
V (max)
IOL = 4 mA, 2.7V ≤ VDD ≤ 5.5V
0.4
V (max)
-85
mA (max)
±10
µA (max)
VOUT = 0V, VDD = 5.5V
Output Coding
Straight (Natural) Binary
AC ELECTRICAL CHARACTERISTICS
FMAX
Throughput Rate
TCK = 20MHz
1
MSPS (max)
INPUT TIMING CHARACTERISTICS
tSET
TDI to TCK (H/L)
See
(1)
2.0
ns (min)
1.5
ns (min)
2.0
ns (min)
2.0
ns (min)
10.0
ns (min)
2.0
ns (min)
2.5
ns (min)
20
MHz (min)
tHOLD
TDI to TCK (H/L)
See
(1)
tSET
TMS to TCK (H/L)
See
(1)
tHOLD
TMS to TCK (H/L)
See
tW
TCK Pulse Width (H/L)
See
tREC
Recovery TIme TRST to TCK
See
tW
TRST Pulse Width (L)
See
FMAX
TCK
(1)
(1)
(1)
(1)
(1)
Data sheet min/max specification limits are specified by design or statistical analysis.
APPLICATIONS INFORMATION
POWER-UP TIMING
The SCANSTA476 typically requires 1 µs to power up, either after first applying VDD, or after an incomplete
conversion shift. To return to normal, one "dummy" conversion must be fully completed. After this first dummy
conversion, the SCANSTA476 will perform conversions properly.
STARTUP MODE
When the VDD supply is first applied, the SCANSTA476 requires one dummy conversion after start-up.
4
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Timing Diagrams
JTAG Reset
TAP
State
TLR (Test-Logic-Reset)
JTAG Instruction Shift
RTI
SEL
DR
SEL
IR
CAP
IR
(IDLE)
EX1
IR
SHIFT IR
UPD
IR
RTI (Run-Test/Idle)
TCK
TRST
TMS
8-bit instruction register op-code (40h to 47h)
TDI
x
x
x
x
0
0
1
0
0
1
8-bit instruction register capture value (81h)
TDO
1
0
0
0
0
0
LSB
MSB
Op-codes 40h to 47h select pins A0 to A7 respectively.
Note the JTAG reset preamble places the JTAG TAP controller in a stable state (RTI). Both the instruction and data shifts start in - and return to - the RTI state
Figure 2. Instruction Shift (Channel Select)
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(IDLE)
TAP
State
RTI
JTAG Data Shift
SEL CAP
DR DR
(IDLE)
EX1 UPD
DR DR
SHIFT DR
RTI
TCK
TRST
TMS
(GRQ¶W FDUH)
TDI
TDO
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
MSB
D3
D2
D1
D0
LSB
D11 through D0 correspond to the 12-bit sample from the ADC Core.
Note that Data shifts can be run back-to-back for continous sampling of a single channel, or can be interleaved with instruction shifts for rippling through all 8 channels.
Figure 3. Data Shift (A/D Sample)
6
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SNLS171G – JANUARY 2005 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 6
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PACKAGE OPTION ADDENDUM
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7-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
SCANSTA476TSD/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WSON
NHQ
16
1000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
CU SN
Level-3-260C-168 HR
(4/5)
-40 to 85
STA476T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
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20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SCANSTA476TSD/NOPB
Package Package Pins
Type Drawing
WSON
NHQ
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
178.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.3
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
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20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SCANSTA476TSD/NOPB
WSON
NHQ
16
1000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NHQ0016A
SDA16A (Rev A)
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