Texas Instruments | SCAN15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer w/Pre-Emphasis & IEEE 1149.6 (Rev. E) | Datasheet | Texas Instruments SCAN15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer w/Pre-Emphasis & IEEE 1149.6 (Rev. E) Datasheet

Texas Instruments SCAN15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer w/Pre-Emphasis & IEEE 1149.6 (Rev. E) Datasheet
SCAN15MB200
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SNLS188E – NOVEMBER 2005 – REVISED APRIL 2013
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6
Check for Samples: SCAN15MB200
FEATURES
DESCRIPTION
•
•
The SCAN15MB200 is a dual-port 2 to 1 multiplexer
and 1 to 2 repeater/buffer. High-speed data paths
and flow-through pinout minimize internal device jitter
and simplify board layout, while pre-emphasis
overcomes ISI jitter effects from lossy backplanes
and cables. The differential inputs and outputs
interface to LVDS or Bus LVDS signals such as those
on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, or to
CML or LVPECL signals.
1
2
•
•
•
•
•
•
•
•
•
1.5 Gbps Data Rate Per Channel
Configurable Off/On Pre-emphasis Drives
Lossy Backplanes and Cables
LVDS/BLVDS/CML/LVPECL Compatible Inputs,
LVDS Compatible Outputs
Low Output Skew and Jitter
On-chip 100Ω Input and Output Termination
IEEE 1149.1 and 1149.6 Compliant
15 kV ESD Protection on LVDS Inputs/Outputs
Hot Plug Protection
Single 3.3V Supply
Industrial -40 to +85°C Temperature Range
48-Pin WQFN Package
Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry
supports
testability
of
both
single-ended
LVTTL/CMOS and high-speed differential PCB
interconnects. The 3.3V supply, CMOS process, and
robust I/O ensure high performance at low power
over the entire industrial -40 to +85°C temperature
range.
Switch
Fabric B
Mux Buffer
LVDS
LVDS
Switch
Fabric A
Backplane or Cable
Typical Application
FPGA
or
ASIC
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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SCAN15MB200
SNLS188E – NOVEMBER 2005 – REVISED APRIL 2013
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Block Diagram
PREA_0
ENA_0
PREB_0
ENB_0
SOA_0
LI_0
SOB_0
PREL_0
ENL_0
SIA_0
LO_0
SIB_0
MUX_S0
Channel 0
Channel 1
TDI
TDO
TCK
TMS
TRST
IEEE 1149.1 (JTAG)
Test Access Port,
1149.6, Fault Insertion
Figure 1. SCAN15MB200 Block Diagram
Pin Descriptions
Pin
Name
WQFN Pin
Number
I/O, Type
Description
SWITCH SIDE DIFFERENTIAL INPUTS
SIA_0+
SIA_0−
30
29
I, LVDS
Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SIA_1+
SIA_1−
19
20
I, LVDS
Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SIB_0+
SIB_0−
28
27
I, LVDS
Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SIB_1+
SIB_1−
21
22
I, LVDS
Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
LINE SIDE DIFFERENTIAL INPUTS
LI_0+
LI_0−
40
39
I, LVDS
Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
LI_1+
LI_1−
9
10
I, LVDS
Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SWITCH SIDE DIFFERENTIAL OUTPUTS
SOA_0+
SOA_0−
34
33
O, LVDS
Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
(1) (2)
SOA_1+
SOA_1−
15
16
O, LVDS
Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
(1) (2)
SOB_0+
SOB_0−
32
31
O, LVDS
Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
(1) (2)
SOB_1+
SOB_1−
17
18
O, LVDS
Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
(1) (2)
(1)
(2)
2
.
.
.
.
For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).
The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN15MB200 device
have been optimized for point-to-point backplane and cable applications.
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Pin Descriptions (continued)
Pin
Name
WQFN Pin
Number
I/O, Type
Description
LINE SIDE DIFFERENTIAL OUTPUTS
LO_0+
LO_0−
42
41
O, LVDS
Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
(3) (4)
LO_1+
LO_1−
7
8
O, LVDS
Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
(3) (4)
.
.
DIGITAL CONTROL INTERFACE
MUX_S0
MUX_S1
38
11
I, LVTTL
Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through
to the Line-side.
PREA_0
PREA_1
PREB_0
PREB_1
26
23
25
24
I, LVTTL
Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side and Bside has a separate pin to control the pre-emphasis on or off.
PREL_0
PREL_1
44
5
I, LVTTL
Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and B-side
has a separate pin to control the pre-emphasis on or off.
ENA_0
ENA_1
ENB_0
ENB_1
36
13
35
14
I, LVTTL
Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and
B-side has a separate enable pin.
ENL_0
ENL_1
45
4
I, LVTTL
Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate
enable pin.
TDI
2
I, LVTTL
Test Data Input to support IEEE 1149.1 features
TDO
1
O, LVTTL
Test Data Output to support IEEE 1149.1 features
TMS
46
I, LVTTL
Test Mode Select to support IEEE 1149.1 features
TCK
47
I, LVTTL
Test Clock to support IEEE 1149.1 features
TRST
3
I, LVTTL
Test Reset to support IEEE 1149.1 features
6, 12, 37,
43, 48
I, Power
VDD = 3.3V ±0.3V.
I, Power
Ground reference for LVDS and CMOS circuitry.
For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is
the exposed metal contact at the bottom of the WQFN-48 package. It should be connected to the
ground plane with at least 4 vias for optimal AC and thermal performance.
POWER
VDD
GND
(3)
(4)
(5)
See
(5)
For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).
The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN15MB200 device
have been optimized for point-to-point backplane and cable applications.
Note that the DAP on the backside of the WQFN package is the primary GND connection for the device when using the WQFN
package.
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VDD
PREL_1
ENL_1
TRST
TDI
TDO
ENB_1
LO-1+
12 11 10
13
LO_1-
ENA_1
LI_1+
LI_1-
MUX_S1
VDD
Connection Diagram
9
8
7
6
5
4
3
2
1
48
VDD
14
47
TCK
SOA_1+
15
46
TMS
SOA_1-
16
45
ENL_0
SOB_1+
17
44
PREL_0
SOB_1-
18
43
VDD
SIA_1+
19
42
LO_0+
DAP
(GND)
SIA_1-
20
41
LO_0-
SIB_1+
21
40
LI_0+
VDD
ENA_0
ENB_0
SOA_0+
SOA_0-
SOB_0+
SOB_0-
37
24
25 26 27 28 29 30 31 32 33 34 35 36
SIA_0+
PREB_1
SIA_0-
MUX_S0
SIB_0+
LI_0-
38
SIB_0-
39
23
PREA_0
22
PREB_0
SIB_1PREA_1
TDO
TDI
TRST
ENL_1
PREL_1
VDD
LO-1+
LO_1-
LI_1+
LI_1-
MUX_S1
VDD
WQFN Top View
DAP = GND
VDD
ENA_1
Channel 1
ENB_1
TCK
SOA_1+
TMS
SOA_1-
ENL_0
PREL_0
SOB_1+
Channel 0
SOB_1-
VDD
SIA_1+
LO_0+
SIA_1-
LO_0-
SIB_1+
LI_0+
SIB_1-
LI_0-
ENA_0
ENB_0
SOA_0+
SOA_0-
SOB_0+
SOB_0-
SIA_0+
SIA_0-
SIB_0+
VDD
SIB_0-
PREB_1
PREA_0
MUX_S0
PREB_0
PREA_1
Directional Signal Paths Top View
(Refer to pin names for signal polarity)
4
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OUTPUT CHARACTERISTICS
The output characteristics of the SCAN15MB200 have been optimized for point-to-point backplane and cable
applications, and are not intended for multipoint or multidrop signaling.
A 100Ω output (source) termination resistor is incorporated in the device to eliminate the need for an external
resistor, providing excellent drive characteristics by locating the source termination as close to the output as
physically possible.
Pre-Emphasis Controls
The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for
each output to minimize power consumption. Pre-emphasis is programmable to be off or on per the Preemphasis Control Table.
PREx_n
(1)
(1)
Output Pre-emphasis
0
0%
1
100%
Applies to PREA_0, PREA_1, PREB_0, PREB_1, PREL_0, PREL_1
Multiplexer Truth Table
Data Inputs
(1)
(2)
(3)
(1) (2)
Control Inputs
SIA_0
SIB_0
MUX_S0
ENL_0
LO_0
X
valid
0
1
SIB_0
valid
X
1
1
SIA_0
X
X
X
Data Input
(3)
0
(3)
Z
Same functionality for channel 1
X = Don't Care
Z = High Impedance (TRI-STATE)
When all enable inputs from both channels are Low, the device
enters a powerdown mode. Refer to the applications section titled
TRI-STATE and Powerdown Modes.
Repeater/Buffer Truth Table
(1)
(2)
Output
(1) (2)
Control Inputs
Outputs
LI_0
ENA_0
ENB_0
X
0
0
SOA_0
valid
0
1
Z
valid
1
0
LI_0
Z
valid
1
1
LI_0
LI_0
Z
(3)
SOB_0
Z
(3)
LI_0
Same functionality for channel 1
X = Don't Care
Z = High Impedance (TRI-STATE)
When all enable inputs from both channels are Low, the device
enters a powerdown mode. Refer to the applications section titled
TRI-STATE and Powerdown Modes.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings
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(1)
Value
Unit
Supply Voltage (VDD)
−0.3V to +4.0
V
CMOS Input Voltage
-0.3V to (VDD+0.3)
V
-0.3V to (VDD+0.3)
V
LVDS Receiver Input Voltage
(2)
LVDS Driver Output Voltage
-0.3V to (VDD+0.3)
V
+40
mA
Junction Temperature
+150
°C
Storage Temperature
LVDS Output Short Circuit Current
−65°C to +150
°C
Lead Temperature (Solder, 4sec)
260
°C
Max Pkg Power Capacity @ 25°C
5.2
W
Thermal Resistance (θJA)
Package Derating above +25°C
ESD Last Passing Voltage
HBM, 1.5kΩ, 100pF
LVDS pins to GND only
EIAJ, 0Ω, 200pF
CDM
(1)
(2)
24
°C/W
41.7
mW/°C
8
kV
15
kV
250
V
1000
V
Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI
does not recommend operation of products outside of recommended operation conditions.
VID max < 2.4V
Recommended Operating Conditions
Min
Max
Supply Voltage (VCC)
Unit
3.0
3.6
V
(1)
0
VCC
V
Output Voltage (VO)
0
VCC
V
−40
+85
°C
Input Voltage (VI)
Operating Temperature (TA) Industrial
(1)
VID max < 2.4V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(1)
Max
Units
LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n, TDI, TDO, TCK, TMS, TRST)
VIH
High Level Input Voltage
2.0
VDD
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = VDD = VDDMAX
−10
+10
µA
IIHR
High Level Output Current
PREA_n, PREB_n, PREL_n
40
200
µA
IIL
Low Level Input Current
VIN = VSS, VDD = VDDMAX
−10
+10
µA
IILR
Low Level Input Current
TDI, TMS, TRST
-40
-200
µA
CIN1
Input Capacitance
Any Digital Input Pin to VSS
COUT1
Output Capacitance
Any Digital Output Pin to VSS
VCL
Input Clamp Voltage
ICL = −18 mA
−1.5
VOH
High Level Output Voltage
(TDO)
IOH = −12 mA, VDD = 3.0 V
2.4
IOH = −100 µA, VDD = 3.0 V
VDD-0.2
VOL
Low Level Output Voltage
(TDO)
IOL = 12 mA, VDD = 3.0 V
0.5
V
IOL = 100 µA, VDD = 3.0 V
0.2
V
IOS
Output Short Circuit Current
TDO
-15
-125
mA
IOZ
Output TRI-STATE Current
TDO
-10
+10
µA
(1)
6
V
2.0
pF
4.0
pF
−0.8
V
V
V
Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(1)
Max
Units
100
mV
LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±)
(2)
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VID
Differential Input Voltage
VCM = 0.8V to 3.55V, VDD = 3.6V
100
2400
mV
VCMR
Common Mode Voltage Range
VID = 150 mV, VDD = 3.6V
0.05
3.55
V
CIN2
Input Capacitance
IN+ or IN− to VSS
IIN
Input Current
VIN = 3.6V, VDD = VDDMAX or 0V
−15
+15
µA
VIN = 0V, VDD = VDDMAX or 0V
−15
+15
µA
500
mV
35
mV
1.475
V
35
mV
-40
mA
(2)
VCM = 0.8V or 1.2V or 3.55V,
VDD = 3.6V
0
VCM = 0.8V or 1.2V or 3.55V,
VDD = 3.6V
−100
0
mV
2.0
pF
LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±)
VOD
Differential Output Voltage,
0% Pre-emphasis (2)
RL is the internal 100Ω between OUT+
and OUT−
ΔVOD
Change in VOD between
Complementary States
VOS
Offset Voltage
ΔVOS
Change in VOS between
Complementary States
IOS
Output Short Circuit Current
OUT+ or OUT− Short to GND
−21
COUT2
Output Capacitance
OUT+ or OUT− to GND when TRISTATE
4.0
All inputs and outputs enabled and
active, terminated with differential load of
100Ω between OUT+ and OUT-.
225
275
mA
ENA_0 = ENB_0 = ENL_0= ENA_1 =
ENB_1 = ENL_1 = L
0.6
4.0
mA
170
250
ps
170
250
ps
1.0
2.5
ns
1.0
2.5
ns
25
75
ps
50
115
ps
1.1
1.5
psrms
20
34
psp-p
14
28
psp-p
250
360
-35
(3)
1.05
1.22
-35
pF
SUPPLY CURRENT (Static)
ICC
Supply Current
ICCZ
Supply Current - Powerdown Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT
Differential Low to High Transition
Time
tHLT
Differential High to Low Transition
Time
tPLHD
Differential Low to High Propagation
Delay
tPHLD
Differential High to Low Propagation
Delay
tSKD1
Pulse Skew
|tPLHD–tPHLD|
tSKCC
Output Channel to Channel Skew
Difference in propagation delay (tPLHD or
tPHLD) among all output channels. (4)
tJIT
Jitter (0% Pre-emphasis)
(5)
Use an alternating 1 and 0 pattern at 200
Mb/s, measure between 20% and 80% of
VOD. (4)
Use an alternating 1 and 0 pattern at 200
Mb/s, measure at 50% VOD between
input to output.
(4)
RJ - Alternating 1 and 0 at 750MHz
DJ - K28.5 Pattern, 1.5 Gbps
TJ - PRBS 27-1 Pattern, 1.5 Gbps
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(6)
(7)
(8)
Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Not Production tested. Specified by statistical analysis on a sample basis at the time of characterization.
Jitter is not production tested, but specified through characterization on a sample basis.
Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50%
duty cycle at 750MHz, tr = tf = 50ps (20% to 80%).
Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been
subtracted. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit
streams of (0011111010 1100000101).
Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted.
The input voltage = VID = 500mV, 27-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%).
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(1)
Max
Units
tON
LVDS Output Enable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from TRI-STATE to active.
0.5
1.5
µs
tON2
LVDS Output Enable time from
powerdown mode
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from Powerdown to active
10
20
µs
tOFF
LVDS Output Disable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from active to TRI-STATE
or powerdown.
12
ns
SWITCHING CHARACTERISTICS - SCAN FEATURES
fMAX
Maximum TCK Clock Frequency
tS
TDI to TCK, H or L
tH
25.0
MHz
3.0
ns
TDI to TCK, H or L
0.5
ns
tS
TMS to TCK, H or L
3.0
ns
tH
TMS to TCK, H or L
0.5
ns
tW
TCK Pulse Width, H or L
10.0
ns
tW
TRST Pulse Width, L
2.5
ns
tREC
Recovery Time, TRST to TCK
2.0
ns
8
RL = 500Ω,
CL = 35 pF
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Typical Performance Characteristics
WQFN Performance Characteristics
Power Supply Current
vs.
Bit Data Rate
Total Jitter
vs.
Bit Data Rate
60
300
50
PRE-EMPHASIS ON
250
TOTAL JITTER (ps)
POWER SUPPLY CURRENT (mA)
350
200
PRE-EMPHASIS OFF
150
100
40
30
VCM = 1.2V
20
50
10
0
0
VCM = 0.25V
VCM = 3.0V
0
500
1000
2000
1500
0
500
BIT DATA RATE (Mbps)
1000
1500
2000
BIT DATA RATE (Mbps)
Dynamic power supply current was measured with all channels active Total Jitter measured at 0V differential while running a PRBS 27-1
and toggling at the bit data rate. Data pattern has no effect on the
pattern with one channel active, all other channels are disabled. VDD =
power consumption. VDD = 3.3V, TA = +25°C, VID = 0.5V, VCM = 1.2V 3.3V, TA = +25°C, VID = 0.5V, pre-emphasis off.
Figure 2.
Figure 3.
Total Jitter
vs.
Temperature
30
TOTAL JITTER (ps)
25
20
15
10
5
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
Total Jitter measured at 0V differential while running a PRBS 27-1 pattern with one channel active, all other channels are disabled.
VDD = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate, pre-emphasis off.
Figure 4.
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TRI-STATE AND POWERDOWN MODES
The SCAN15MB200 has output enable control on each of the six onboard LVDS output drivers. This control
allows each output individually to be placed in a low power TRI-STATE mode while the device remains active,
and is useful to reduce power consumption on unused channels. In TRI-STATE mode, some outputs may remain
active while some are in TRI-STATE.
When all six of the output enables (all drivers on both channels) are deasserted (LOW), then the device enters a
Powerdown mode that consumes only 0.5mA (typical) of supply current. In this mode, the entire device is
essentially powered off, including all receiver inputs, output drivers and internal bandgap reference generators.
When returning to active mode from Powerdown mode, there is a delay until valid data is presented at the
outputs because of the ramp to power up the internal bandgap reference generators.
Any single output enable that remains active will hold the device in active mode even if the other five outputs are
in TRI-STATE.
When in Powerdown mode, any output enable that becomes active will wake up the device back into active
mode, even if the other five outputs are in TRI-STATE.
Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. Please refer to
application note AN-1194 (SNLA051), “Failsafe Biasing of LVDS Interfaces” for more information.
Interfacing LVPECL to LVDS
An LVPECL driver consists of a differential pair with coupled emitters connected to GND via a current source.
This drives a pair of emitter-followers that require a 50Ω to VCC-2.0 load. A modern LVPECL driver will typically
include the termination scheme within the device for the emitter follower. If the driver does not include the load,
then an external scheme must be used. The 1.3 V supply is usually not readily available on a PCB, therefore, a
load scheme without a unique power supply requirement may be used.
50:
15MB200
LVPECL
50:
R1
150:
R2
150:
Figure 5. DC Coupled LVPECL to LVDS Interface
Figure 5 is a separated π termination scheme for a 3.3 V LVPECL driver. R1 and R2 provides proper DC load for
the driver emitter followers, and may be included as part of the driver device.
NOTE
The bias networks shown above for LVPECL drivers and receivers may or may not be
present within the driver device. The LVPECL driver and receiver specification must be
reviewed closely to ensure compatibility between the driver and receiver terminations and
common mode operating ranges.
10
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SCAN15MB200
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SNLS188E – NOVEMBER 2005 – REVISED APRIL 2013
The 15MB200 includes a 100Ω input termination for the transmission line. The common mode voltage will be at
the normal LVPECL levels – around 2 V. This scheme works well with LVDS receivers that have rail-to-rail
common mode voltage, VCM, range. Most Texas Instruments LVDS receivers have wide VCM range. The
exceptions are noted in devices’ respective datasheets. Those LVDS devices that do have a wide VCM range do
not vary in performance significantly when receiving a signal with a common mode other than standard LVDS
VCM of 1.2 V.
0.1 PF
50:
15MB200
LVPECL
50:
R1
150:
R2
150:
0.1 PF
Figure 6. AC Coupled LVPECL to LVDS Interface
An AC coupled interface is preferred when transmitter and receiver ground references differ more than 1 V. This
is a likely scenario when transmitter and receiver devices are on separate PCBs. Figure 6 illustrates an AC
coupled interface between a LVPECL driver and LVDS receiver. R1 and R2, if not present in the driver device
provide DC load for the emitter followers and may range between 140-220Ω for most LVPECL devices for this
particular configuration.
NOTE
The bias networks shown above for LVPECL drivers and receivers may or may not be
present within the driver device. The LVPECL driver and receiver specification must be
reviewed closely to ensure compatibility between the driver and receiver terminations and
common mode operating ranges.
The 15MB200 includes an internal 100Ω resistor to terminate the transmission line for minimal reflections. The
signal after ac coupling capacitors will swing around a level set by internal biasing resistors (i.e. fail-safe) which
is either VDD/2 or 0 V depending on the actual failsafe implementation. If internal biasing is not implemented, the
signal common mode voltage will slowly drift to GND level.
Interfacing LVDS to LVPECL
An LVDS driver consists of a current source (nominal 3.5mA) which drives a CMOS differential pair. It needs a
differential resistive load in the range of 70 to 130Ω to generate LVDS levels. In a system, the load should be
selected to match transmission line characteristic differential impedance so that the line is properly terminated.
The termination resistor should be placed as close to the receiver inputs as possible. When interfacing an LVDS
driver with a non-LVDS receiver, one only needs to bias the LVDS signal so that it is within the common mode
range of the receiver. This may be done by using separate biasing voltage which demands another power
supply. Some receivers have required biasing voltage available on-chip (VT, VTT or VBB).
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SCAN15MB200
SNLS188E – NOVEMBER 2005 – REVISED APRIL 2013
www.ti.com
50:
LVPECL
15MB200
50:
R1
50:
R2
50:
VT
Figure 7. DC Coupled LVDS to LVPECL Interface
Figure 7 illustrates interface between an LVDS driver and a LVPECL with a VT pin available. R1 and R2, if not
present in the receiver, provide proper resistive load for the driver and termination for the transmission line, and
VT sets desired bias for the receiver.
NOTE
The bias networks shown above for LVPECL drivers and receivers may or may not be
present within the driver device. The LVPECL driver and receiver specification must be
reviewed closely to ensure compatibility between the driver and receiver terminations and
common mode operating ranges.
VDD
0.1PF
R1
83:
R2
83:
50:
LVPECL
15MB200
50:
0.1PF
R3
130:
R4
130:
Figure 8. AC Coupled LVDS to LVPECL Interface
Figure 8 illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a VT pin
available. The resistors R1, R2, R3, and R4, if not present in the receiver, provide a load for the driver, terminate
the transmission line, and bias the signal for the receiver.
NOTE
The bias networks shown above for LVPECL drivers and receivers may or may not be
present within the driver device. The LVPECL driver and receiver specification must be
reviewed closely to ensure compatibility between the driver and receiver terminations and
common mode operating ranges.
12
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SCAN15MB200
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SNLS188E – NOVEMBER 2005 – REVISED APRIL 2013
Design-For-Test (DfT) Features
IEEE 1149.1 SUPPORT
The SCAN15MB200 supports a fully compliant IEEE 1149.1 interface. The Test Access Port (TAP) provides
access to boundary scan cells at each LVTTL I/O on the device for interconnect testing. Differential pins are
included in the same boundary scan chain but instead contain IEEE1149.6 cells. IEEE1149.6 is the improved
IEEE standard for testing high-speed differential signals.
Refer to the BSDL file located on TI's website for the details of the SCAN15MB200 IEEE 1149.1 implementation.
IEEE 1149.6 SUPPORT
AC-coupled differential interconnections on very high speed (1+ Gbps) data paths are not testable using
traditional IEEE 1149.1 techniques. The IEEE 1149.1 structures and methods are intended to test static (DCcoupled), single ended networks. IEEE 1149.6 is specifically designed for testing high-speed differential,
including AC coupled networks.
The SCAN15MB200 is intended for high-speed signalling up to 1.5 Gbps and includes IEEE1149.6 on all
differential inputs and outputs.
FAULT INSERTION
Fault Insertion is a technique used to assist in the verification and debug of diagnostic software. During system
testing faults are "injected" to simulate hardware failure and thus help verify the monitoring software can detect
and diagnose these faults. In the SCAN15MB200 an IEEE1149.1 "stuck-at" instruction can create a stuck-at
condition, either high or low, on any pin or combination of pins. A more detailed description of the stuck-at
feature can be found in TI Applications note AN-1313 (SNLA060).
Packaging Information
The WQFN package is a leadframe based chip scale package (CSP) that may enhance chip speed, reduce
thermal impedance, and reduce the printed circuit board area required for mounting. The small size and very low
profile make this package ideal for high density PCBs used in small-scale electronic applications such as cellular
phones, pagers, and handheld PDAs. The WQFN package is offered in the no Pullback configuration. In the no
Pullback configuration the standard solder pads extend and terminate at the edge of the package. This feature
offers a visible solder fillet after board mounting.
The WQFN has the following advantages:
• Low thermal resistance
• Reduced electrical parasitics
• Improved board space efficiency
• Reduced package height
• Reduced package mass
For more details about WQFN packaging technology, refer to applications note AN-1187 (SNOA401), "Leadless
Leadframe Package"
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13
SCAN15MB200
SNLS188E – NOVEMBER 2005 – REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
14
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SCAN15MB200TSQ/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
15MB200
SCAN15MB200TSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
15MB200
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SCAN15MB200TSQ/NOP
B
WQFN
RHS
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
SCAN15MB200TSQX/NO
PB
WQFN
RHS
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SCAN15MB200TSQ/NOPB
WQFN
RHS
WQFN
RHS
SCAN15MB200TSQX/NOP
B
SPQ
Length (mm)
Width (mm)
Height (mm)
48
250
210.0
185.0
35.0
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHS0048A
WQFN - 0.8 mm max height
SCALE 1.800
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
A
B
PIN 1 INDEX AREA
0.5
0.3
7.15
6.85
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
(0.2)
5.1 0.1
(A) TYP
24
13
44X 0.5
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
12
25
EXPOSED
THERMAL PAD
2X
5.5
49
SYMM
SEE TERMINAL
DETAIL
1
PIN 1 ID
(OPTIONAL)
36
48
37
SYMM
48X
0.5
0.3
48X
0.30
0.18
0.1
0.05
C A B
4214990/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 5.1)
SYMM
37
48
48X (0.6)
1
36
48X (0.25)
(1.05) TYP
44X (0.5)
(1.25) TYP
49
SYMM
(6.8)
(R0.05)
TYP
( 0.2) TYP
VIA
25
12
13
24
(1.25)
TYP
(1.05)
TYP
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214990/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.625) TYP
(1.25)
TYP
37
48
48X (0.6)
1
36
49
48X (0.25)
44X (0.5)
(1.25)
TYP
(0.625) TYP
SYMM
(6.8)
(R0.05) TYP
METAL
TYP
25
12
13
16X
( 1.05)
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4214990/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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