Texas Instruments | 3.125 Gbps 1:4 LVDS Repeater w/ Transmit Pre-Emphasis and Receive Equalization (Rev. D) | Datasheet | Texas Instruments 3.125 Gbps 1:4 LVDS Repeater w/ Transmit Pre-Emphasis and Receive Equalization (Rev. D) Datasheet

Texas Instruments 3.125 Gbps 1:4 LVDS Repeater w/ Transmit Pre-Emphasis and Receive Equalization (Rev. D) Datasheet
DS25BR204
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SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013
DS25BR204 3.125 Gbps 1:4 LVDS Repeater with Transmit Pre-Emphasis and Receive
Equalization
Check for Samples: DS25BR204
FEATURES
DESCRIPTION
•
The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater
optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and
balanced cables. Fully differential signal paths ensure
exceptional signal integrity and noise immunity.
1
2
•
•
•
•
•
•
DC - 3.125 Gbps Low Jitter, Low Skew, Low
Power Operation
Pin Selectable Transmit Pre-Emphasis and
Receive Equalization Eliminate Data
Dependant Jitter
Wide Input Common Mode Range Allows DCcoupled Interface to LVDS, CML and LVPECL
Drivers
Redundant Inputs
Integrated 100Ω Input and Output
Terminations
8 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small 6 mm x 6 mm WQFN-40 Space Saving
Package
APPLICATIONS
•
•
•
•
Clock and Data Distribution
Clock and Data Buffering and Muxing
OC-48 / STM-16
SD/HD/3GHD SDI Routers
The device has two different LVDS input channels
and a select line determines which input is active.
Both inputs have programmable equalization
providing maximum signal strength. A loss-of-signal
(LOS) circuit monitors both input channels and a
unique LOS pin reports when no signal is detected at
that input.
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout.
Each differential input and output is internally
terminated with a 100Ω resistor to lower device return
losses, reduce component count and further minimize
board space.
Typical Application
CARD A
CARD C
ASIC/FPGA 1
ASIC/FPGA
ASIC/FPGA 2
DS25BR204
1:4 LVDS
Repeater
Discrete
Serializer
CARD B
Discrete
Deserializer 1
Discrete
Deserializer 2
BACKPLANE
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS25BR204
SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013
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Block Diagram
SEL_in
PWDNn
4
PE0
OUT0+
PE
OUT0-
EQ1
PE1
IN1+
OUT1+
PE
EQ
IN1-
OUT1-
EQ2
PE2
IN2+
EQ
IN2-
OUT2+
PE
OUT2PE3
OUT3+
PE
OUT3-
PWDN
Control and LOS
Circuitry
2
LOSn
NC
EQ1
PWDN
LOS1
LOS2
PWDN0
PWDN1
PWDN2
PWDN3
PE0
40
39
38
37
36
35
34
33
32
31
Connection Diagram
NC
1
30
VDD
NC
2
29
OUT0+
VDD
3
28
OUT0-
IN1+
4
27
OUT1+
26
OUT1-
25
VDD
DAP
IN1-
5
IN2+
6
IN2-
7
24
OUT2+
VDD
8
23
OUT2-
NC
9
22
OUT3+
NC
10
21
OUT3-
11
12
13
14
15
16
17
18
19
20
EQ2
NC
NC
SEL_in
VDD
GND
NC
PE3
PE2
PE1
GND
DS25BR204 Pin Diagram
2
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SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013
PIN DESCRIPTIONS
Pin Name
Pin
Number
IN1+, IN1-,
IN2+, IN2-,
I/O, Type
Pin Description
4, 5,
6, 7,
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29,
27,
24,
22,
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
EQ1, EQ2,
39,11
I, LVCMOS
Receive equalization level select pins.
PE0, PE1,
PE2, PE3
31, 20,
19, 18
I, LVCMOS
Transmit pre-emphasis level select pins.
SEL_in
14
I, LVCMOS
Input select pin.
LOS2
LOS1
36,
37
O, LVCMOS
Loss of Signal output pin, LOSn, reports when an open input fault condition is
detected at the input, INn. These are open drain outputs. External pull up
resistors are required.
PWDN0,
PWDN1,
PWDN2,
PWDN3
35,
34,
33,
32
I, LVCMOS
Channel output power down pins. When the PWDNn is set to L, the channel
output, OUTn, is in the power down mode.
NC
1, 2,
9, 10,
12, 13,
17, 40
NC
NO CONNECT pins. May be left floating.
PWDN
38
I, LVCMOS
Device power down pin. When the PWDN is set to L, the device is in the
power down mode.
VDD
3, 8,
15,25, 30
Power
Power supply pins.
GND
16, DAP
Power
Ground pin and a pad (DAP - die attach pad).
28,
26,
23,
21
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage
LVCMOS Input Voltage
−0.3V to (VCC + 0.3V)
LVCMOS Output Voltage
−0.3V to (VCC + 0.3V)
−0.3V to +4V
LVDS Input Voltage
Differential Input Voltage |VID|
1V
−0.3V to (VCC + 0.3V)
LVDS Output Voltage
LVDS Differential Output Voltage
0.0V to +1V
LVDS Output Short Circuit Current Duration
5 ms
Junction Temperature
+150°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
RTA0040A Package
4.65W
Derate RTA0040A Package
37.2 mW/°C above +25°C
Package Thermal Resistance
θJA
+26.9°C/W
θJC
+3.8°C/W
ESD Susceptibility
HBM
MM
(3)
(2)
(3)
(4)
(5)
≥250V
(5)
CDM
(1)
≥8 kV
(4)
≥1250V
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Human Body Model, applicable std. JESD22-A114C
Machine Model, applicable std. JESD22-A115-A
Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Supply Voltage (VCC)
Receiver Differential Input Voltage (VID)
Operating Free Air Temperature (TA)
Min
Typ
Max
Units
3.0
3.3
3.6
V
1
V
+85
°C
0
−40
+25
Electrical Characteristics (1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(2) (3)
Min
Typ
Max
Units
V
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VDD
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
±10
μA
(1)
(2)
(3)
4
VIN = 3.6V
VCC = 3.6V
0
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
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Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (2) (3)
Symbol
Parameter
Conditions
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
VOL
Low Level Output Voltage
IOL= 4 mA
Min
Typ
Max
Units
0
±10
μA
−0.9
−1.5
V
0.4
V
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
VTH
Differential Input High Threshold
0
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = 3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor
Between IN+ and IN-
100
Ω
VCM = +0.05V or VCC-0.05V
0
−100
1
V
+100
mV
0
0.05
±1
mV
VCC 0.05
V
±10
μA
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
250
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
IOS
Output Short Circuit Current
RL = 100Ω
-35
1.05
(4)
350
RL = 100Ω
1.2
-35
450
mV
35
mV
1.375
V
35
mV
OUT to GND
-35
-55
mA
OUT to VCC
7
55
mA
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
SUPPLY CURRENT
ICC
Supply Current
PE = OFF, EQ = OFF, PWDN = H
150
185
mA
ICCZ
Power Down Supply Current
PWDN = L
47
65
mA
(4)
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(1) (2)
Min
Typ
Max
Units
460
600
ps
420
600
ps
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
Differential Propagation Delay Low to
High (3)
tPHLD
Differential Propagation Delay High to
Low (3)
tSKD1
Pulse Skew |tPLHD − tPHLD|
40
100
ps
tSKD2
Channel to Channel Skew
55
110
ps
tSKD3
Part to Part Skew
50
190
ps
tLHT
Rise Time
80
160
ps
80
160
ps
RL = 100Ω
(2) (4)
(5) (3)
(3) (6)
(3)
RL = 100Ω
(3)
tHLT
Fall Time
tON
Any PWDN to Output Active Time
8
20
μs
tOFF
Any PWDN to Output Inactive Time
5
12
ns
tSEL
Select Time
5
12
ns
JITTER PERFORMANCE WITH EQ = Off, PE = Off (3) (Figure 5)
tRJ1
tRJ2
Random Jitter (RMS Value)
No Test Channels
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
No Test Channels
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
11
19
ps
3.125 Gbps
13
24
ps
Total Jitter (Peak to Peak)
No Test Channels
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.05
0.10
UIP-P
3.125 Gbps
0.07
0.13
UIP-P
(7)
tDJ1
tDJ2
(8)
tTJ1
tTJ2
(9)
JITTER PERFORMANCE WITH EQ = Off, PE = On
tRJ1B
tRJ2B
tDJ1B
tDJ2B
tTJ1B
tTJ2B
tRJ2D
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
6
(Figure 6, Figure 9)
Random Jitter (RMS Value)
Test Channel B
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
Test Channel B
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
10
23
ps
3.125 Gbps
4
20
ps
Total Jitter (Peak to Peak)
Test Channel B
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.06
0.10
UIP-P
3.125 Gbps
0.05
0.13
UIP-P
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
(7)
(8)
(9)
JITTER PERFORMANCE WITH EQ = On, PE = Off
tRJ1D
(3)
Random Jitter (RMS Value)
Test Channel D
(7)
(3)
(Figure 7, Figure 9)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
Specification is guaranteed by characterization and is not tested in production.
tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
Symbol
tDJ1D
tDJ2D
tTJ1D
tTJ2D
Parameter
Conditions
tRJ2BD
tDJ2BD
tTJ2BD
Units
2.5 Gbps
17
30
ps
3.125 Gbps
15
28
ps
Total Jitter (Peak to Peak)
Test Channel D
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.07
0.13
UIP-P
3.125 Gbps
0.08
0.15
UIP-P
(9)
(3)
(Figure 8, Figure 9)
Random Jitter (RMS Value)
Input Test Channel D
Output Test Channel B
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
10
20
ps
3.125 Gbps
8
21
ps
Total Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.07
0.12
UIP-P
3.125 Gbps
0.08
0.15
UIP-P
(8)
tTJ1BD
Max
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
(8)
(7)
tDJ1BD
Typ
Deterministic Jitter (Peak to Peak)
Test Channel D
JITTER PERFORMANCE WITH EQ = On, PE = On
tRJ1BD
Min
(9)
DC TEST CIRCUITS
¼ DS25BR204
Power Supply
VOH
OUT+
IN+
R
D
RL
Power Supply
IN-
OUTVOL
Figure 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
¼ DS25BR204
OUT+
IN+
R
Signal Generator
D
IN-
RL
OUT-
Figure 2. Differential Driver AC Test Circuit
Figure 3. Propagation Delay Timing Diagram
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Figure 4. LVDS Output Transition Times
Pre-Emphasis and Equalization Test Circuits
DS25BR204
CHARACTERIZATION BOARD
50:
Microstrip
50:
Microstrip
¼ DS25BR204
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50:
Microstrip
50:
Microstrip
Figure 5. Jitter Performance Test Circuit
DS25BR204
CHARACTERIZATION BOARD
TEST
CHANNEL
¼ DS25BR204
50: MS
50: MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50: MS
50: MS
Figure 6. Pre-emphasis Performance Test Circuit
TEST
CHANNEL
DS25BR204
CHARACTERIZATION BOARD
50: MS
¼ DS25BR204
50: MS
L=4"
L=4"
L=4"
L=4"
50: MS
50: MS
PATTERN
GENERATOR
OSCILLOSCOPE
Figure 7. Equalization Performance Test Circuit
8
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TEST
CHANNEL
DS25BR204
CHARACTERIZATION BOARD
50:
Microstrip
TEST
CHANNEL
50:
Microstrip
¼ DS25BR204
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50:
Microstrip
50:
Microstrip
Figure 8. Pre-Emphasis and Equalization Performance Test Circuit
50: MS
50: MS
L = A, B or C
L=1"
L=1"
L=1"
50: MS
L=1"
100: Diff.
Stripline
50: MS
Figure 9. Test Channel Block Diagram
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric
constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:
Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel
Length
(inches)
Insertion Loss (dB)
500 MHz
750 MHz
1000 MHz
1250 MHz
1500 MHz
1560 MHz
A
10
-1.2
-1.7
-2.0
-2.4
-2.7
-2.8
B
20
-2.6
-3.5
-4.1
-4.8
-5.5
-5.6
C
30
-4.3
-5.7
-7.0
-8.2
-9.4
-9.7
D
15
-1.6
-2.2
-2.7
-3.2
-3.7
-3.8
E
30
-3.4
-4.5
-5.6
-6.6
-7.7
-7.9
F
60
-7.8
-10.3
-12.4
-14.5
-16.6
-17.0
Functional Description
The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and switching over
lossy FR-4 printed circuit board backplanes and balanced cables.
The DS25BR204 SEL_in pin selects one out of two available LVDS inputs. The following is the input select truth
tables.
Table 1. Input Select Truth Table
CONTROL Pin (SEL_in) State
Input Selected
0
IN1
1
IN2
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The DS25BR204 has a pre-emphasis control pin for each output for switching the transmit pre-emphasis to ON
and OFF setting and an equalization control pin for each input for switching the receive equalization to ON and
OFF setting. The following are the transmit pre-emphasis and receive equalization truth tables.
Table 2. Transmit Pre-Emphasis Truth Table (1)
OUTPUT OUTn, n = {0, 1, 2, 3}
(1)
CONTROL Pin (PEn) State
Pre-emphasis Level
0
OFF
1
ON
Transmit Pre-emphasis Level Selection for an Output OUTn
Table 3. Receive Equalization Truth Table (1)
INPUT INn, n = {1, 2}
(1)
CONTROL Pin (EQn) State
Equalization Level
0
OFF
1
ON
Receive Equalization Level Selection for an Input INn
Input Interfacing
The DS25BR204 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS25BR204 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS25BR204 inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS25BR204
Receiver
100: Differential T-Line
OUT+
IN+
100:
IN-
OUT-
Figure 10. Typical LVDS Driver DC-Coupled Interface to an DS25BR204 Input
CML3.3V or CML2.5V
Driver
VCC
50:
DS25BR204
Receiver
100: Differential T-Line
50:
OUT+
IN+
100:
IN-
OUT-
Figure 11. Typical CML Driver DC-Coupled Interface to an DS25BR204 Input
10
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LVPECL
Driver
OUT+
100: Differential T-Line
LVDS
Receiver
IN+
100:
OUT150-250:
IN150-250:
Figure 12. Typical LVPECL Driver DC-Coupled Interface to an DS25BR204 Input
Output Interfacing
The DS25BR204 outputs signals are compliant to the LVDS standard. Its outputs can be DC-coupled to most
common differential receivers. The following figure illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check the
respective receiver's data sheet prior to implementing the suggested interface implementation.
DS25BR204
Driver
Differential
Receiver
100: Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100:
100:
IN-
OUT-
Figure 13. Typical DS25BR204 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR204
11
DS25BR204
SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013
www.ti.com
Typical Performance
60
150
VCC = 3.3V
TA = 25°C
50
NRZ PRBS-7
EQ = Off
40 PE = Off
TA = 25°C
NRZ PRBS7
EQ = On
125
RESIDUAL JITTER (ps)
TOTAL JITTER (ps)
VCC = 3.3V
30
20
10
100
20" FR4 Stripline
75
50
25
0
10" FR4 Stripline
0
0
0.8
1.6
2.4
3.2
0
4.0
0.8
DATA RATE (Gbps)
2.4
3.2
4.0
DATA RATE (Gbps)
Figure 14. Total Jitter as a Function of Data Rate
Figure 15. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
150
240
VCC = 3.3V
VCC = 3.3V
SUPPLY CURRENT (mA)
TA = 25°C
NRZ PRBS7
PEM = On
125
RESIDUAL JITTER (ps)
1.6
100
40" FR4 Stripline
75
30" FR4 Stripline
50
25
220 TA = 25°C
NRZ PRBS7
200
180
PE = On
160
140
PE = Off
20" FR4 Stripline
0
120
0
0.8
1.6
2.4
3.2
4.0
0.8
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 16. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
12
0
Figure 17. Supply Current as a Function of Data Rate and
PE Level
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR204
DS25BR204
www.ti.com
SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR204
13
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
DS25BR204TSQ/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WQFN
RTA
40
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
2BR204SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS25BR204TSQ/NOPB
Package Package Pins
Type Drawing
WQFN
RTA
40
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
16.4
Pack Materials-Page 1
6.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.3
1.5
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS25BR204TSQ/NOPB
WQFN
RTA
40
250
210.0
185.0
35.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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