Texas Instruments | Low-Power RS-485 Full-Duplex Drivers/Receivers (Rev. E) | Datasheet | Texas Instruments Low-Power RS-485 Full-Duplex Drivers/Receivers (Rev. E) Datasheet

Texas Instruments Low-Power RS-485 Full-Duplex Drivers/Receivers (Rev. E) Datasheet
SN65HVD3080E
SN65HVD3083E
SN65HVD3086E
www.ti.com
SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
LOW-POWER RS-485 FULL-DUPLEX DRIVERS/RECEIVERS
Check for Samples: SN65HVD3080E, SN65HVD3083E, SN65HVD3086E
FEATURES
1
•
•
•
•
•
•
•
•
Low Quiescent Power
– 375 μA (Typical) Enabled Mode
– 2 nA (Typical) Shutdown Mode
Small MSOP Package
1/8 Unit-Load—Up to 256 Nodes per Bus
16 kV Bus-Pin ESD Protection, 6 kV All Pins
Failsafe Receiver (Bus Open, Short, Idle)
TIA/EIA-485A Standard Compliant
RS-422 Compatible
Power-Up, Power-Down Glitch-Free Operation
DGS PACKAGE
(TOP VIEW)
1
10
VCC
RE
2
9
A
DE
3
8
B
D
4
7
Z
GND
5
6
Y
D PACKAGE
(TOP VIEW)
APPLICATIONS
•
•
•
•
•
•
•
R
NC
R
RE
DE
D
GND
GND
Motion Controllers
Point-of-Sale (POS) Terminals
Rack-to-Rack Communications
Industrial Networks
Power Inverters
Battery-Powered Applications
Building Automation
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
NC - No internal connection
Pins 6 and 7 are connected together internally
Pins 13 and 14 are connected together internally
DESCRIPTION
Each of these devices is a balanced driver and receiver designed for full-duplex RS-485 or RS-422 data bus
networks. Powered by a 5-V supply, they are fully compliant with the TIA/EIA-485A standard.
With controlled bus output transition times, the devices are suitable for signaling rates from 200 kbps to 20 Mbps.
The devices are designed to operate with a low supply current, less than 1 mA (typical), exclusive of the load.
When in the inactive shutdown mode, the supply current drops to a few nanoamps, making these devices ideal
for power-sensitive applications.
The wide common-mode range and high ESD protection levels of these devices make them suitable for
demanding applications such as motion controllers, electrical inverters, industrial networks, and cabled chassis
interconnects where noise tolerance is essential.
These devices are characterized for operation over the temperature range -40°C to 85°C
Enabled ICC
ISL
MAX
TI
350
370
390
410
430
450
470
490
510
530
550
Current - mA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
SN65HVD3080E
SN65HVD3083E
SN65HVD3086E
SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PART NUMBER
SIGNALING RATE
SN65HVD3080E
200 kbps
SN65HVD3083E
1 Mbps
SN65HVD3086E
20 Mbps
(1)
(2)
PACKAGE (1)
MARKED AS
BTT
DGS, DGSR 10-pin MSOP
(2)
BTU
BTF
D 14-pin SOIC
HVD3086
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The R suffix indicated tape and reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
VCC
Supply voltage range
(2)
–0.3 V to 7 V
V(A), V(B), V(Y), V(Z)
Voltage range at any bus terminal (A, B, Y, Z)
–9 V to 14 V
V(TRANS)
Voltage input, transient pulse through 100 Ω.
See Figure 10 (A, B, Y, Z)
–50 to 50 V
VI
Input voltage range (D, DE, RE)
PD
Continuous total power dissipation
TJ
Junction temperature
(1)
(2)
-0.3 V to VCC+0.3 V
See the dissipation rating table
170°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
POWER DISSIPATION RATINGS
(1)
PACKAGE
TA < 25°C
DERATING FACTOR (1)
ABOVE TA < 25°C
TA = 85°C
10-pin MSOP (DGS)
463 mW
3.71 mW/°C
241 mW
14-pin SOIC (D)
765 mW
6.1 mW/°C
400 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
Human Body Model
TEST CONDITIONS
(1)
Charged Device Mode (2)
Machine Model
(1)
(2)
(3)
2
(3)
MIN
TYP
MAX
UNIT
A,B,Y,Z, and GND
16
kV
All pins
6
kV
All pins
1.5
kV
All pins
400
V
Tested in accordance JEDEC Standard 22, Test Method A114-A. Bus pin stressed with respect to a common connection of GND and
VCC.
Tested in accordance JEDEC Standard 22, Test Method C101.
Tested in accordance JEDEC Standard 22, Test Method A115.
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SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
SUPPLY CURRENT
over recommended operating conditions unless otherwise noted
PARAMETER
ICC
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RE at 0 V, D and DE at VCC, No load
Receiver enabled,
Driver enabled
375
750
μA
RE at 0 V, D and DE at 0 V, No load
Receiver enabled,
Driver disabled
300
680
μA
RE at VCC, D and DE at VCC, No load
Receiver disabled,
Driver enabled
240
600
μA
RE and D at VCC, DE at 0 V, No load
Receiver disabled,
Driver disabled
2
1000
nA
UNIT
Supply current
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
IOH
High-level output current
IOL
Low-level output current
TJ
Junction temperature
TA
Ambient still-air temperature
(1)
MIN
NOM
MAX
4.5
5
5.5
–7 (1)
12
D, DE, RE
2
VCC
D, DE, RE
0
0.8
–12
12
Dynamic , See Figure 11
V
V
V
V
Driver
–60
Receiver
–10
mA
Driver
60
Receiver
10
150
–40
85
mA
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
Copyright © 2006–2012, Texas Instruments Incorporated
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SN65HVD3083E
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SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
4.3
VCC
RL = 54 Ω, See Figure 1
1.5
2.3
Vtest = –7 V to 12 V, See Figure 2
1.5
No load, IO = 0
|VOD|
Differential output voltage
Δ|VOD|
Change in magnitude of differential output voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Common-mode output voltage (Dominant)
VOC(PP)
Peak-to-peak common-mode output voltage
RL = 100 Ω, See Figure 1
High-impedance state output current
V
2
RL = 54 Ω, See Figure 1 and Figure 2
See Figure 3
–0.2
0
0.2
1
2.6
3
0
0.1
-0.1
V
V
0.5
VCC = 0 V, V(Z) or V(Y) = 12 V
Other input at 0 V
IZ(Y) or
IZ(Z)
UNIT
1
VCC = 0 V, V(Z) or V(Y) = -7 V
Other input at 0 V
-1
µA
VCC = 5 V, V(Z) or V(Y) = 12 V
Other input at 0 V
1
VCC = 5 V, V(Z) or V(Y) = -7 V
Other input at 0 V
-1
II
Input current
D, DE
-100
100
µA
IOS
Short-circuit output current
–7 V ≤ VO ≤ 12 V
-250
250
mA
UNIT
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH,
tPHL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
TYP
MAX
HVD3080E
TEST CONDITIONS
0.7
1.3
μs
HVD3083E
150
500
ns
HVD3086E
12
20
ns
0.9
1.5
μs
200
300
ns
7
15
ns
HVD3080E
20
200
ns
HVD3083E
5
50
ns
HVD3086E
1.4
5
ns
HVD3080E
2.5
7
μs
HVD3083E
1
2.5
μs
13
30
ns
80
200
ns
HVD3083E
60
100
ns
HVD3086E
12
30
ns
HVD3080E
2.5
7
μs
HVD3080E
tr,
tf
Differential output signal rise time
Differential output signal fall time
HVD3083E
HVD3086E
tsk(p)
tPZH
Pulse skew (|tPHL – tPLH|)
Propagation delay time,
high-impedance-to-high-level output
HVD3086E
HVD3080E
tPHZ
tPZL
Propagation delay time,
high-level-to-high-impedance output
Propagation delay time, high-impedance-to-low-level
output
2.5
μs
30
ns
80
200
ns
HVD3083E
60
100
ns
HVD3086E
12
30
ns
3.5
7
μs
Propagation delay time, standby-to-high-level output (See Figure 5)
tPZL
Propagation delay time, standby-to-low-level output (See Figure 6)
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RL = 110 Ω,
RE at 0 V,
See Figure 5
1
tPZH,
4
RL = 54 Ω,
CL = 50 pF,
See Figure 4
13
HVD3080E
Propagation delay time, low-level-to-high-impedance
output
0.5
HVD3083E
HVD3086E
tPLZ
MIN
RL = 110 Ω,
RE at 0 V,
See Figure 6
RL = 110 Ω, RE at 3 V
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SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
MIN TYP (1)
TEST CONDITIONS
VIT+
Positive-going differential input threshold voltage
IO = –10 mA
VIT-
Negative-going differential input threshold
voltage
IO = 10 mA
Vhys
Hysteresis voltage (VIT+ - VIT-)
VOH
High-level output voltage
VID = 200 mV, IOH = –10 mA,
See Figure 7 and Figure 8
VOL
Low-level output voltage
VID = –200 mV, IOH = 10 mA,
See Figure 7 and Figure 8
IOZ
High-impedance-state output current
VO = 0 or VCC
Other input at 0V
-0.08
UNIT
–0.01
V
–0.2 -0.1
30
mV
4 4.6
V
0.15
–1
0.4
V
1
µA
VA or VB = 12 V
0.04
0.11
VA or VB = 12 V, VCC = 0 V
0.06
0.13
II
Bus input current
IIH
High-level input current
VIH = 2 V
–60
IIL
Low-level input current
VIL = 0.8 V
-60
CID
Differential input capacitance
VI = 0.4 sin (4E6πt) + 0.5 V
VA or VB = -7 V
VA or VB = -7 V, VCC = 0 V
(1)
MAX
–0.1
–0.04
–0.05
–0.03
mA
-30
µA
-30
µA
7
pF
All typical values are at 25°C and with a 3.3-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
TEST CONDITIONS
MIN
VID = -1.5 V to 1.5 V,
CL = 15 pF, See Figure 8
TYP
MAX
75
100
79
100
UNIT
tsk(p)
Pulse skew (|tPHL – tPLH|)
4
10
tr
Output signal rise time
1.5
3
tf
Output signal fall time
1.8
3
tPZH,
tPZL
DE at VCC,
See Figure 9
10
50
ns
Output enable time
DE at GND,
See Figure 9
1.7
3.5
μs
tPHZ,
tPLZ
Output disable time
7
50
ns
From standby
DE at GND or VCC,
See Figure 9
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5
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SN65HVD3083E
SN65HVD3086E
SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
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PARAMETER MEASUREMENT INFORMATION
VCC
DE
RL
2
IO
Y
D
0 or 5 V
VOD
RL
2
IO
Z
VI
VOC
VO
VO
Figure 1. Driver VOD Test Circuit and Current Definitions
375 Ω ±1%
VCC
DE
D
Y
VOD
0 or 5 V
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
Z
375 Ω ±1%
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
VCC
27 Ω ± 1%
DE
Input
D
Y
VY
Z
VZ
Y
27 Ω ± 1%
Z
50 pF ±20%
VOC
Input: PRR = 500 kHz, 50% Duty Cycle,
tr < 6 ns, tf < 6 ns, ZO = 50 W
CL Includes Fixture and
Instrumentation Capacitance
VOC
VOC(SS)
VOC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3V
VI
Y
VI
W
Z
RL = 54 W
1.5 V
1.5 V
CL = 50 pF ±20%
±1%
90%
VOD
0V
10%
VOD(H)
90%
0V
10%
VOD(L)
Generator: PRR = 500 kHz, 50% Duty Cycle,
tr < 6 ns, tf < 6 ns, ZO = 50 W
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
6
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SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
PARAMETER MEASUREMENT INFORMATION (continued)
Y
3 V when testing Y,
0 V when testing Z
1.5 V
RL = 110 W
CL = 50 pF
0.5 V
tPZH
±1%
±20%
50 W
VI
0V
V OH
VO
Generator: PRR = 500 kHz,
50% Duty Cycle, tr < 6 ns,
1.5 V
VI
Z
DE
Input
Generator
3V
S1 VO
D
2.5 V
»0V
tPHZ
CL Includes Fixture and
Instrumentation Capacitance
tf < 6 ns, ZO = 50 W
Figure 5. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
VCC
RL = 110 W
Y
0 V when testing Y,
3 V when testing Z
1.5 V
tPZL
Z
0V
tPLZ
CL = 50 pF
50 W
VI
1.5 V
VI
VO
DE
Input
Generator
S1
D
3V
±1%
VO
±20%
5V
0.5 V
2.5 V
VOL
Generator: PRR = 500 kHz,
50% Duty Cycle, tr < 6 ns,
CL Includes Fixture and
Instrumentation Capacitance
tf < 6 ns, ZO = 50 W
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA
A
IO
R
VA
VA + VB
2
VID
VIC
B
VO
IB
VB
Figure 7. Receiver Voltage and Current Definitions
A
Input
Generator
R
VI
50 Ω
1.5 V
B
3V
VO
1.5 V
0V
CL = 15 pF
RE
1.5 V
VI
t PLH
±20%
t PHL
VOH
90% 90%
Generator: PRR = 500 kHz,
50% Duty Cycle,tr < 6 ns,
tf < 6 ns, ZO = 50 W
CL Includes Fixture and
Instrumentation Capacitance
VO
1.5 V
10%
1.5 V
10%
tr
VOL
tf
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
0 or 2.5 V
A
VO
R
2.5 or 0 V
B
CL = 15 pF
RE
Input
Generator
VI
C
1 kW ±1%
3V
VI
S1
0V
D
A at 2.5 V
B at 0 V
S1 to D
VOH - 0.5 V
1.5 V
VO
CL Includes Fixture and
Instrumentation Capacitance
tPZL
A at 0 V
B at 2.5 V
S1 to C
Generator: PRR = 500 kHz, 50% Duty Cycle,
tr < 6 ns, tf < 6 ns, ZO = 50 W
tPHZ
tPZH
±20%
50 W
1.5 V
1.5 V
VO
tPLZ
1.5 V
VOH
»0V
»5V
VOL + 0.5 V
VOL
Figure 9. Receiver Enable and Disable Test Circuit and Voltage Waveforms
0 V or 3 V
DE
A
Y
D
R
Z
+
-
A.
100 W
100 W
±1%
±1%
Pulse Generator
15 ms duration
1% Duty Cycle
tr, tf £ 100 ns
B
RE
0 V or 3 V
+
-
This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 10. Transient Overvoltage Test Circuit
8
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SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
DEVICE INFORMATION
1
VID - Differential Input Voltage - pk
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10 12 14
Signaling Rate - Mbps
16
18
20
Figure 11. Recommended Minimum Differential Input Voltage vs Signaling Rate
FUNCTION TABLES
DRIVER (1)
(1)
INPUT
ENABLE
OUTPUTS
D
DE
Y
H
H
H
L
L
H
L
H
X
L or OPEN
Z
Z
Open
H
H
L
Z
H = high level, L = low level, Z = high impedance, X = irrelevant, ? =
indeterminate
RECEIVER (1)
DIFFERENTIAL INPUTS
VID = V(A) - V(B)
ENABLE
RE
OUTPUT
R
L
(1)
VID ≤ −0.2 V
L
−0.2 V < VID < −0.01 V
L
?
−0.01 V ≤ VID
L
H
X
H or OPEN
Z
Open Circuit
L
H
BUS Idle
L
H
Short Circuit
L
H
H = high level, L = low level, Z = high impedance, X = irrelevant, ? =
indeterminate
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DEVICE ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETERS
P(AVG)
Average power dissipation
TEST CONDITIONS
RL = 60 Ω, Input to D a 500-kHz 50% duty
cycle square-wave
MIN
TYP
MAX
UNIT
85
109
136
mW
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Input
DE Input
VCC
VCC
50 kW
500
500
Input
Input
9V
50 kΩ
9V
A Input
B Input
VCC
16 V
VCC
16 V
36 kW
180 kW
36 kW
180 kW
Input
Input
16 V
36 kW
16 V
36 kW
R Outputs
Y and Z Outputs
VCC
VCC
16 V
5W
Output
Output
16 V
10
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9V
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SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
TYPICAL CHARACTERISTICS
HVD3080E
SUPPLY CURRENT
vs
SIGNALING RATE
INPUT BIAS CURRENT
vs
BUS INPUT VOLTAGE
10
80
No Load
VCC = 5 V
TA = 25°C
50% Square wave input
ICC − Supply Current − mA
II − Input Bias Current − µA
60
40
20
VCC = 0 V
VCC = 5 V
0
−20
Driver and Receiver
1
Receiver Only
−40
0.1
−60
−8
−6
−4
−2
0
2
4
6
8
10
12
1
10
VI − Bus Input Voltage − V
Figure 12.
Figure 13.
HVD3083E
SUPPLY CURRENT
vs
SIGNALING RATE
HVD3086E
SUPPLY CURRENT
vs
SIGNALING RATE
100
100
No Load
VCC = 5 V
TA = 25°C
50% Square wave input
No Load
VCC = 5 V
TA = 25°C
50% Square wave input
ICC − Supply Current − mA
ICC − Supply Current − mA
100
Signaling Rate − kbps
10
Driver and Receiver
1
Receiver Only
10
Driver and Receiver
1
Receiver Only
0.1
1
10
100
Signaling Rate − kbps
Figure 14.
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1k
0.1
0.001
0.01
0.1
1
10
100
Signaling Rate − Mbps
Figure 15.
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11
SN65HVD3080E
SN65HVD3083E
SN65HVD3086E
SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
5.0
5.0
TA = 25°C
VCC = 5 V
4.5
RL = 120 Ω
4.0
VO − Receiver Output Voltage − V
VOD − Differential Output Voltage − V
4.5
3.5
3.0
RL = 60 Ω
2.5
2.0
1.5
1.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0.0
0
10
20
30
40
IO − Differential Output Current − mA
Figure 16.
12
4.0
TA = 25°C
VCC = 5 V
VIC = 0.75 V
Submit Documentation Feedback
50
0.0
−200−180 −160 −140−120 −100 −80 −60 −40 −20
0
VID − Differential Input Voltage − V
Figure 17.
Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD3080E SN65HVD3083E SN65HVD3086E
SN65HVD3080E
SN65HVD3083E
SN65HVD3086E
www.ti.com
SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
APPLICATION INFORMATION
Hot-Plugging
These devices are designed to operate in “hot swap” or “hot pluggable” applications. Key features for hotpluggable applications are power-up, power-down glitch free operation, default disabled input/output pins, and
receiver failsafe. An internal Power-On Reset circuit keeps the outputs in a high-impedance state until the supply
voltage has reached a level at which the device will reliably operate. This ensures that no spurious transitions
(glitches) will occur on the bus pin outputs as the power supply turns on or turns off.
As shown in the device FUNCTION TABLES, the ENABLE inputs have the feature of default disable on both the
driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R
pin until the associated controller actively drives the enable pins.
Copyright © 2006–2012, Texas Instruments Incorporated
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Product Folder Links: SN65HVD3080E SN65HVD3083E SN65HVD3086E
13
SN65HVD3080E
SN65HVD3083E
SN65HVD3086E
SLLS771E – NOVEMBER 2006 – REVISED NOVEMBER 2012
www.ti.com
REVISION HISTORY
Changes from Revision B (March 2007) to Revision C
Page
•
Added D package ................................................................................................................................................................. 1
•
Added D package and information to Ordering Information ................................................................................................. 2
•
Added D package information to Power Dissipation Ratings ............................................................................................... 2
•
Changed Electrostatic Discharge Protection ........................................................................................................................ 2
•
Changed Supply Current information ................................................................................................................................... 3
•
Changed Receiver Switching Characteristics ....................................................................................................................... 5
•
Changed Figure 5 ................................................................................................................................................................. 7
•
Changed Figure 6 ................................................................................................................................................................. 7
Changes from Revision C (December 2009) to Revision D
Page
•
Added Differential input voltage dynamic to RECOMMENDED OPERATING CONDITIONS ............................................. 3
•
Added Figure 11 ................................................................................................................................................................... 9
Changes from Revision D (January 2011) to Revision E
Page
•
Added Power-Up, Power-Down Glitch-Free Operation to FEATURES ................................................................................ 1
•
Changed ENABLE in DRIVER FUNCTION TABLE from L to L or OPEN ........................................................................... 9
•
Changed ENABLE in RECEIVER FUNCTION TABLE from H to H or OPEN ..................................................................... 9
•
Added APPLICATION INFORMATION section .................................................................................................................. 13
14
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Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD3080E SN65HVD3083E SN65HVD3086E
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65HVD3080EDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
-40 to 85
BTT
SN65HVD3080EDGSG4
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
-40 to 85
BTT
SN65HVD3080EDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BTT
SN65HVD3083EDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BTU
SN65HVD3083EDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
-40 to 85
BTU
SN65HVD3086ED
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HVD3086E
SN65HVD3086EDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
-40 to 85
BTF
SN65HVD3086EDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BTF
SN65HVD3086EDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HVD3086E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
22-Jan-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD3080EDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65HVD3083EDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65HVD3086EDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65HVD3086EDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD3080EDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
SN65HVD3083EDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
SN65HVD3086EDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
SN65HVD3086EDR
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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