Texas Instruments | Low-Power 3.3V-Supply Full-Duplex RS-485 Driver/Receiver (Rev. A) | Datasheet | Texas Instruments Low-Power 3.3V-Supply Full-Duplex RS-485 Driver/Receiver (Rev. A) Datasheet

Texas Instruments Low-Power 3.3V-Supply Full-Duplex RS-485 Driver/Receiver (Rev. A) Datasheet
SN65HVD37
SLLSE92 A – OCTOBER 2011 – REVISED NOVEMBER 2011
www.ti.com
Low-Power 3.3V-Supply Full-Duplex RS-485 Driver/Receiver
Check for Samples: SN65HVD37
FEATURES
DESCRIPTION
•
•
•
The SN65HVD37 combines a robust differential driver
and a receiver with high noise immunity for
demanding industrial applications. The driver
differential outputs and the receiver differential inputs
are separate pins, to form a bus port for full-duplex
(four-wire) communications. The driver and receiver
can be independently enabled, and feature a wide
common-mode voltage range, making this device
suitable for multi-point applications over long cable
runs. The SN65HVD37 is characterized over the
temperature range of -40ºC to 85 ºC.
1
•
•
•
•
•
•
•
•
Low-Current Standby Mode: <1 μA Typical
Operational Quiescent Current < 1 mA
High Receiver Hysteresis for Noise Immunity
(60 mV Typical)
1/8 Unit-Load (Up to 256 Nodes on the Bus)
Bus-pin ESD Protection Exceeds 15 kV HBM
Driver Output Transition Times Optimized for
Signaling Rate up to 20 Mbps
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
5V-Tolerant Logic Inputs
Bus Idle, Open, and Short-Circuit Failsafe
Driver Current Limiting and Thermal Shutdown
Fully Meets All TIA-485-A Specifications
APPLICATIONS
•
•
•
•
•
•
Telecommunications Equipment
Industrial Automation
Process Automation
Building Automation
Point-of-Sale (POS) Terminals
Improved Replacement for ADM3076,
ADM3491, LTC2852, MAX3491 and SP3491
D PACKAGE (TOP VIEW)
NC
1
14
VCC
R
2
13
VCC
RE
3
12
A
DE
4
11
B
D
5
10
Z
GND
6
9
Y
GND
7
8
NC
NC - No internal connection
LOGIC DIAGRAM (POSITIVE LOGIC)
DE
4
9
D
RE
5
10
Z
3
12
R
Y
2
A
11
B
Figure 1. 60 mV Receiver Hysteresis for Noise Immunity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
SN65HVD37
SLLSE92 A – OCTOBER 2011 – REVISED NOVEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE/UNITS
VCC
Supply voltage
–0.5 V to 7 V
Voltage range at A, B, Y, Z pins
–13 V to 13 V
Input voltage range at any logic pin
–0.3 V to 5.7 V
–25 V to 25 V
Voltage range, transient pulse, A, B, Y, Z, through 100Ω
–24 mA to 24 mA
Receiver output current
TJ
Junction temperature
170°C
Continuous total power dissipation
IEC 60749-26 ESD
JEDEC Standard 22
JEDEC Standard 22
(1)
(see Thermal Table)
±16 kV
(Human Body Model), bus terminals and GND
±5 kV
Test Method A114 (Human Body Model), all pins
Test Method C101 (Charged Device Model), all pins
±1.5 kV
Test Method A115 (Machine Model), all pins
±150 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
SN65HVD37
THERMAL METRIC (1)
D
UNITS
14 PINS
θJA
Junction-to-ambient thermal resistance
79.3
θJCtop
Junction-to-case (top) thermal resistance
44.8
θJB
Junction-to-board thermal resistance
33.5
ψJT
Junction-to-top characterization parameter
13.3
ψJB
Junction-to-board characterization parameter
33.3
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage (1)
(2)
MIN
NOM
MAX
3
3.3
3.6
UNIT
V
VI
Input voltage at any bus terminal (separately or common mode)
–7
12
V
VIH
High-level input voltage (Driver, driver enable, and receiver enable inputs)
2
VCC
V
VIL
Low-level input voltage (Driver, driver enable, and receiver enable inputs)
0
0.8
V
VID
Differential input voltage
–12
12
V
Driver
–60
60
–8
8
IO
Output current
RL
Differential load resistance
CL
Differential load capacitance
Signaling rate
Receiver
54
60
Ω
50
pF
20
Mbps
TA
Operating free-air temperature (See application section for thermal information)
–40
85
°C
TJ
Junction Temperature
–40
150
°C
(1)
(2)
2
HVD37
mA
Both pins 13 and 14 should be connected to the supply voltage; both pins 6 and 7 should be connected to ground.
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
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SLLSE92 A – OCTOBER 2011 – REVISED NOVEMBER 2011
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
|VOD|
Driver differential output voltage
magnitude
TEST CONDITIONS
1.9
V
RL = 54 Ω (RS-485)
1.5
2
V
2
2.2
V
–0.1
0
0.1
V
1.5 VCC /2
2.5
V
0.1
V
Change in magnitude of driver differential
RL = 54 Ω, CL = 50 pF
output voltage
VOC(SS)
Steady-state common-mode output
voltage
ΔVOC
Change in differential driver output
common-mode voltage
VOC(PP)
Peak-to-peak driver common-mode
output voltage
CID
Differential input capacitance
COD
Differential output capacitance
VIT+
Positive-going receiver differential input
voltage threshold
VIT–
Negative-going receiver differential input
voltage threshold
VHYS
Receiver differential input voltage
threshold hysteresis (VIT+ – VIT–)
VOH
Receiver high-level output voltage
IOH = –8 mA
VOL
Receiver low-level output voltage
IOL = 8 mA
II
Driver input, driver enable, and receiver
enable input current
IOZ
Receiver output high-impedance current
IOS
Driver short-circuit output current
Center of two 27-Ω load
resistors, CL = 50 pF
See Figure 3
–0.1
See Figure 3
ICC
Supply current (dynamic)
(1)
0
400
mV
A, B
3
pF
Y, Z
14
pF
See
(1)
–60
–200
–120
30
60
2.4
VCC0.3
0.2
VO = 0 V or VCC, RE at VCC
See
(1)
mV
mV
mV
V
V
–2
2
μA
–1
1
μA
250
mA
VI = 12 V
75
VI = –7 V
–20
0.4
–250
VCC = 3 to 3.6 V or
VCC =0 V, DE at 0 V
–100
125
–40
μA
850
μA
DE = VCC, RE = VCC
400
μA
Driver disabled, receiver
enabled
DE = GND, RE = GND
800
μA
Driver and receiver disabled
(standby)
DE = GND, D = open,
RE = VCC
1
μA
Driver and Receiver enabled DE = VCC, RE = GND
Supply current, steady-state, no load
(quiescent)
UNIT
1.5
Δ|VOD|
Bus input current (disabled driver)
TYP MAX
See Figure 1, RL= 60 Ω, VCC ≥ 3.15 V,
375 Ω on each output to –7 V to 12 V
RL = 100 Ω (RS-422),
TJ ≥ 25°C, VCC ≥ 3.3 V
II
MIN
Driver enabled, receiver
disabled
720
0.2
See “TYPICAL CHARACTERISTICS” section
Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–.
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
UNIT
DRIVER
Driver differential output rise/fall
time
tr, tf
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
6
14
RL = 54 Ω, CL = 50 pF, See Figure 4
10
20
See Figure 5 and Figure 6
20
50
ns
8
25
ns
2.6
8
μs
1
Receiver enabled
Driver enable time
ns
See Figure 5 and Figure 6
Receiver disabled
RECEIVER
tr , tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew,
|tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tPZL(1), tPZH(1),
Receiver enable time
tPZL(2), tPZH(2)
CL = 15 pF, See Figure 7
2
5
9
ns
40
50
75
ns
2
5
ns
15
25
ns
Driver enabled, See Figure 8
35
50
ns
Driver disabled, See Figure 8
3
8
μs
DRIVER FUNCTION TABLE
INPUT
ENABLE
D
DE
Y
OUTPUTS
H
H
H
L
Actively drive bus High
L
H
L
H
Actively drive bus Low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus High by default
Z
RECEIVER FUNCTION TABLE
4
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VIT+ < VID
L
H
Receive valid bus High
VIT– < VID < VIT+
L
?
Indeterminate bus state
VID < VIT–
L
L
Receive valid bus Low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and DE Input
RE Input
VCC
VCC
130 kW
1.5 kW
1.5 kW
Input
Input
7V
7V
125 kW
A Input
B Input
VCC
VCC
R1
18 V
R1
18 V
R3
R3
Input
Input
18 V
R2
18 V
R2
R Output
Y and Z Outputs
VCC
VCC
18 V
1W
Output
18 V
SN65HVD37
Output
4V
R1/R2
R3
18 kΩ
190 kΩ
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PARAMETER MEASUREMENT INFORMATION
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω
375 Ω ±1%
VCC
DE
D
Y
VOD
0 or 3 V
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
Z
375 Ω ±1%
Figure 2. Measurement of Driver Differential Output Voltage With Common-mode Load
VCC
27 Ω ± 1%
DE
Y
D
Input
Y
VY
Z
VZ
VOC(PP)
27 Ω ± 1%
Z
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Figure 3. Measurement of Driver Differential and Common-mode Output with RS-485 Load
3V
VCC
CL = 54 pF ±20%
DE
Y
D
Input
Generator
VI
50 W
Z
VOD
CL Includes Fixture
and Instrumentation
Capacitance
RL = 54 W
±1%
1.5 V
VI
0V
tPHL
tPLH
VOD
1.5 V
0V
10%
90%
»2 V
90%
0V
10% »-2 V
tf
tr
Figure 4. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3V
Y
S1
D
3V
VI
VO
0V
t PZH
Z
DE
Input
Generator
VI
50 W
50%
50%
CL = 50 pF
±20%
RL = 110 W
±1%
VO
50%
V
90% OH
~0V
tPHZ
NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output.
CL includes Fixture and Instrumentation Capacitance
Figure 5. Measurement of Driver Enable and Disable Times with Active High Output and Pull-down Load
6
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PARAMETER MEASUREMENT INFORMATION (continued)
3V
RL = 110 Ω
± 1%
Y
3V
VI
S1
D
50 %
50 %
VO
0V
Z
DE
Input
Generator
3V
t PZL
t PLZ
3V
CL = 50 pF ±20%
VI
50 Ω
VO
50 %
10 %
VOL
NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output.
C L Includes Fixture and Instrumentation Capacitance
Figure 6. Measurement of Driver Enable and Disable Times with Active Low Output and Pull-up Load
A
R
Input
Generator
VI
50 Ω
1.5 V
B
50%
VI
50%
0V
CL = 15 pF
±20%
RE
0V
3V
VO
t PLH
CL Includes Fixture and Instrumentation Capacitance
VO
t PHL
VOH
90% 90%
50%
10%
tr
50%
10% V
OL
tf
Figure 7. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
0 V or 1.5 V
V CC
A
3V
R
1.5 V or 0 V
B
RE
Input
Generator
VI
1 k W ±1%
VO
S1
C L = 15 pF
±20%
VI
0V
t PZH(1)
50 W
C L Includes Fixture and
Instrumentation Capacitance
50%
50%
VO
t PHZ
V OH
50%
50%
~0 V
t
t
PZL(1)
D at 3 V
S1 to GND
PLZ
VCC
VO
1.5 V
V OL
D at 0 V
S1 to VCC
Figure 8. Measurement of Receiver Enable/Disable Times
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SIGNALING RATE
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
3.5
65
RL = 54 W,
CL = 50 pF
VOD - Differential Output Voltage - V
ICC - Supply Current - mA
60
VCC = 3.6 V
VCC = 3 V
VCC = 3.3 V
55
VCC = 3.6 V
50
45
40
35
3.0
2.0
1.5
1.0
RL = 60 W
0.5
VCC = 3 V
0
30
0
5
10
Signaling Rate - Mbps
15
20
0
Figure 10.
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
RECEIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
80
90
75
VID = ±1.5 V,
CL = 15 pF
3.0
70
VCM = 12 V
Propagation Delay - ns
2.5
2.0
VCM = -7 V
1.5
60
70
10
20
30
40
50
IOD - Differential Output Current - mA
Figure 9.
3.5
VO - Output Voltage - V
VCC = 3.3 V
2.5
VCM = 1.65 V
1.0
65
VCC = 3 V
VCC = 3.3 V
60
VCC = 3.6 V
55
0.5
0
-200
-150 -100 -50
0
100
50
VID - Differential Input Voltage - mV
150
200
50
-40
Figure 11.
8
-20
0
20
40
60
TA - Free-Air Temperature -° C
80
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
DRIVER RISE/FALL TIME
vs
FREE-AIR TEMPERATURE
7.5
7.0
VCC = 3.6 V,
RL = 54,
CL = 50 pF
Rise/Fall Time - ns
6.5
6.0
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
5.5
5.0
4.5
4.0
3.5
-40
-20
0
20
40
60
TA - Free-Air Temperature -° C
Figure 13.
80
Master Node
Slave Node
Slave Node
Slave Node
Figure 14. Example Full-Duplex Master/Slave Application Circuit
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APPLICATION INFORMATION
RECEIVER FAILSAFE
The differential receiver is “failsafe” to invalid bus states caused by:
• open bus conditions such as a disconnected connector,
• shorted bus conditions such as cable damage shorting the twisted-pair together,
• or idle bus conditions that occur when no driver on the bus is actively driving.
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the
receiver is not indeterminate.
In the HVD37, receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input
indeterminate” range does not include zero volts differential. In order to comply with the RS-422 and RS-485
standards, the receiver output must output a High when the differential input VID is more positive than 200 mV,
and must output a Low when the VID is more negative than -200 mV. The receiver parameters which determine
the failsafe performance are VIT+ and VIT- and VHYS. In the Electrical Characteristics table, VIT- has a typical value
of -120 mV and a minimum (most negative) value of -200 mV, so differential signals more negative than -200 mV
will always cause a Low receiver output. Similarly, differential signals more positive than 200 mV will always
cause a High receiver output, because the typical value of VIT+ is -60mV, and VIT+ is never more positive than
-20 mV under any conditions of temperature, supply voltage, or common-mode offset.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output
will be High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low
state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis
value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+.
For the HVD37, the typical noise immunity is about 120 mV, which is the negative noise level needed to exceed
the VIT- threshold (VIT- TYP = -120 mV). In the worst case, the failsafe noise immunity is never less than 50 mV,
which is set by the maximum positive threshold (VIT+ MAX = -20mV) plus the minimum hysteresis voltage (VHYS
MIN = 30 mV).
HOT-PLUGGING
These devices are designed to operate in “hot swap” or “hot pluggable” applications. Key features for
hot-pluggable applications are power-up, power-down glitch free operation, default disabled input/output pins,
and receiver failsafe. An internal Power-On Reset circuit keeps the driver outputs in a high-impedance state until
the supply voltage has reached a level at which the device will reliably operate. This ensures that no spurious
transitions (glitches) will occur on the bus pin outputs as the power supply turns on or turns off.
As shown in the device FUNCTION TABLE, the ENABLE inputs have the feature of default disable on both the
driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R
pin until the associated controller actively drives the enable pins.
LOW POWER STANDBY MODE
As is customary with RS-485 devices, the receiver output is directly enabled/disabled by RE, and the driver
outputs are directly enabled/disabled by DE.
When both the driver and receiver are disabled, (DE=LO and RE=HI) the receiver differential comparator stage
enters a standby mode for reduced power.
When either the Driver or Receiver is enabled, the receiver differential comparator stage is enabled for fast
response to signal changes.
SPACER
10
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REVISION HISTORY
Changes from Original (October 2011) to Revision A
•
Page
Changed the device From: Product Preview To: Production ................................................................................................ 1
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN65HVD37D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HVD37
SN65HVD37DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HVD37
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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