Texas Instruments | SymPol Transceiver. (Rev. B) | Datasheet | Texas Instruments SymPol Transceiver. (Rev. B) Datasheet

Texas Instruments SymPol Transceiver. (Rev. B) Datasheet
SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
www.ti.com
SymPol™ Transceiver
Check for Samples: SN65HVD96
FEATURES
•
1
•
2
•
•
•
•
•
Communicate Without Errors on Normal or
Reversed-Wire Bus Lines
Up to 5 Mbps Signaling
Industrial Temperature Range: –40°C to 85°C
Symmetric Polarity Receiver
Receiver Hysteresis > 100 mV
Connect up to 32 Nodes Plus Parallel
Terminators on one Bus, or Connect up to 200
Nodes on an Unterminated Bus
•
•
Transient Protection
– ±12 kV Human Body Model on Bus Pins
– ±25 V Repetitive Transient Pulse on Bus
Pins
Additional Reliability Features:
– Bus Standoff From –35 V to 40 V
– Driver Output Short-Circuit Current Limit
– Automatic Thermal Shutdown and
Recovery
Complies with ANSI/TIA-4963 Standard
DESCRIPTION
The SN65HVD96 is specifically designed to meet the requirements for a transceiver which operates with no
errors if the twisted-pair signal wires are connected normally or reversed. This allows for error free operation in
applications where the signal wires may become inadvertently reversed during installation or maintenance. This
feature is corrected internally so no intervention from the controller or operator is required. The SN65HVD96
complies with the requirements of ANSI/TIA-4963, Electrical Characteristics of Reversible Balanced Voltage
Digital Interface Circuits.
Similar to RS-485, these transceivers can be used for point-to-point, multi-drop, or multi-point networks.
Sympol™ devices are not backwards compatible with, but are an upgrade to, existing RS-485 networks. The
pin-out is identical to the industry-standard SN75176 transceiver, allowing direct upgrade from RS-485 to
SymPol. Current-limited differential outputs protect in case of driver contention on a party-line bus. High receiver
input impedance allows connection of at least 32 nodes. Several fault tolerant features are integrated into the
device to protect from operational hazards. Current limiting on the driver outputs protects against short-circuit
faults, and operates independently on each driver output. An automatic thermal shutdown protects the driver
circuits against over temperature conditions. The receiver output enters a deterministic failsafe state if the bus
connection is left disconnected or if the bus wires are shorted together.
The small outline integrated circuit (SOIC) package saves board space compared to equivalent discrete
implementations. These devices are fully characterized for operation over the industrial temperature range
of –40°C to 85°C.
SN65HVD96
R
RE
DE
Driver signaling(DE = high)
8
1
D
A or B
B
B or A
A
|VID|
2
3
VOD
7
D
Vcc
4
Receiver detecting(RE = low)
passive
active
passive
active
R
B
6
A
Temp.
SHDN
5
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Sympol is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
Supply voltage, VCC
–0.5 to 6
V
Voltage range at A or B
–35 to 40
V
–0.3 to VCC+0.3
V
Voltage input range, transient pulse, A and B, through 100Ω
±25
V
Voltage input transient pulse, A and B, per ISO 7637
±200
V
–75 to +75
V
Electro-static discharge per JEDEC Std. 22 A114, A and B pins, Human Body Model
±12
kV
Electro-static discharge per JEDEC Std. 22 A114, all pins, Human Body Model
±5
kV
Electro-static discharge per JEDEC Std. 22 C101, all pins, Charged Device Model
±2
kV
Voltage range at logic pins (D, DE, RE)
Differential voltage, VA – VB
Electro-static discharge per JEDEC Std. 22 A115, all pins, Machine Model
±200
V
Receiver output current
±20
mA
170
°C
Junction temperature, TJ
Continuous total power dissipation
(1)
(see Dissipation Rating Table)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
SN65HVD96
THERMAL METRIC (1)
θJA
Junction-to-ambient thermal resistance (2)
θJC(top)
Junction-to-case(top) thermal resistance
θJB
Junction-to-board thermal resistance
UNITS
124.5
(3)
55.9
(4)
50.2
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
θJC(bottom)
8 PINS SOIC
Junction-to-case(bottom) thermal resistance
4.9
(6)
°C/W
46.0
(7)
n/a
TEST CONDITIONS
Pd
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
2
Power Dissipation
VCC = 5.25 V, TJ = 150°C, RL = 300 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver), unterminated (8)
188
VCC = 5.25 V, TJ = 150°C, RL = 100 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver), RS-422 load (8)
251
VCC = 5.25 V, TJ = 150°C, RL = 54 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver), RS-485 load (8)
319
mW
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Driver and receiver enabled, 50% duty cycle square-wave signal at 5 Mbps.
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SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
–7
12
V
2
VCC
V
0
0.8
V
–12
12
V
70
mA
2
mA
0
5
Mbps
–40
85
°C
VCC
Supply voltage
VI
Input voltage at any bus terminal (separately or common mode) (1)
VIH
High-level input voltage (Driver, driver enable, and receiver enable inputs)
VIL
Low-level input voltage (Driver, driver enable, and receiver enable inputs)
VID
Differential input voltage
IO
Output current, Driver
–70
IO
Output current, Receiver
–2
RL
Differential load resistance
54
1/tUI
Signaling rate
TA
Operating free-air temperature
(1)
Ω
60
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
|VOD(ACT)|
TEST CONDITIONS
Driver differential output voltage
magnitude (active)
MIN
RS-485 common-mode load, see Figure 2
1.5
RS-485 differential load RL = 54 Ω,
CL = Open, see Figure 3
1.5
RS-422 differential load RL = 100 Ω,
CL = Open, see Figure 3
|VOD(PAS)|
Driver differential output voltage
magnitude (passive)
TYP
MAX
UNIT
V
2
RS-485 common-mode load, See Figure 2
50
RS-485 differential load RL = 54 Ω,
CL = Open, see Figure 3
20
RS-422 differential load RL = 100 Ω,
CL = Open, see Figure 3
25
No Load
50
mV
VOC(SS)
Steady-state common-mode output
voltage
Voc = (VA + VB) / 2
RL = 54Ω
ΔVOC
Change in differential driver output
common-mode voltage
Voc(D=High) – Voc(D=Low)
RL = 54Ω
VIT(ACT)
Active-going receiver differential input
threshold
VID = VA – VB or VID = VB – VA
VIT(PASS)
Passive-going receiver differential input
threshold
500
625
mV
VHYS
Receiver differential input threshold
hysteresis (VIT(ACT) - VIT(PASS))
100
150
mV
VOH
Receiver high-level output voltage
–20 µA ≥ IO ≥ –2 mA
VOL
Receiver low-level output voltage
20 µA ≤ IO ≤ 2 mA
II
Logic pins input current
IOZ
Receiver output high-impedance current
VO = 0 V or Vcc, RE at Vcc
IOS
Driver short-circuit output current
–7 V < Vo < +12 V
II
Bus input current (passive driver)
Vcc = 4.75 to 5.25 V or
Vcc=0V, DE at 0V, other
bus pin at 0V
ICC
Supply current (quiescent), no load
RID
Differential input resistance
1
Vcc/2
–0.2
775
2.4
DE at OV, Vcm = Vcc/2
V
0.2
V
900
mV
3.7
V
–100
100
μA
–10
10
uA
–350
350
mA
1
mA
–0.8
24
mA
40
20
mA
57
kΩ
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V
0.4
VI = 12 V
VI = –7 V
3
3
SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER
trise , tfall
Driver differential output rise/fall time
15
30
ns
tpAP , tpPA
Driver propagation delay
40
80
ns
tSK(P)
Driver differential output pulse skew,
|tpAP – tpPA|
1
10
ns
tpZA, tpAZ
Driver enable/disable time
D = GND, RL= 54 Ω, CL= 50 pF,
See Figure 4
50
80
ns
8
15
ns
CL= 15 pF, See Figure 5
70
90
ns
5
15
ns
20
100
ns
RL= 54 Ω, CL= 50 pF, See Figure 3
RECEIVER
trise, tfall
Receiver output rise/fall time
tPHL , tPLH
Receiver propagation delay time
tSK(P)
Receiver output pulse skew,|tPHL – tPLH|
tPZL, tPZH,
tPLZ, tPHZ
Receiver enable/disable time
See Figure 6
FUNCTION TABLE
DRIVER
DE
D
VOD
L or OPEN
X
Z
Driver Disabled (Passive)
L
H
Driver Active
H or Open
Z
Driver Passive
VID
R
X
Z
Receiver Disabled
VID < –0.9 V
L
Active Bit Received
–0.9 V < VID < –0.5
?
Indeterminate bus
–0.5 V < VID < 0.5 V
H
Passive Bit Received
0.5 V < VID < 0.9 V
?
Indeterminate bus
0.9 V < VID
L
Active Bit Received
Open, Short, Idle
H
Failsafe Condition
H
RECEIVER
RE
H or OPEN
L
4
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SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
www.ti.com
DEVICE INFORMATION
DE Input
D and /RE Input
Vcc
Vcc
4.3 k ?
4.3 k ?
Input
Input
6V
6V
140 k?
A and B Outputs
A and B Input
Vcc
Vcc / 2
39 k?
3k ?
Input
36 k ?
B
A
40 V
40 V
3.3 V
40 V
R Output
15 ?
Output
6V
Figure 1. Equivalent Input and Output Schematic Diagrams
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5
SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
www.ti.com
APPLICATION INFORMATION
Sympol™ States
Differential Output Voltage - V
4
VCC = 5 V
3
VCC = 4.75 V
2
1
0
0
20
40
60
80
100
120
Differential Load Resistance - W
140
Using Sympol to Achieve Immunity to Crossed Bus Wire
Many applications which use RS-422 or RS-485 are wired on-site by third-party installers. This opens the door to
the possibility of miss-wiring, especially for far-flung networks with many stations (or nodes). Neither RS-422 nor
RS-485 allows correct communications when the bus wires (typically a twisted-pair) are swapped.
The existing solutions for this case require active intervention, either by the installer or maintenance technician,
or by an automated controller. Sympol offers a way to replace RS-422 or RS-485 networks with communication
over the same bus lines. Due to the innovative nature of Sympol signaling levels, a Sympol network is immune to
communication errors caused by crossed bus wires.
Signaling levels are similar to RS-422 and RS-485, so signaling rates, cable lengths, and noise immunity will be
comparable.
Sympol is NOT interoperable with RS-422 or RS-485; that is, designers may not mix Sympol nodes with existing
RS-485 nodes.
6
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SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
www.ti.com
Number of Nodes
The SN65HV96 specifications for bus-pin impedance are similar to a standard one unit-load (1 UL) RS-485
device. This allows designers to attach up to 32 nodes plus two parallel termination resistors on a single bus
segment. In applications where the standard trunk-and-stub arrangement of RS-485 is not practical, or if
mis-termination may occur during installation, it may be desirable to not use parallel termination on the bus lines.
In these applications, the number of nodes allowed can be up to about 200, while still maintaining high driver
output amplitude. The bus pin impedance is approximated as 12 kΩ, therefore 200 devices in parallel present
differential loading similar to the 60 Ω termination resistance.
PARAMETER MEASUREMENT INFORMATION
Input generator rate is 100kbps, 50% duty-cycle, transition times less than 6 ns for all figures.
Figure 2. Measurement of Driver Differential Output Voltage With Common-Mode Load
3V
D
50 %
0V
B
D
Generator
RL
CL
tpAP
VOD
tpPA
90 %
A
90 %
VOD
DE
50 %
10 %
VCC
trise
tfall
Figure 3. Measurements of Driver Differential Output Rise and Fall Times and Propagation delays
3V
DE
B
GND
D
50%
RL
CL
VOD
tpAZ
tpZA
0V
A
Signal
Generator
VOD
DE
50%
Figure 4. Measurements of Driver Enable and Disable Times With Active Output
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SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
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PARAMETER MEASUREMENT INFORMATION (continued)
1.5 V
700 mV
V
ID
A/B
0V
R
V ID
tpLH
B/A
RE
tpHL
CL
V OH
90%
R
1.5 V
10%
tr
V OL
tf
Figure 5. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
3V
3 .3 V
50%
RE
A/B
R
1 kW
0V
t pZL
t pLZ
3.3V
V ID
B/A
RE
C L = 15 pF
(includes probe and
jig capacitance)
Signal
Generator
R
|V ID|=1.5V
50%
VOL +0.5V
t pZH
R
|V ID|=0V
VOH -0.5V
50%
t pHZ
VOL
VOH
0V
Figure 6. Measurement of Receiver Enable Times With Driver Disabled
8
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SN65HVD96
SLLSE35B – JUNE 2010 – REVISED NOVEMBER 2011
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REVISION HISTORY
Changes from Original (June 2010) to Revision A
Page
•
Changed the 4th bullet in Features to 2 bulleted items ........................................................................................................ 1
•
Changed the 6th bullet in Features to read "Connect up to 32 Nodes Plus Parallel Terminators on one Bus, or
Connect up to 200 Nodes on an Unterminated Bus" ............................................................................................................ 1
•
Deleted italics from party line and failsafe in second paragraph .......................................................................................... 1
•
Added to protect after Several fault......into the device sentence, second paragraph .......................................................... 1
•
Changed in abs max table from 7V to 6V ............................................................................................................................. 2
•
Deleted deleted 'dc' from the VALUE column in 2nd and 4th parameter ............................................................................. 2
•
Added commas after the name of the test specification, A224, 2 places, C101 and A115. Added the word pins after
A and B in the first Human Body Model row ......................................................................................................................... 2
•
Deleted 290 in the THERMAL Table from the first cell under TEST Conditions. Deleted 5V supply from all three
cells. ...................................................................................................................................................................................... 2
•
Added typical characteristics graph to Application Information Section ............................................................................... 6
•
Added section to Application Information titled Number of Nodes ....................................................................................... 7
Changes from Revision A (December 2010) to Revision B
Page
•
Changed revision A, December 2010 to Rev B, October 2011 ............................................................................................ 1
•
Added new ListItem to the FEATURES: 'Complies .....Standard' ......................................................................................... 1
•
Added last sentence to the first paragraph of DESCRIPTION ............................................................................................. 1
•
Added Differential voltage.......V row to the ABS MAX RATINGS table ............................................................................... 2
•
Added differential input resistance specification to Electrical Characteristics table. ............................................................ 3
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN65HVD96D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HVD96
SN65HVD96DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HVD96
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65HVD96DR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD96DR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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