Texas Instruments | 3-V to 5.5-V Multichannel RS-232 Line Driver/Receiver, TRS3243E (Rev. C) | Datasheet | Texas Instruments 3-V to 5.5-V Multichannel RS-232 Line Driver/Receiver, TRS3243E (Rev. C) Datasheet

Texas Instruments 3-V to 5.5-V Multichannel RS-232 Line Driver/Receiver, TRS3243E (Rev. C) Datasheet
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
3-V TO 5.5-V MULTICHANNEL RS-232 LINE DRIVER/RECEIVER
WITH ±15-kV IEC ESD PROTECTION
Check for Samples: TRS3243E
FEATURES
1
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
32 31
30
29
28 27
26
N.C.
VCC
V+
C1+
C2+
QFN PACKAGE
(TOP VIEW)
25
RIN1
1
24
GND
RIN2
2
23
C1–
RIN3
3
22
FORCEON
RIN4
4
21
FORCEOFF
RIN5
5
20
INVALID
DOUT1
6
19
ROUTB2
DOUT2
7
18
ROUT1
DOUT3
8
17
ROUT2
9
10
11
12
13 14
15
16
N.C.
Battery-Powered Systems
PDAs
Notebooks
Laptops
Palmtop PCs
Hand-Held Equipment
25
5
ROUT3
•
•
•
•
•
•
26
4
C1+
V+
VCC
GND
C1−
FORCEON
FORCEOFF
INVALID
ROUT2B
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT4
APPLICATIONS
27
3
ROUT5
•
2
C2–
•
•
28
DIN1
•
•
•
•
1
DIN2
•
V–
•
•
C2+
C2−
V−
RIN1
RIN2
RIN3
RIN4
RIN5
DOUT1
DOUT2
DOUT3
DIN3
DIN2
DIN1
N.C.
•
DB, DW, OR PW PACKAGE
(TOP VIEW)
N.C.
•
Single-Chip and Single-Supply Interface for
IBM™ PC/AT™ Serial Port
ESD Protection for RS-232 Bus Pins
– ±15-kV Human-Body Model (HBM)
– ±8-kV IEC61000-4-2, Contact Discharge
– ±15-kV IEC61000-4-2, Air-Gap Discharge
Meets or Exceeds Requirements of
TIA/EIA-232-F and ITU v.28 Standards
Operates With 3-V to 5.5-V VCC Supply
Always-Active Noninverting Receiver Output
(ROUT2B)
Designed to Transmit at a Data Rate up to
500 kbit/s
Low Standby Current . . . 1 μA Typ
External Capacitors . . . 4 × 0.1 μF
Accepts 5-V Logic Input With 3.3-V Supply
Designed to Be Interchangeable With Industry
Standard '3243E Devices
Serial-Mouse Driveability
Auto-Powerdown Feature to Disable Driver
Outputs When No Valid RS-232 Signal Is
Sensed
Package Options Include Plastic Small-Outline
(DW), Shrink Small-Outline (DB), and Thin
Shrink Small-Outline (PW) Packages
DIN3
•
2
N.C. − Not internally connected
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IBM, PC/AT are trademarks of International Business Machines Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2011, Texas Instruments Incorporated
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
DESCRIPTION/ORDERING INFORMATION
The TRS3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with
±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)
protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides the
electrical interface between an asynchronous communication controller and the serial-port connector. This
combination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, or
compatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V
supply. In addition, the device includes an always-active noninverting output (ROUT2B), which allows
applications using the ring indicator to transmit data while the device is powered down. The device operates at
data signaling rates up to 250 kbit/s and a maximum of 30-V/μs driver output slew rate.
Flexible control options for power management are available when the serial port is inactive. The
auto-powerdown feature functions when FORCEON is low and FORCEOFF is high. During this mode of
operation, if the device does not sense a valid RS-232 signal, the driver outputs are disabled. If FORCEOFF is
set low, both drivers and receivers (except ROUT2B) are shut off, and the supply current is reduced to 1 μA.
Disconnecting the serial port or turning off the peripheral drivers causes the auto-powerdown condition to occur.
Auto-powerdown can be disabled when FORCEON and FORCEOFF are high, and should be done when driving
a serial mouse. With auto-powerdown enabled, the device is activated automatically when a valid signal is
applied to any receiver input. The INVALID output is used to notify the user if an RS-232 signal is present at any
receiver input. INVALID is high (valid data) if any receiver input voltage is greater than 2.7 V or less than –2.7 V
or has been between –0.3 V and 0.3 V for less than 30 μs. INVALID is low (invalid data) if all receiver input
voltages are between –0.3 V and 0.3 V for more than 30 μs. Refer to Figure 5 for receiver input levels.
The TRS3243EC is characterized for operation from 0°C to 70°C. The TRS3243EI is characterized for operation
from –40°C to 85°C.
Table 1. ORDERING INFORMATION
PACKAGE (1)
TA
0°C to 70°C
–40°C to 85°C
(1)
2
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SSOP – DB
Reel of 2000
TRS3243ECDBR
TRS3243EC
SOP – DW
Reel of 2000
TRS3243ECDWR
TRS3243EC
TSSOP – PW
Reel of 2000
TRS3243ECPWR
RS43EC
QFN – RHB
Reel of 2000
TRS3243ECRHBR
RS43EC
SSOP – DB
Reel of 2000
TRS3243EIDBR
TRS3243ECI
SOP – DW
Reel of 2000
TRS3243EIDWR
TRS3243ECI
TSSOP – PW
Reel of 2000
TRS3243EIPWR
RS43EI
QFN – RHB
Reel of 2000
TRS3243EIRHBR
RS43EI
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
FUNCTION TABLES
ABC
Each Driver (1)
INPUTS
DIN
(1)
FORCEON
OUTPUT
FORCEOFF
VALID RIN
RS-232 LEVEL
DRIVER STATUS
DOUT
X
X
L
X
Z
Powered off
L
H
H
X
H
H
H
H
X
L
Normal operation with
auto-powerdown disabled
L
L
H
Yes
H
H
L
H
Yes
L
X
L
H
No
Z
Normal operation with
auto-powerdown enabled
Powered off by auto-powerdown
feature
H = high level, L = low level, X = irrelevant, Z = high impedance
Each Receiver (1)
INPUTS
(1)
OUTPUT
RIN
FORCEON
FORCEOFF
ROUT
X
X
L
Z
L
X
H
H
H
X
H
L
Open
X
H
H
RECEIVER STATUS
Powered off
Normal operation with
auto-powerdown disabled/enabled
H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off
ROUT2B and Outputs INVALID
(1)
INPUTS
VALID RIN
RS-232 LEVEL
(1)
OUTPUTS
RIN2
FORCEON
FORCEOFF
INVALID
ROUT2B
Yes
L
X
X
H
L
Yes
H
X
X
H
H
Yes
Open
X
X
H
L
No
Open
X
X
L
L
OUTPUT STATUS
Always active
H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off
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TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
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LOGIC DIAGRAM (POSITIVE LOGIC)
DIN1
DIN2
DIN3
FORCEOFF
FORCEON
ROUT1
ROUT2B
ROUT2
ROUT3
ROUT4
ROUT5
4
14
9
13
10
12
11
DOUT1
DOUT2
DOUT3
22
23
Auto-powerdown
19
21
4
INVALID
RIN1
20
18
5
17
6
16
7
15
8
RIN2
RIN3
RIN4
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RIN5
Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TRS3243E
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
(2)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.3
6
V
V+
Positive output supply voltage range (2)
–0.3
7
V
V–
Negative output supply voltage range (2)
0.3
–7
V
V+ – V–
Output supply voltage difference (2)
13
V
VI
Input voltage range
VO
Output voltage range
θJA
Package thermal impedance (3)
Driver (FORCEOFF, FORCEON)
–0.3
6
Receiver
–25
25
–13.2
13.2
–0.3
VCC + 0.3
Driver
Receiver (INVALID)
(4)
DB package
62
DW package
46
PW package
(1)
(2)
(3)
(4)
V
°C/W
62
Lead temperature 1,6 mm (1/16 in) from case for 10 s
Tstg
V
–65
Storage temperature range
260
°C
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network GND.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) - TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
See Figure 6
VCC = 3.3 V
Supply voltage
VCC = 5 V
VIH
Driver and control high-level input voltage
DIN, FORCEOFF, FORCEON
VIL
Driver and control low-level input voltage
DIN, FORCEOFF, FORCEON
VI
Driver and control input voltage
DIN, FORCEOFF, FORCEON
VI
Receiver input voltage
TA
(1)
VCC = 3.3 V
NOM
MAX UNIT
3
3.3
3.6
4.5
5
5.5
V
2
VCC = 5 V
V
2.4
TRS3243EC
Operating free-air temperature
MIN
TRS3243EI
0.8
V
0
5.5
V
–25
25
V
0
70
–40
85
°C
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)
PARAMETER
II
ICC
(1)
(2)
Input leakage current
Supply current
(TA = 25°C)
TEST CONDITIONS
FORCEOFF, FORCEON
MIN
TYP (2) MAX
UNIT
±0.01
±1
μA
0.3
1
mA
Auto-powerdown disabled
No load,
FORCEOFF and FORCEON at VCC
Powered off
No load, FORCEOFF at GND
1
10
Auto-powerdown enabled
No load, FORCEOFF at VCC,
FORCEON at GND,
All RIN are open or grounded,
All DIN are grounded
1
10
μA
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
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TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
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DRIVER SECTION
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)
PARAMETER
MIN TYP (2) MAX
TEST CONDITIONS
UNIT
VOH
High-level output voltage
All DOUT at RL = 3 kΩ to GND
5
5.4
V
VOL
Low-level output voltage
All DOUT at RL = 3 kΩ to GND
–5
–5.4
V
VO
Output voltage
(mouse driveability)
DIN1 = DIN2 = GND, DIN3 = VCC, 3-kΩ to GND at DOUT3,
DOUT1 = DOUT2 = 2.5 mA
±5
IIH
High-level input current
VI = VCC
±0.01
±1
μA
IIL
Low-level input current
VI at GND
±0.01
±1
μA
Vhys
Input hysteresis
±1
V
±60
mA
±25
μA
VCC = 3.6 V,
VO = 0 V
VCC = 5.5 V,
VO = 0 V
IOS
Short-circuit output current (3)
rO
Output resistance
VCC, V+, and V– = 0 V,
VO = ±2 V
Ioff
Output leakage current
FORCEOFF = GND,
VO = ±12 V,
(1)
(2)
(3)
300
V
Ω
10M
VCC = 0 to 5.5 V
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.
Switching Characteristics (1)
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted) (see Figure 6)
TEST CONDITIONS
MIN
TYP (2)
Maximum data rate
CL = 1000 pF,
One DOUT switching,
RL = 3 kΩ
See Figure 1
250
500
kbit/s
tsk(p)
Pulse skew (3)
CL = 150 pF to 2500 pF,
RL = 3 kΩ to 7 kΩ, See Figure 2
100
ns
Slew rate, transition region
(see Figure 1)
VCC = 3.3 V,
RL = 3 kΩ to 7 kΩ,
PRR = 250 kbit/s
CL = 150 pF to 1000 pF
6
30
SR(tr)
CL = 150 pF to 2500 pF
4
30
PARAMETER
(1)
(2)
(3)
MAX
UNIT
V/μs
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V + 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
ESD Protection
PARAMETER
Driver outputs (pins 9–11)
6
TEST CONDITIONS
TYP
HBM
±15
IEC61000-4-2, Air-Gap Discharge
±15
IEC61000-4-2, Contact Discharge
±8
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UNIT
kV
Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TRS3243E
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
RECEIVER SECTION
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –1 mA
VOL
Low-level output voltage
IOH = 1.6 mA
TYP (2)
VCC – 0.6
VCC – 0.1
MAX
0.4
1.6
2.4
VCC = 5 V
1.9
2.4
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input hysteresis (VIT+ – VIT– )
Ioff
Output leakage current (except ROUT2B)
FORCEOFF = 0 V
ri
Input resistance
VI = ±3 V or ±25 V
VCC = 3.3 V
0.6
1.1
VCC = 5 V
0.8
1.4
UNIT
V
VCC = 3.3 V
VIT+
(1)
(2)
MIN
V
V
V
0.5
V
±0.05
±10
μA
5
7
kΩ
3
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Switching Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low- to high-level output
tPHL
Propagation delay time, high- to low-level output
ten
Output enable time
tdis
Output disable time
tsk(p)
Pulse skew (3)
(1)
(2)
(3)
CL = 150 pF, See Figure 3
CL = 150 pF, RL = 3 kΩ, See Figure 4
See Figure 3
TYP (2)
UNIT
150
ns
150
ns
200
ns
200
ns
50
ns
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH - tPHL| of each channel of the same device.
ESD Protection
PARAMETER
Driver outputs (pins 4–8)
TEST CONDITIONS
TYP
HBM
±15
IEC61000-4-2, Air-Gap Discharge
±15
IEC61000-4-2, Contact Discharge
±8
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UNIT
kV
7
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
AUTO-POWERDOWN SECTION
Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
MIN
VIT+(valid)
Receiver input threshold
for INVALID high-level output voltage
FORCEON = GND,
FORCEOFF = VCC
VIT–(valid)
Receiver input threshold
for INVALID high-level output voltage
FORCEON = GND,
FORCEOFF = VCC
–2.7
VT(invalid)
Receiver input threshold
for INVALID low-level output voltage
FORCEON = GND,
FORCEOFF = VCC
–0.3
VOH
INVALID high-level output voltage
IOH = -1 mA, FORCEON = GND,
FORCEOFF = VCC
VOL
INVALID low-level output voltage
IOL = 1.6 mA, FORCEON = GND,
FORCEOFF = VCC
MAX
UNIT
2.7
V
V
0.3
V
VCC – 0.6
V
0.4
V
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
TYP (1)
UNIT
tvalid
Propagation delay time, low- to high-level output
VCC = 5 V
1
μs
tinvalid
Propagation delay time, high- to low-level output
VCC = 5 V
30
μs
ten
Supply enable time
VCC = 5 V
100
μs
(1)
8
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
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PARAMETER MEASUREMENT INFORMATION
3V
Generator
(see Note B)
Input
RS-232
Output
50 Ω
RL
CL
(see Note A)
3V
FORCEOFF
TEST CIRCUIT
0V
Output
SR(tr) +
tTLH
tTHL
6V
t THL or tTLH
VOH
3V
3V
−3 V
−3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 1. Driver Slew Rate
3V
Generator
(see Note B)
RS-232
Output
50 Ω
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPHL
tPLH
VOH
3V
FORCEOFF
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 2. Driver Pulse Skew
3 V or 0 V
FORCEON
3V
Input
1.5 V
1.5 V
−3 V
Output
Generator
(see Note B)
tPHL
50 Ω
3V
FORCEOFF
tPLH
CL
(see Note A)
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 3. Receiver Propagation Delay Times
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PARAMETER MEASUREMENT INFORMATION
3V
Input
VCC
3 V or 0 V
FORCEON
1.5 V
GND
S1
−3 V
tPZH
(S1 at GND)
tPHZ
(S1 at GND)
RL
3 V or 0 V
1.5 V
VOH
Output
50%
Output
CL
(see Note A)
FORCEOFF
Generator
(see Note B)
50 Ω
0.3 V
tPZL
(S1 at VCC)
tPLZ
(S1 at VCC)
0.3 V
Output
50%
VOL
TEST CIRCUIT
NOTES: A.
B.
C.
D.
VOLTAGE WAVEFORMS
CL includes probe and jig capacitance.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
Figure 4. Receiver Enable and Disable Times
10
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PARAMETER MEASUREMENT INFORMATION
2.7 V
2.7 V
0V
Receiver
Input
0V
−2.7 V
−2.7 V
ROUT
Generator
(see Note B)
50 Ω
3V
tinvalid
tvalid
50% VCC
50% VCC
−3 V
VCC
Autopowerdown
ten
INVALID
≈V+
V+
CL = 30 pF
(see Note A)
0.3 V
VCC
0V
0.3 V
Supply
Voltages
FORCEOFF
FORCEON
0V
INVALID
Output
DIN
DOUT
V−
TEST CIRCUIT
≈V−
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VOLTAGE WAVEFORMS
Valid RS-232 Level, INVALID High
2.7 V
Indeterminate
0.3 V
0V
−0.3 V
If Signal Remains Within This Region
For More Than 30 µs, INVALID Is Low†
Indeterminate
−2.7 V
Valid RS-232 Level, INVALID High
†
Auto-powerdown disables drivers and reduces supply
current to 1 µA.
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 5 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 5. INVALID Propagation Delay Times and Supply Enabling Time
Submit Documentation Feedback
Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TRS3243E
11
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
C1+
1
+
C2
−
2
3
C2−
VCC
V−
GND
+
C1−
RIN1
RIN2
RIN3
RS-232 Inputs
RIN4
RIN5
DOUT1
RS-232 Outputs
DOUT2
4
27
+
−
26
25
C3†
+
−
+ CBYPASS
− = 0.1 µF
C1
24
23
FORCEON
5
Autopowerdown
C4
−
V+
C2+
28
6
7
22
FORCEOFF
8
21
9
20
10
19
INVALID
ROUT2B
ROUT1
5 kΩ
DOUT3
11
18
ROUT2
5 kΩ
DIN3
12
Logic Outputs
17
ROUT3
5 kΩ
Logic Inputs
DIN2
13
16
ROUT4
5 kΩ
DIN1
14
15
ROUT5
5 kΩ
† C3 can be connected to V
CC or GND.
NOTES: A. Resistor values shown are nominal.
B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or
electrolytic capacitors are used, they should be connected as shown.
VCC vs CAPACITOR VALUES
VCC
C1
C2, C3, and C4
3.3 V ± 0.3 V
5 V ± 0.5 V
3 V to 5.5 V
0.1 µF
0.047 µF
0.1 µF
0.1 µF
0.33 µF
0.47 µF
Figure 6. Typical Operating Circuit and Capacitor Values
12
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Product Folder Link(s): TRS3243E
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
ESD Protection
TI TRS3243E devices have standard ESD protection structures incorporated on the pins to protect against
electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver
outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures
were designed to successfully protect these bus pins against ESD discharge of ±15-kV in all states: normal
operation, shutdown, and powered down. The TRS3243E devices are designed to continue functioning properly
after an ESD occurrence without any latchup.
The TRS3243E devices have three specified ESD limits on the driver outputs and receiver inputs, with respect to
GND:
• ±15-kV Human-Body Model (HBM)
• ±15-kV IEC61000-4-2, Air-Gap Discharge (formerly IEC1000-4-2)
• ±8-kV IEC61000-4-2, Contact Discharge
ESD Test Conditions
ESD testing is stringently performed by TI, based on various conditions and procedures. Please contact TI for a
reliability report that documents test setup, methodology, and results.
Human-Body Model (HBM)
The HBM of ESD testing is shown in Figure 7, while Figure 8 shows the current waveform that is generated
during a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage
of concern, and subsequently discharged into the DUT through a 1.5-kΩ resistor.
RD
1.5 kΩ
VHBM
+
−
CS
100 pF
DUT
Figure 7. HBM ESD Test Circuit
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Product Folder Link(s): TRS3243E
13
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
1.5
VHBM = 2 kV
I DUT (A)
1.0
0.5
DUT = 10-V 1-Ω Zener Diode
0.0
0
50
100
150
200
Time (ns)
Figure 8. Typical HBM Current Waveform
IEC61000-4-2 (Formerly Known as IEC1000-4-2)
Unlike the HBM, MM, and CDM ESD tests that apply to component level integrated circuits, the IEC61000-4-2 is
a system-level ESD testing and performance standard that pertains to the end equipment. The TRS3243E is
designed to enable the manufacturer in meeting the highest level (Level 4) of IEC61000-4-2 ESD protection with
no further need of external ESD protection circuitry. The more stringent IEC test standard has a higher peak
current than the HBM, due to the lower series resistance in the IEC model.
Figure 9 shows the IEC61000-4-2 model, and Figure 10 shows the current waveform for the corresponding
±8-kV contact-discharge (Level 4) test. This waveform is applied to a probe that has been connected to the DUT.
On the other hand, the corresponding ±15-kV (Level 4) air-gap discharge test involves approaching the DUT with
an already energized probe.
High-Voltage
DC Source
+
−
50−100 MΩ
330 Ω
RC
RD
CS
150 pF
DUT
Figure 9. Simplified IEC61000-4-2 ESD Test Circuit
14
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Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TRS3243E
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
I
(30A) 100%
(Vcontact = 8 kV)
I Peak
90%
(16A)
(8A)
10%
t
30 ns
60 ns
tr = 0.7 ns to 1 ns
Figure 10. Typical Current Waveform of IEC61000-4-2 ESD Generator
Machine Model (MM)
The MM ESD test applies to all pins using a 200-pF capacitor with no discharge resistance. The purpose of the
MM test is to simulate possible ESD conditions that can occur during the handling and assembly processes of
manufacturing. In this case, ESD protection is required for all pins, not just RS-232 pins. However, after PC
board assembly, the MM test is no longer as pertinent to the RS-232 pins.
Submit Documentation Feedback
Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TRS3243E
15
TRS3243E
SLLS789C – APRIL 2007 – REVISED SEPTEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Revision B (July 2009) to Revision C
Page
•
Deleted "VALID RIN RS-232 LEVEL" from INPUTS. ........................................................................................................... 3
•
Deleted "ROUT2B is active" RECEIVER STATUS and combined ROUT outputs. .............................................................. 3
•
Added New Table "ROUT2B and INVALID Outputs" defining truth table for ROUT2B and INVALID outputs. ................... 3
16
Submit Documentation Feedback
Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TRS3243E
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TRS3243ECDB
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS3243EC
TRS3243ECDBR
ACTIVE
SSOP
DB
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS3243EC
TRS3243ECDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS3243EC
TRS3243ECDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS3243EC
TRS3243ECPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RS43EC
TRS3243ECPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RS43EC
TRS3243ECRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
RS43EC
TRS3243EIDB
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS3243EI
TRS3243EIDBR
ACTIVE
SSOP
DB
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS3243EI
TRS3243EIDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS3243EI
TRS3243EIDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS3243EI
TRS3243EIPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RS43EI
TRS3243EIPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RS43EI
TRS3243EIPWRG4
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RS43EI
TRS3243EIRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
RS43EI
TRS3243EIRHBRG4
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
RS43EI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TRS3243ECDBR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SSOP
DB
28
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
TRS3243ECDWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
TRS3243ECPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
TRS3243ECRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
TRS3243EIDBR
SSOP
DB
28
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
TRS3243EIDWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
TRS3243EIRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TRS3243ECDBR
SSOP
DB
28
2000
367.0
367.0
38.0
TRS3243ECDWR
SOIC
DW
28
1000
350.0
350.0
66.0
TRS3243ECPWR
TSSOP
PW
28
2000
350.0
350.0
43.0
TRS3243ECRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
TRS3243EIDBR
SSOP
DB
28
2000
367.0
367.0
38.0
TRS3243EIDWR
SOIC
DW
28
1000
350.0
350.0
66.0
TRS3243EIRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
SCALE 1.500
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
26X 0.65
28
1
2X
10.5
9.9
NOTE 3
8.45
14
15
28X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.15
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
15
14
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
SEE SIDE WALL
DETAIL
SYMM
33
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
32X
0.5
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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